EE260: Digital Design, Spring 2018 11-Mar-18
Assignment review 1
EE 260: Introduction toDigital Design
Assignment Reviews
Yao ZhengDepartment of Electrical Engineering
University of Hawaiʻi at Mānoa
Overview
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Problem 6.14 Structural Model
Structural Model (cont.) Problem 6.15
EE260: Digital Design, Spring 2018 11-Mar-18
Assignment review 2
Instantiation Instantiation
Problem 6.18 Problem 6.19
Verilog Taskn Verilog function: a subroutine that
produces one outputn Verilog task: a subroutine that does not
return a result
Verilog Task
EE260: Digital Design, Spring 2018 11-Mar-18
Assignment review 3
Problem 7.19
Problem 7.26
Overview
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Problem 7.10
EE260: Digital Design, Spring 2018 11-Mar-18
Assignment review 4
MSI Comparator : 74x85 Problem 7.11
Parameterized ModuleParameterized Module
Problem 7.4 Problem 7.37