P89V51RD2
General description
The P89V51RD2 is an P89v51RD2 microcontroller with 64 kB Flash and 1024 bytes of
data RAM.
A key feature of the P89V51RD2 is its X2 mode option. The design engineer can
choose to run the application with the conventional P89v51RD2 clock rate (12 clocks per
machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice
the throughput at the same clock frequency. Another way to benefit from this feature
is to keep the same performance by reducing the clock frequency by half, thus
dramatically reducing the EMI.
The Flash program memory supports both parallel programming and in serial
In-System Programming (ISP). Parallel programming mode offers gang-programming
at high speed, reducing programming costs and time to market. ISP allows a device
to be reprogrammed in the end product under software control. The capability to
field/update the application firmware makes a wide range of applications possible.
The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash
program memory to be reconfigured even while the application is running.
1. Features
P89v51RD2 Central Processing Unit 5 V Operating voltage from 0 to 40 MHz 64 kB of on-chip Flash program memory with ISP (In-System Programming) and IAP (In-Application Programming) Supports 12-clock (default) or 6-clock mode selection via software or ISP SPI (Serial Peripheral Interface) and enhanced UART PCA (Programmable Counter Array) with PWM and Capture/Compare functions Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)
Three 16-bit timers/counters Programmable Watchdog timer (WDT) Eight interrupt sources with four priority levels Second DPTR register Low EMI mode (ALE inhibit) TTL- and CMOS-compatible logic levels Brown-out detection Low power modes Power-down mode with external interrupt wake-up Idle mode PDIP40, PLCC44 and TQFP44 packages
Block diagram
Pinning information
Pin description
VCC: Supply voltage.
GND: Ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each
pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high-impedance
inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus
during accesses to external program and data memory. In this mode, P0 has
internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
Table-3 Pin description ofP89V51RD2
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups. Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that use
16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function
Register. Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins,
they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (IIL) because of the pull-ups. Port 3 receives
some control signals for Flash programming and verification. Port 3 also serves the
functions of various special features of the P89V51RD2, as shown in the following
table.
Table-4 Special features of port 3 in P89V51RD2
RST: Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device. This pin drives High for 98 oscillator periods after the
Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state
of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low byte
of the address during accesses to external memory. This pin is also the program
pulse input (PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency
and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data memory. If desired, ALE
operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE
is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution
mode.
PSEN: Program Store Enable (PSEN) is the read strobe to external program
memory. When the AT89S51 is executing code from external program memory,
PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
EA/VPP: External Access Enable. EA must be strapped to GND in order to enable
the device to fetch code from external program memory locations starting at 0000H
up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally
latched on reset. EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash
programming.
XTAL1: Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
XTAL2: Output from the inverting oscillator amplifier.
Special Function Registers: A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 1. Note that not all of the addresses
are occupied, and unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return random data, and write
accesses will have an indeterminate effect.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two
priorities can be set for each of the five interrupt sources in the IP register.
Table -5 AUXR: Auxillary Register
Dual Data Pointer Registers: To facilitate accessing both internal and external
data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR
address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects
DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON
SFR. POF is set to “1” during power up. It can be set and rest under software control
and is not affected by reset.
Table -6 AUXR1: Auxilliary Register 1.
Memory Organization: MCS-51 devices have a separate address space for
Program and Data Memory. Up to 64Kbytes each of external Program and Data
Memory can be addressed.
Program Memory: If the EA pin is connected to GND, all program fetches are
directed to external memory. On the P89V51RD2, if EA is connected to VCC,
program fetches to addresses 0000H through FFFH are directed to internal memory
and fetches to addresses 1000H through FFFFH are directed to external memory.
Data Memory: The P89V51RD2 implements 256 bytes of on-chip RAM. The 128
bytes are accessible via direct and indirect addressing modes. Stack operations are
examples of indirect addressing, so the 256 bytes of data RAM are available as
stack space.
Watchdog Timer (One-time enabled with reset-out): The WDT is intended as a
recovery method in situations where the CPU may be subjected to software upsets.
The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR.
The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must
write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, it will increment every machine cycle while the oscillator
is running. The WDT timeout period is dependent on the external clock frequency.
When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT: To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled,
the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT
overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will
reset the device. When the WDT is enabled, it will increment every machine cycle
while the oscillator is running. This means the user must reset the WDT at least
every 16383 machine cycles. To reset the WDT the user must write 01EH and
0E1Hto WDTRST. WDTRST is a write-only register. The WDT counter cannot be read
or written. When WDT overflows, it will generate an output RESET pulse at the RST
pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best
use of the WDT, it MCS-51 devices have a separate address space for Program and
Data Memory. Up to 64K bytes each of external Program and Data Memory can be
addressed.
UART: The UART in the P89V51RD2 operates the same way as the UART in the
P89V51RD2.
Timer 0 and 1: Timer 0 and Timer 1 in the P89V51RD2 operate the same way as
Timer 0 and Timer 1 in the P89V51RD2.
Interrupts: The P89V51RD2 has a total of five interrupt vectors: two external
interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port
interrupt. These interrupts are all shown in Figure 1.
Each of these interrupt sources can be individually enabled or disabled by
setting or clearing a bit in Special Function Register IE. IE also contains a global
disable bit, EA, which disables all interrupts at once.
Note that Table 4 shows that bit position IE.6 is unimplemented. In the
P89V51RD2, bit position IE.5 is also unimplemented. User software should not write
1s to these bit positions, since they may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next
cycle.
Table -7 Interrupt Enable (IE) Register
Oscillator Characteristics: XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier that can be configured for use as an on-chip
oscillator, as shown in Figure 2.2(i). Either a quartz crystal or ceramic resonator may
be used. To drive the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 2.2(j). There are no
requirements on the duty cycle of the external clock signal, since the input to the
internal clocking circuitry is through a divide-by-two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.
Figure – 2.2(i) Oscillator Connections
Idle Mode: In idle mode, the CPU puts itself to sleep while all the on-chip
peripherals remain active. The mode is invoked by software. The content of the on-
chip RAM and all the special function registers remain unchanged during this mode.
The idle mode can be terminated by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally
resumes program execution from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected
write to a port pin when idle mode is terminated by a reset, the instruction following
the one that invokes idle mode should not write to a port pin or to external memory.
Power-down Mode: In the Power-down mode, the oscillator is stopped, and the
instruction that invokes Power down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power-down mode
is terminated. Exit from Power-down mode can be initiated either by a hardware
reset or by activation of an enabled external interrupt into INT0 or INT1. Reset
redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before VCC is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and stabilize.
Table- 8 Status of External Pins During Idle and Power-down
Modes.
Programming the Flash –Serial Mode: The Code memory array can be
programmed using the serial ISP interface while RST is pulled to VCC. The serial
interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high,
the Programming Enable instruction needs to be executed first before other
operations can be executed. Before a reprogramming sequence can occur, a Chip
Erase operation is required.
The Chip Erase operation turns the content of every memory location in the
Code array into FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal
needs to be connected across pins XTAL1 and XTAL2(Fig 2.2(k)). The maximum
serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With
a 33 MHz oscillator clock, the maximum SCK frequency is 2MHz.
POWER SUPPLY SECTION: This section is used for supplying the required power
to the system(fig-2.2(a)). The power supply section mainly consist of :
1. Step down transformer (12-0-12).
2. Electronic Rectifier.
3. Filter.
4. Regulator.
Fig 2.2(a) power supply section
The main building block of any electronic system is the power supply to provide
required power for their operation. For the microcontroller, keyboard, LCD, RTC,
GSM, +5V are required & for driving buzzer +12V is required. The power supply
provides regulated output of +5V & non-regulated output of +12V.
The 3 terminal IC7805 meets the requirement of +5V regulated. The secondary
voltage from the main transformer is rectified by electronic rectifier & filtered by
capacitor. This unregulated DC voltage is supplied to the input pin of regulator IC.
The IC used are fixed regulator with internal short circuit current limiting & thermal
shutdown capability.
Internal Block Digram
Serial Communication
In telecommunication and computer science, serial communication is the process of
sending data one bit at a time, sequentially, over a communication channel or
computer bus. This is in contrast to parallel communication, where several bits are
sent as a whole, on a link with several parallel channels. Serial communication is
used for all long-haul communication and most computer networks, where the cost
of cable and synchronization difficulties make parallel communication impractical.
Serial computer buses are becoming more common even at shorter distances, as
improved signal integrity and transmission speeds in newer serial technologies have
begun to outweigh the parallel bus's advantage of simplicity (no need for serializer
and deserializer, or SerDes) and to outstrip its disadvantages (clock skew,
interconnect density). The migration from PCI to PCI Express is an example.
Serial versus parallel
The communication links across which computers—or parts of computers—talk to
one another may be either serial or parallel. A parallel link transmits several
streams of data (perhaps representing particular bits of a stream of bytes) along
multiple channels (wires, printed circuit tracks, optical fibres, etc.); a serial link
transmits a single stream of data.
At first sight it would seem that a serial link must be inferior to a parallel one,
because it can transmit less data on each clock tick. However, it is often the case
that serial links can be clocked considerably faster than parallel links, and achieve a
higher data rate. A number of factors allow serial to be clocked at a greater rate:
Clock skew between different channels is not an issue (for unclocked asynchronous
serial communication links)
A serial connection requires fewer interconnecting cables (e.g. wires/fibres) and
hence occupies less space. The extra space allows for better isolation of the channel
from its surroundings
Crosstalk is less of an issue, because there are fewer conductors in proximity.
In many cases, serial is a better option because it is cheaper to implement. Many
ICs have serial interfaces, as opposed to parallel ones, so that they have fewer pins
and are therefore less expensive.
Asynchronous serial communication describes an asynchronous, serial transmission
protocol in which a start signal is sent prior to each byte, character or code word
and a stop signal is sent after each code word. The start signal serves to prepare
the receiving mechanism for the reception and registration of a symbol and the stop
signal serves to bring the receiving mechanism to rest in preparation for the
reception of the next symbol. A common kind of start-stop transmission is ASCII
over RS-232, for example for use in teletypewriter operation.
In the diagram, two bytes are sent, each consisting of a start bit, followed by seven
data bits (bits 0-6), a parity bit (bit 7), and one stop bit, for a 10-bit character frame.
The number of data and formatting bits, the order of data bits, and the transmission
speed must be pre-agreed by the communicating parties.
The "stop bit" is actually a "stop period"; the stop period of the transmitter may be
arbitrarily long. It cannot be shorter than a specified amount, usually 1 to 2 bit
times. The receiver requires a shorter stop period than the transmitter. At the end
of each character, the receiver stops briefly to wait for the next start bit. It is this
difference which keeps the transmitter and receiver synchronized.
The Universal Asynchronous Receiver Transmitter (UART)
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O
modules available in the PIC24H device family. The UART is a full-duplex, asynchronous
communication channel that communicates with peripheral devices and personal computers,
using protocols such as RS-232, RS-485, LIN 1.2 and IrDA®. The module also supports the
hardware flow control option with UxCTS and UxRTS pins and also includes the IrDA encoder
and decoder.
The primary features of the UART module are:
. Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX pins . Even, Odd or No Parity options (for 8-bit data) . One or two Stop bits . Hardware Auto-Baud feature . Hardware Flow Control option with UxCTS and UxRTS pins . Fully Integrated Baud Rate Generator with 16-Bit Prescaler . Baud Rates ranging from 10 Mbps to 38 bps at 40 MIPS . 4-deep First-In-First-Out (FIFO) Transmit Data Buffer . 4-deep FIFO Receive Data Buffer . Parity, Framing and Buffer Overrun Error Detection . Support for 9-bit mode with Address Detect (9th bit = 1) . Transmit and Receive Interrupts . Loopback mode for Diagnostic Support
. IrDA Encoder and Decoder Logic . LIN 1.2 Protocol Support . 16x Baud Clock Output for External IrDA Encoder/Decoder support
A simplified block diagram of the UART is shown in Figure 17-1. The UART module consists of
the following key important hardware elements:
. Baud Rate Generator
. Asynchronous Transmitter
. Asynchronous Receiver
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial
port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:
Bit Name Explanation of Function
7 SM0 Serial port mode bit 0
6 SM1 Serial port mode bit 1.
5 SM2 Mutliprocessor Communications Enable (explained later)
4 REN Receiver Enable. This bit must be set in order to receive characters.
3 TB8 Transmit bit 8. The 9th bit to transmit in mode 2 and 3.
2 RB8 Receive bit 8. The 9th bit received in mode 2 and 3.
1 TI Transmit Flag. Set when a byte has been completely transmitted.
0 RI Receive Flag. Set when a byte has been completely received.
SM0 SM1 Mode Description Baud Rate
0 0 0 shift register fOSC/ 12
0 1 1 8-bit UART variable
1 0 2 9-bit UART fOSC/64 or fOSC/32
1 1 3 9-bit UART variable
REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used.
TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software.
RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
ADC
ADC 0804
Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required
• Conversion Time < 100ms
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
Description
ADC0804 is one of the most commonly used analog to digital converter IC. In many applications
it is required to convert the output of the sensor, which is analogue in nature to a digital form.
The data in digital format can then be utilized for further processing by the digital processors.
Typical applications include sound processing, temperature processing etc.
The ADC0804 family are CMOS 8-Bit, successive-approximation A/D converters which use a
modified potentiometric ladder and are designed to operate with the 8080A control bus via three-
state outputs. These converters appear to the processor as memory locations or I/O ports, and
hence no interfacing logic is required.The differential analog voltage input has good
commonmode-rejection and permits offsetting the analog zero-input voltage value. In addition,
the voltage reference input can be adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
ADC0804 is a single channel analog to digital convertor i.e., it can take only one analog signal.
An ADC has n bit resolution (binary form) where n can be 8,10,12,16 or even 24 bits. ADC 0804
has 8 bit resolution. The higher resolution ADC gives smaller step size. Step size is smallest
change that can be measured by an ADC. For an ADC with resolution of 8 bits, the step size is
19.53mV (5V/255).
The time taken by the ADC to convert analog data into digital form is dependent on the
frequency of clock source. ADC0804 can be given clock from external source. It also has an
internal clock. However the conversion time cannot be more than110us. To use the internal clock
a capacitor and resistor is connected to pin 19 and 4 as shown in the circuit diagram. The
frequency is given by the relation f= 1/ (1.1RC). The circuit uses a resistance of 10k and a
capacitor of 150pF to generate clock for ADC0804. Vin, which is the input pin, is connected to a
preset to provide analog input.
Pin Diagram
Pin Description
1. CS, Chip Select: This is an active low pin and used to activate the ADC0804.
2. RD, Read: This is an input pin and active low. After converting the analog data, the ADC
stores the result in an internal register. This pin is used to get the data out of the ADC 0804 chip.
When CS=0 & high to low pulse is given to this pin, the digital output is shown on the pins D0-
D7.
3. WR, Write: This is an input pin and active low. This is used to instruct the ADC to start the
conversion process. If CS=0 and WR makes a low to high transition, the ADC starts the
conversion process.
4. CLK IN, Clock IN: This is an input pin connected to an external clock source.
5. INTR, Interrupt: This is an active low output pin. This pin goes low when the conversion is
over.
6. Vin+ : Analog Input .
7. Vin- : Analog Input. Connected to ground.
8. AGND: Analog Ground.
9. Vref/2: This pin is used to set the reference voltage. If this is not connected the default
reference voltage is 5V. In some application it is required to reduce the step size. This can be
done by using this pin.
10. DGND: Digital Ground.
11-18. Output Data Bits (D7-D0).
19. CLKR: Clock Reset.
20. Vcc: Positive Supply
Detailed DescriptionThe functional diagram of the ADC0802 series of A/D converters operates on the successive
approximation principle (see Application Notes AN016 and AN020 for a more detailed
description of this principle). Analog switches are closed sequentially by successive-
approximation logic until the analog differential input voltage [VlN(+) - VlN(-)] matches
a voltage derived from a tapped resistor string across the reference voltage. The most significant
bit is tested first and after 8 comparisons (64 clock cycles), an 8-bit binary code
(1111 1111 = full scale) is transferred to an output latch.The normal operation proceeds as
follows. On the high-to-low transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set high. As long as the CS input and
WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a lowto- high transition. After the
requisite number of clock pulses to complete the conversion, the INTR pin will make a high-to-
low transition. This can be used to interrupt a processor, or otherwise signal the availability of a
new conversion. A RD operation (with CS low) will clear the INTR line high again The device
may be operated in the free-running mode by connecting INTR to the WR input with CS = 0. To
ensure start-up under all possible conditions, an external WR pulse is required during the first
power-up cycle. A conversion-in-process can be interrupted by issuing a second start command.
The first diagram shows how to start a conversion. Also you can see which signals are to be
asserted and at what time to start a conversion. So looking into the timing diagram FIGURE
10A. We note down the steps or say the order in which signals are to be asserted to start a
conversion of ADC. As we have decided to make Chip select pin as low so we need not to bother
about the CS signal in the timing diagram. Below steps are for starting an ADC conversion. I am
also including CS signal to give you a clear picture.
Once the conversion in ADC is done, the data is available in the output latch of the ADC.
Looking at the FIGURE 10B which shows the timing diagram of how to read the converted
value from the output latch of the ADC. Data of the new conversion is only avalable for reading
after ADC0804 made INTR pin low or say when the conversion is over. Below are the stepts to
read output from the ADC0804.
Make chip select (CS) pin low.
Make read (RD) signal low.
Read the data from port where ADC is connected.
Make read (RD) signal high.
Make chip select (CS) high.
Relays
A relay is electrically controllable switch widely used in industrial controls,automobiles
and appliances. It allows the isolation of two separate sections of a system with 2
different voltages sources. For example , a +5v system can be isolated from a 120v
system by placing a relay in between them. One such relay is called Electromechanical
relay(EMR).The EMR have 3 components: the coil, spring and contacts. When current
flows through the coil, a magnetic field is created around the coil (coil is energized),
which causes the armature to be attracted to the coil. The armature’s contact acts like
switch and closes or opens the circuit.when the coil is not energized,a spring pulls the
armature to its normal state of open or closed. There are 3 types of relays
1.SPST(single pole single throw)- (Single Pole Single Throw Relay) an electromagnetic
switch, consist of a coil (terminals 85 & 86), 1 common terminal (30), and one normally
open terminal (87). It does not have a normally closed terminal like the SPDT relay, but
may be used in place of SPDT relays in all diagrams shown on this site where terminal
87a is not used.
2. SPDT(single pole double throw)- (Single Pole Double Throw Relay) an
electromagnetic switch, consist of a coil (terminals 85 & 86), 1 common terminal (30), 1
normally closed terminal (87a), and one normally open terminal (87) (Figure 1).
When the coil of an SPDT relay (Figure 1) is at rest (not energized), the common
terminal (30) and the normally closed terminal (87a) have continuity. When the coil is
energized, the common terminal (30) and the normally open terminal (87) have
continuity.
The diagram below center (Figure 2) shows an SPDT relay at rest, with the coil not
energized. The diagram below right (Figure 3) shows the relay with the coil energized.
As you can see, the coil is an electromagnet that causes the arm that is always connected
to the common (30) to pivot when energized whereby contact is broken from the
normally closed terminal (87a) and made with the normally open terminal (87).
When energizing the coil of a relay, polarity of the coil does not matter unless there is a
diode across the coil. If a diode is not present, you may attach positive voltage to either
terminal of the coil and negative voltage to the other, otherwise you must connect
positive to the side of the coil that the cathode side (side with stripe) of the diode is
connected and negative to side of the coil that the anode side of the diode is connected.
3. DPDT(Double pole Double throw)- (Single Pole Single Throw Relay) an
electromagnetic switch, consist of a coil (terminals 85 & 86), 1 common terminal (30),
and two normally open terminals (87 and 87b). Dual make SPST relays (Figure 4) are
used to power two circuits at the same time that are normally isolated from each other,
such as parking lamp circuits on German automobiles.
The diagram below center (Figure 5) shows a dual make SPST relay at rest, with the coil
not energized. The diagram below right (Figure 6) shows the relay with the coil
energized. The coil is an electromagnet that causes the arms that are always connected to
the common (30) to pivot when energized whereby contact is made with the normally
open terminals (87 and 87b).
In choosing a relay the following characteristics need to be considered:
1.The contacts can be normally open (NO) or normally closed (NC). In the NC type, the
contacts are closed when the coil is not energized .In NO, contacts are open when coil is
not energized.
2. There can be 1 or more contacts.
3. The voltage and current needed to energized the coil. The voltage can vary from a few
volts to 50 volts, while the current can be from few mA to 20 mA. The relay has a
minimum voltage, below which the coil will not be energized. This minimum voltage is
called the “pull-in” voltage.
4. The maximum DC/AC voltage and current that can be handled by the contacts.
Solid-state relay
Another widely used relay is the solid state relay. In this relay, there is no coil, spring, or
mechanical contact switch. The entire relay is made out of semiconductor materials.
Because no mechanical parts are involved in solid state relays, their switching response
time is much faster than that of electromechanical relays. Another problem with the
elctromechanical relay is its life expectancy. The life cycle for electromechanical relay
can Vary from a few hundred thouasnd to few million operations. Wear and tear on the
contact points can cause the relay to malfunction after a while solid state relays have no
limitations. Extremely low input current and small packaging make solid –state relay
ideal for logical switching.
SOFTWARES
Embedded C using KEIL IDE software.
The system program written in embedded C will be stored in Microcontroller .
The following are some of the major reasons for writing programs in C instead of
assembly
It is easier and less time consuming to write in C than assembly.
C is easier to modify and update.
You can use code available in function libraies.
C code is portable to other microcontrollers with little or no modification.
Keil development tools for the P89V51RD2 Microcontroller Architecture support every
level of software developer from the professional applications engineer to the student just
learning about embedded software development.
The industry-standard Keil C Compilers, Macro Assemblers, Debuggers, Real-time
Kernels, Single-board Computers, and Emulators support all P89V51RD2 derivatives and
help you get your projects completed on schedule.
The Keil P89V51RD2 Development Tools are designed to solve the complex problems
facing embedded software developers. Is this possible if we use hard reset (Logic 1 Pulse
with some delay) by using ISR and one Port Pin Connected to RESET Pin? so that
Controller can RESET itself by Applying RESET signal by ISR. I mean Software cum
Hardware RESET!
Flash magic is used to Dump the code to microcontroller from PC.
CIRCUIT DIAGRAM
Transmitter
Reciever
GLOBAL SYSTEM FOR MOBILE COMMUNICATION
The Global System for Mobile Communication (GSM: original from group special
mobile) is the most popular standard for mobile phones in the world. From the point of view of
the consumers, the key advantage of GSM systems has been higher digital voice quality and low
cost alternatives to making calls such as the Short Message Service (SMS). The advantage for
network operator has been the ability to deploy equipment from different vendors because the
open standard allows network operators to offer roaming services which mean subscribers can
use their phones all over the world.
2.1.1History of GSM:
The growth of cellular telephone systems started in the early 1980s, particularly in
Europe. The lack of a technological standardization promoted the European conference of postal
and telecommunications administrations (CEPT) to create the groupe special mobile (GSM) in
1982 with the objective of developing a standard for a mobile telephone system that could be
used across Europe.
In 1989, GSM responsibility was transferred to the European Telecommunications Standard
Institution (ETSI), and phase I if the GSM specifications were published in 1990. The first GSM
network was launched in 1991 by radiolinja in Finland. By the end of 1993, over a million
subscribers were using GSM phone networks being operated by 70 carriers across 48 countries.
2.1.2 Radio interface
GSM is a cellular network, which means that mobile phones connect to it by searching
for cells in the immediate vicinity. GSM networks operate in four different frequency ranges.
Most GSM networks operate in the 900 MHz or 1800 MHz bands. Some countries in the
Americas (including Canada) use the 850 MHz and 1900 MHz bands because the 900 and 1800
MHz bands because the 900 and 1800 MHz frequency bands were already allocated.
The rarer 400 and 450 MHz frequency bands are assigned in some countries, notably
Scandinavia, were these frequencies were these frequencies were previously used for first-
generation systems.
In the 900 MHz band the uplink frequency band is 890-950 MHz, and the downlink
frequency band is 935-960 mhz. this 25 MHz bandwidth is subdivided into 124 carrier frequency
channels, each spaced 200 kHz apart. Time division multiplexing is used to allow eight full-rate
or sixteen half-rate speech channels per radio frequency channel. There are eight radio timeslots
(given eight burst periods) grouped into what is called a TDMA frame. Half rate channels use
alternate frames in the same timeslot. The channel data rate is 270.833 Kbit/s, and the frame
duration is 4.615ms.
The transmission power in the handset is limited to a maximum of 2 watts in
GSM850/1900.
GSM has used a variety of voice codecs to squeeze 3.1khz audio into between 6 and 13
Kbits/s. Originally, two codecs, named after the types of data channel they were allocated, called
“Full Rate”(13 Kbits/s) and “Half Rate”(6 Kbits/s). These used a system based upon Linear
Predictive Coding (LPC). In addition to being efficient with bit rates, these codecs also made it
easier to identify more important parts of audio, allowing the air interface layer to prioritize and
better protect these parts of the signal.
2.1.3 Subscriber Identity Module
One of the key features of GSM is the subscriber identity module (SIM), commonly
known as SIM card. The SIM is detachable smart card containing the user’s subscription
information and phonebook. This allows user to retain his or her information after switching
handsets. Alternatively, the user can also change operators while retaining the handset simply by
changing SIM. Some operators will block this is by allowing the phone to use only a single SIM,
or only a SIM issued by them; this practice is known as SIM locking, and is illegal in some
countries.
2.1.4 GSM Security
GSM was designed with a moderate level of security. The system was designed to
authenticate the subscriber using shared-secret cryptography. Communication between the
subscriber and the base station can be encrypted. The security model therefore offers
confidentially and authentication, but limited authorization capabilities, and no non-repudiation.
2.1.5GSM Modems:
A GSM modem is a specialized type of modem which accepts a SIM card, and operates
over a subscription to a mobile operator, just like a mobile phone. From the mobile operator
perspective, a GSM modem looks just like a mobile phone.A GSM modem can be a dedicated
modem device with a serial, USB or Bluetooth connection, or it may be a mobile phone that
provides GSM modem capabilities.
A GSM modem (fig 2.1) exposes an interface that allows applications such as Now SMS
to send and receive messages over the modem interface. The mobile operator charges for this
message sending and receiving as if it was performed directly on a mobile phone. To perform
these tasks, a GSM modem must support an "extended AT command set" for sending/receiving
SMS messages. GSM modems can be a quick and efficient way to get started with SMS, because
a special subscription to an SMS service provider is not required.
The mobile operator charges for this message sending and receiving as if it was
performed directly on a mobile phone. In most parts of the world, GSM modems are a cost
effective solution for receiving SMS messages, because the sender is paying for the message
delivery.
Historically, we have recommended GSM modems from manufacturers such as
Multitech, Falcom, Siemens (now Cinterion), iTegno and Wavecom. While these manufacturers
make very good GSM modems, there are currently a lot of GSM/3G USB stick modems
available on the market, which are less expensive, and in many cases significantly faster than
older GSM modems. The modem interfaced in our project is SIMCOM SIM300 module that
connects to the specific application and the air interface. As SIM300 can be integrated with a
wide range of application.
2LCD [LIQUID CRYSTAL DISPLAY]:
LCDs have become very popular over recent years for information display in many ‘smart’
appliances due to the following reasons:
1. The declining prices of LCD2.The ability to display numbers, characters,and graphics3.Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task of refreshing the LCD4.Ease of programming for characters and graphics
They are usually controlled by microcontrollers. They make complicated equipment easier to operate .LCDs come in many shapes and sizes but the most common is the 16 character x 2 line display with back light. It requires only 16 connections – eight bits for data (which can be reduced to four if necessary) and three control lines. It runs with a 5V DC supply and only needs about 1mA of current.The display contrast can be varied by changing the voltage into pin 3 of the display, usually with a pot.
Table-1pin description
Table-2 Initializing by Instruction:
Figure-2.3 Interfacing Diagram:
2.2.3MAX232:
The MAX232 from Maxim was the first IC which in one package contains the necessary drivers
(two) and receivers (also two), to adapt the RS-232 signal voltage levels to TTL logic. It became
popular, because it just needs one voltage (+5V) and generates the necessary RS-232 voltage
levels (approx. -10V and +10V) internally. This greatly simplified the design of circuitry.
Circuitry designers no longer need to design and build a power supply with three voltages (e.g. -
12V, +5V, and +12V), but could just provide one +5V power supply, e.g. with the help of a
simple 78x05 voltage converter. The MAX232 has a successor, the MAX232A. The MAX232 is
an integrated circuit that converts signals from an RS-232 serial port to signals suitable for use in
TTL compatible digital logic circuits. The MAX232 is a dual driver/receiver and typically
converts the RX, TX, CTS and RTS signals. The pin diagram of max232 is as shown in the fig
2.2(b).
The drivers provide RS-232 voltage level outputs (approx. ± 7.5 V) from a single + 5 V supply
via on-chip charge pumps and external capacitors. This makes it useful for implementing RS-232
in devices that otherwise do not need any voltages outside the 0 V to + 5 V range, as power
supply design does not need to be made more complicated just for driving the RS-232 in this
case.
The receivers reduce RS-232 inputs (which may be as high as ± 25 V), to standard 5 V TTL
levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of 0.5 V.
The later MAX232A is backwards compatible with the original MAX232 but may operate at
higher baud rates and can use smaller external capacitors 0.1 μF in place of the 1.0 μF capacitors
used with the original device.
The newer MAX3232 is also backwards compatible, but operates at a broader voltage range,
from 3 to 5.5V.
FEATURES:
Operates from a Single 5-V Power Supply with 1.0uF Charge-pump capacitors.
Operates upto 120 kbit/s.
Two drivers and two Receivers.
±30-V Input Levels.
Low supply current 8mA typical.
ESD protection exceeds JESD 22.
2000-V human-body model (A114-A).
Upgrade with improved ESD (15-kV HBM) and 0.1uF charge-pump capacitors is
available with the MAX202.
Applications
EIA-232-F , Battery-Powered Systems.
Terminals , Modems, and Computers.
Figure-2.2(b) pin diagram of max232:
Figure-2.2(c) logic diagram of max232:
VOLTAGE LEVELS: When a MAX232 IC receives a TTL level to convert, it changes a TTL
Logic 0 to between +3 and +15V, and changes TTL Logic 1 to between -3 to -15V, and vice
versa for converting from RS232 to TTL. This can be confusing when you realize that the RS232
Data Transmission voltages at a certain logic state are opposite from the RS232 Control Line
voltages at the same logic state). The logic diagram of max232 is shown in fig 2.2(c).
Figure-2.2(d) TYPICAL OPERATING CIRCUIT of max232:
DESCRIPTION:
The MAX232 is a dual driver/receiver (fig 2.2(d)) that includes a capacitive voltage generator to
supply TIA/EIA-232 voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-
232-F inputs to 5-V TTL/CMOS levels.
These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept
±30-V inputs(fig2.2(e)).
Each driver converts TTL/CMOS input levels into TIA/EIA-232 levels.
Figure-2.2(e)Interfacing Diagram
Max232