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Session 10: OPAMP APPLICATIONSPrakash Biswagar
Asst. Professor
E&C Engg. Dept
RV College of Engineering, Bangalore
INTRODUCTION: OPAMP is a very versatile IC.The name itself indicates that almost
all the mathematical operations (e.g. Addition, substraction, multiplication, averaging,integration & differentiation etc) can be easily realized using this IC chip. Analog
computers, which existed before the onset of digital computers, were built using these
ICs only. Also almost all the circuits that are realized using discrete devices like BJT,
FET etc can be designed using OPAMP.Applications of the OPAMP can be broadlyclassified as open loop & closed loop depending on whether there is a feedback
connection between the input and output. Some of the important and widely used circuits
are discussed here.
INSTRUMENTAION AMPLIFIER: Basically it is a difference amplifier. It isemployed to control the industrial parameters like pressure; temperature etc. A transducer
converts these parameters into equivalent electrical voltage. This is then applied to theinstrumentation amplifier, which boosts the signal level to drive the display devices.
An instrumentation amplifier must meet the following requirements.
(i)Low-level signal amplification:The instrumentation amplifiers should amplify signals of very small amplitude. Hence
they should have very high gain. Also, the gain should be stable.
(ii)Low noise:
As the signals involved are very weak, the instrumentation amplifiers must contributeminimum noise, otherwise, it may interfere with the signals. The instrumentation
amplifier beng a differential amplifier they are capable of rejecting the noise common toboth the inputs.
(iii)Low thermal drift.
The environment in which the instrumentation amplifiers are employed may have lot of
temperature fluctuations. Hence the parameters of these amplifiers must be thermallystable.
(iv) High input impedance:
To avoid loading effect on the input source, the instrumentation amplifiers must have
high input impedance.
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THREE OPAMP INSTRUMENTATION AMPLIFIERS:
This is a high impedance amplifier using cross-coupled difference amplifiers. A1 & A2 in
the above figure are non-inverting amplifiers. As all the OPAMPS are assumed to have
infinite Zi ,their i/p current is zero.EXPRESSION FOR VOLTAGE GAIN:From the above figure, we can write
12 & VVVV BA ==
2R
VVI BA
= --------------- (1)
But 12 & VVVV BA ==
2
12
R
VVI
= --------------------- (2)
But 022011 & VVVV==
Since A1 &A2 are unity gain amplifiers.
1
022
1
101
2
21
R
VV
R
VV
R
VVI
=
=
= ---------- (3)
2
2
1
212
2
2
1
1
1
1
01 11
R
VV
RRR
V
R
V
R
V
R
V
+=+= ----- (4)
2
2
11
2
101 1 V
R
RV
R
RV
+= ---------------------- (5)
Similarly,
2
212
1
2
2
2
1
1
2
1
02 11 V
RRR
V
R
V
R
V
R
V
R
V
++=+=
2
2
11
2
102 1 V
R
RV
R
RV
++= ------------------ (6)
Output voltage of the first stage is
( )12
2
1
2
2
1
1
2
1
2
2
1
1
2
1
0102
2111 VV
R
RV
R
RV
R
RV
R
RV
R
RVV
+=+
+
++= -----------
(7)
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Gain of the first stage
2
1
12
102
1
21
R
R
VV
VVA OV +=
= -------------------------- (8)
Second stage is a differential amplifier with a gain of
=2VA3
4
R
R------------------------------------------- (9)
Overall gain of the instrumentation amplifier is
3
4
2
1
21
21
R
R
R
RAAA
VVV
+== ---------- (10)
Hence by varying R2, the overall gain can be linearly varied.
Output voltage, ( )210 VVAV V = ---------- (11)ADVANTAGES OF INSTRUMENTATION AMPLIFIERS:
The gain can be adjusted precisely by varying a single resistor.
Input impedance is very high as it depends on two unity gain buffers A 1&A2This circuit can reject any common mode signals such as noise due to high CMRR of the
three amplifier stages A1, A2, &A3.
P1. Calculate the gain of the configuration shown below.
SOLN: Overall gain of this circuit is
3
4
2
121R
R
R
RAV
+=
Substituting the given values,
29210
22
2
1021 =
+=VA
P2. For the instrumentation amplifier of p1 above, calculate the output voltage if
V1 = 2mV & V2 = 1mV.
SOLN: (i) Referring to above fig, output amplifier A1 is
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2
2
11
2
102 1 V
R
RV
R
RV
++=
Substituting the different values
mVmVmVV 412
10
122
1002 =
++= -------------- (1)
(ii) Again from the above figure,
2
2
11
2
101 1 V
R
RV
R
RV
+=
Substituting the values,
mVmVmVV 712
102
2
10101 =
+=
(iii) V01 &V02 are the inputs to the difference amplifier A3. Output voltage can be
calculated using superposition theorem.
(a)Assume V02 = 0 & calculate the output V0 only
V0= .4.1572210
22
10
2211
01
43
4
3
4 mVmVVRR
R
R
R=
+
+=
+
+
(b) Assume V01 = 0 & calculate the output V0due to V02 only.
( )mVmVVR
RV 8.8)4
10
2202
3
4''
0===
(iv) Total output voltage,
mVVVV 2.298.84.15''
0
'
00 =+=+=
INSTRUMENTATION AMPLIFIER USING TRANSDUCER BRIDGE:
Above figure shows a differential instrumentation amplifier using a transducer bridge.
Resistance RT is a resistance of which changes proportional with some physical quantity
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Such as temperature, pressure, light intensity etc. RT is the resistance of the transducer &
R is the change in the resistance RT.A DC or AC voltage source can excite the bridge. Under balanced conditions
ba VV = ------------------ (1)
Butdc
TA
Aa V
RR
RV
+=
dcCB
Bb V
RR
RV
+=
( ) ( ) dcCB
B
dc
TA
A VRR
RV
RR
R
+=
+
TBBACABA RRRRRRRR +=+
TBCA RRRR =
A
T
B
C
R
R
R
R= ------------------------ (2)
(Under balanced condition)
The values of RA,RB& RC are such that they are equal to RT at a particular value of the
physical quantity being measured. This value is decided by the designer depending on the
transducer characteristics.
INSTRUMENTATION AMPLIFIER WITH DUAL OP-AMPS:
The above figure shows an instrumentation amplifier using only two opamps.
1.A1 is a non-inverting amplifier. Hence, its output voltage is given by
1
4
3
01 1 inVR
RV
+= ---------------------------------------- (1)
2. V01 is applied to the inverting terminal of A2.Hence, its output voltage can be obtained
with the help of superposition theorem by considering V01 & V02 separately.
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3. Output voltage considering only V01,
1
4
3
1
201
1
2'
0 1 inVR
R
R
RV
R
RV
+== --------------------- (2)
Output voltage considering only Vin2 is--------------------------------------- (3)
4. Output voltage,"
0
'
00VVV += , substituting the values,
2
1
21
4
3
1
20 11 inin V
R
RV
R
R
R
RV
++
+=
=
+
+
+ 11
1
1
2
1
4
3
2
1
2 Vin
R
R
RR
VR
Rin ------------------ (4)
5. The circuit works as a true difference amplifier if
4
3
2
1
R
R
R
R=
So that )(1 121
2
0 inin VVR
R
V
+= -------------------- (5)
OPAMP AS A COMPARATOR:
Comparator is basically a circuit which compares the signals applied to its inputs.
2
1
2''0 1 inV
RRV
+=
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Let the voltage applied at the non-inverting input be denoted by VP & that applied at the
inverting terminal be VN.Then the output voltage V0 is,
ifVV OH =0 VP > VN
ifVV L = 00 VP0
= LVV 00 for Vd
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through resistors R1&R2 almost zero and hence the voltage drop across them will be
nearly zero. Hence V1=Vin & V2 = Vref .The differential input voltage is,
refind VVVVV == 21 ------------------------ (1)
When ,refin VV < the inverting terminal is at higher potential than the non-invertingterminal is at higher potential than the non-inverting terminal. As the Vd is negative,
OPAMP output will swing to -Vsat.
Similarly, for ,refin VV > Vd i
s positive & output will swing to +Vsat .The waveforms are shown below.
For OPAMPs working with single power supply, the comparator output will be unipolar.are shown below.
SCHMITT TRIGGER:
(REGENERATIVE COMPARATOR)
This circuit uses a positive or regenerative feedback.
The resistance divider network R1 R2 facilitates for positive feedback.
OPERATION OF THE CIRCUIT:
The voltage developed across R2 will serve as the reference voltage.
( ) 021
2
1 VRR
RV
+= ---------------------------(1)
There are two different triggering levels for Schmitt-Trigger i.e. UTP& LTP.The output voltage V0 switches whenever the input voltage crosses the value of V i,which forces a transition from +Vsat to -Vsat in the output voltage. Similarly the lower
trigger level is the value of Vin ,which forces a transition from +Vsat to -Vsat .Thesethreshold levels can be given as,
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)3()(
)2(
21
2
21
2
+
=
+
=
sat
sat
VRR
RLTP
VRR
RUTP
The waveforms & the transfer characteristics for the Schmitt trigger are shown below.
HYSTERISIS:
The hysteresis or backlash for a comparator occurs when a positive feedback isemployed. It is defined as the difference between the turn-on and turn-ff input voltage.
Due to hysteresis, the comparator makes transitions between high state and low state.
LTPUTPVH =
( )[ ]
( )
=
+
=
+
=
.
21
2
21
2
2 sat
satsat
VRR
R
VV
RR
R
P1: Design a Schmitt trigger using IC741, such that the hysteresis will be 6V. Use supply
of .10V
We have,
( )satH V
RR
RV
+=
21
22
Let VVsat 10=
( )
( )
==
=
=
+=
=+
+
=
KR
KLetR
RR
RRR
RR
R
RR
R
3.4107
310
7
3
3.03.0
3.0
102
6
2
1
12
212
21
2
21
2
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In the OPAMP comparator shown above, supply voltages are CCsat VVV 9.0&12 = if
a sine wave of 10V is applied, calculate the threshold levels & plot the input & output
waveforms.
SOLN: We have
( ) VVRR
RUTP sat 16.2)129.0
41
1
21
2 =+
=+
=
( )satV
RR
RLTP
+=
21
2
=( )
( ) V16.2129.041
1=
+
The waveforms are shown above.
CLIPPING CIRCUITS USING OPAMP:
Clipping circuits are used for removing a portion of the input signal. Clippers can be
positive or negative depending on which part of the input signal is clipped off.
POSITIVE CLIPPER:
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Above fig. Shows the circuit diagram & waveform for a positive clipper usingOPAMP.The potentiometer P is used to adjust the reference voltage.
The reference voltage Vref has been adjusted to say +1.5V, by using the pot. P.
When Vi is positive but less than Vref , the diode D will conduct as it is forward biased. Ifthe diode is assumed to be identical, it will act as a short circuit & force the circuit to
operate as a voltage follower.
inVV = 0 for refin VV < ----------- (1)
As soon as the positive input exceeds V ref , the diode is reverse biased. Hence it acts like
an open circuit and isolates the OPAMP output from the load .The output voltage is equalto Vref.
refVV = 0 for refin VV > --------- (2)
During the negative half cycle of the input, the diode is forward biased & hence conducts
to make inVV =0 .
inVV = 0 --------------- 0
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Asst. Professor
E&C Engg. Dept
RV College of Engineering, Bangalore
NEGATIVE CLIPPER:
The above figures show the circuit diagram & waveforms for a clipper circuit. Here the
diode is reversed compared to +ve clipper. The negative half cycle of the input gets
clipped partially or fully depending on the magnitude of the Vref
CLAMPERS USING OPAMP:A clamper is a circuit used to shift dc level of the input signal. It adds a desired dc levelto the ac input voltage. If the added dc level is positive, it is called as a +ve clamper.
Otherwise negative clamping if the added dc level is negative.
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The above figures show the circuit diagram & waveforms for a clamper circuit. The
potentiometer p is used to vary the reference voltage applied to the non-inverting
terminal of the OPAMP.The waveforms to be clamped is applied to the inverting terminal & the dc reference
voltage is applied to the non-inverting terminal of the OPAMP.As both the inputs arenon-zero; the circuit can be analyzed using superposition theorem.
With only +Vref given to the non-inverting terminal (assuming Vin =0), the OPAMPoutput is positive, the diode D is forward biased and the output is,
V0 =Vref
When Vin is +ve, the OPAMP output will be negative. The diode will be reverse biasedand the capacitor cant discharge, as there is no discharge path for it. Output becomes
V0=Vm +Vin
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Total output is
V0 = V0+V0=Vref + Vm +Vin
In this expression Vref +Vm is the fixed dc level added to the input signal.
Note: In the above circuit, a battery V ref can also be used instead of the pot. For negative
clamping, the is to be reverse biased.
ABSOLUTE VALUE OUTPUT CIRCUIT:This circuit is used for wave shaping of the input signals. Output of this circuit will be
always positive, irrespective of the polarity of the input signal.
PEAK DETECTOR USING OPAMP:
This is a non-linear application of the OPAMP.Output of this circuit fllows the peak
value of the input signal and retain it infinitely. Peak detectors can be positive ornegative type.
Positive peak detector:
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Above figures show the circuit diagram equivalent circuits and waveforms.
Operation of the circuit:
The OPAMP workas as a voltage follower & hence the gain is 1.Diode D will be
forward biased only in the positive half cycle of the input, hence this circuit is sensitivity
only positive input voltages.Diode D is assumed to be ideal and the output is taken across the capacitor. i.e. V0 =
VCC.Track mode:
Initially capacitor is discharged i.e. V0 = 0. Hence in the first positive half cycle of the
input, the diode is forward biased and the capacitor charges to the +ve peak of the input.
Hold mode:
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Now as the Vin decreases, diode is reverse biased. There is no way for the capacitor to
discharge; hence it holds the peak value of Vin.
In the next positive half cycle, diode is forward biased as soon as V in rises above thecapacitor voltage. Thus the capacitor now charges to a new higher peak value as shown in
fig (b) above. It should be noted that the capacitor will charge only to a new higher value.
If the new peak value of the input is less than the existing VC, then the output will notchange. This is because the diode remains reverse biased.
The MOSFET switch across the capacitor is to reset the circuit. By turning on this switch
momentarily, the capacitor can be discharged completely.By reversing the diode, the same circuit can work as a negative peak detector.
Note: Peak detectors are used in instrumentation, AM detectors etc.
SAMPLE & HOLD CIRCUIT USING OPAMP:
The sample & hold circuit is used to hold the sampled value of the input signal for a
specified period of time. Thus S/H operation has two different processes: sampling
the input signal and holding the latest sample value.
BASIC SAMPLE & HOLD CIRCUIT:
The above figure shows the minimum circuitry required for a sample & hold circuit. Thecircuit operation in either of the modes (sampling & holding) depending on the position
of the switch.
Sampling mode:
In this mode, the switch is in the closed position and the capacitor charges to the
instantaneous input voltage.Hold mode:
In this mode, the switch is in the open position. The capacitor is now disconnected fromthe input. As there is no path for the capacitor to discharge, it will hold the voltage on it
just before opening the switch. The capacitor will hold this voltage till the next sampling
instant.
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Figures above show the sample and hold circuit using OPAMP and the relevant
waveforms. The MOSFET driven by a control voltage VC acts as a switch.
Operation:
When VC is high, MOSFET is turned ON and acts like a closed switch. The capacitor
charges through the MOSFET to the instantaneous input voltage. As soon as V C =0, the
MOSFET turns off and the capacitor is disconnected from OPAMP1 output capacitorcant discharge through amplifier A2 due to its high input impedance. This is the hold
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mode and the capacitor holds the latest sample value. Waveforms for both these modes
have been shown above.
Applications:
In the pulse modulation schemes
In ADC circuits.
ACTIVE FILTERS USING OPAMP:
Filters are frequency selective circuits.They are required to pass a specific band offrequencies and attenuate frequencies outside the band. Filters using an active device like
OPAMP are called active filters.Other way to design filters is using passive components
like resistor, capacitor and inductor.
ADVANTAGES OF ACTIVE FILTERS:
1. Possible to incorporate variable gain
2. Due to high Zi & Z0 of the OPAMP, active filters donot load the input source or
load.3. Flexible design.
FREQUENCY RESPONSE OF FILTERS:
Gain of a filter is given as,
)1(0
=iV
VG
Ideal & practical frequency responses of different types of filters are shown below.
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I-ORDER LPF:
In I order LPF which is also known as one pole LPF. Butterworth filter and itsfrequency response are shown above. This circuit uses a RC & values decide the cut-
off frequency of the filter, where as the resistors R1 & RF will decide its gain in passband. As the OPAMP is used in the non-inverting configuration, the closed loop gain
of the filter is given by
1
1R
RA FVF +=
EXPRESSION FOR THE GAIN OF THE FILTER:
Voltage across the capacitor is,
)1(1
= inCC
VjXR
jX
V
Reactance of the capacitor is,
fC
XC2
1=
Equation (1) becomes
)2(
21
2
2
1
2
1
1
=
=
=
j
fRC
V
jfRC
jV
fCjR
VfC
j
V ininin
=( )fRCj
Vin
21+
Output of the filter is
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+
=
+
+==
H
VF
in
inFVF
f
fj
A
V
V
fRCj
V
R
RVAV
1
211
0
1
10
Where fH = cut-off frequency.
DESIGN PROCEDURE:
Step1: Choose the cut-off frequency fH
Step2: Select a value of C (Approximately between o.001 & 0.1F)
Step3: Calculate the value of R using
CfR
H2
1=
Step4: Select resistors R1 & R2 depending on the desired pass band gain.
Eg1. For a first ordr Butterworth LPF, calculate the cut off frequency if R=10K &
C=0.001F.Also calculate the pass band voltage gain if R1=10K RF =100K .
SOLN: (1) KHzRC
fH 915.1510001.010102
1
2
163=
==
(2) 1110
10011
1
=+=+=K
K
R
RA FVF
Eg2. Design a I order LPF for the following specification
(i) Pass band voltage gain = 2
(ii) Cut off frequency, f C = 10KHz.
Soln: Given AVF = 2Let RF = 10K
(i)
===
+=
KRRR
R
R
RA
FF
FVF
10&1
1
1
1
1
(ii) Let C = 0.001F
63 10001.010102
1
2
1&
2
1
===
CfR
RCf
H
H
R=15.9K
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I ORDER HPF:
Circuit diagram & frequency response are shown above.
Again RC components decide the cut off frequency of the HPF where as RF & R1decide the closed loop gain.
EXPRESSION FOR THE GAIN:
Voltage
fCWhereX
VjXR
RV
C
in
C
2
1
1
=
=
( )inin V
fRCj
fCjR
fCjR
RV
fC
jR
RV
21
2
2
1
2
1 +
=+
=
=
= in
l
LV
f
fj
f
fj
+
1
Output voltage,in
L
L
VF
VF V
f
fj
f
jfA
VAV
+
==
1
. 10
Gain =
+
=
L
L
VF
in
f
fj
f
jfA
V
V
1
0
Magnitude is given as
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2
0
1
+
=
f
f
A
V
V
L
VF
in
Phase angle is given as
=
inin V
V
V
V 00
NARROW BAND PASS FILTERS:
This circuit uses only one OPAMP. Frequency response of this filter is also shown above.
This is a band pass filter with a small bandwidth. Bandwidth is equal to fH - fL.
Normally we design the narrow band pass filter for specific values of center frequency fCand the Q factor of the filter.
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DESIGN EQUATIONS:
1. Select C1 = C2 =C
2.FCCAf
QR
21 =
3. ( )FC AQCf
QR
=22
22
4.Cf
QR
C
B
=
5. A is the gain at f =fC
1
3
2R
RAF =
6. Condition on gain22QAF
BAND REJECT FILTERS:
These filters attenuate a specific range of frequencies & pass the rest of frequencies.
Circuit diagram & frequency response of a notch filter are shown above. These are used
in communication & biomedical instrumentation for eliminating the undesiredfrequencies.
DESIGN STEPS:
(1) Select a capacitor C of value less than 1F
(2) CalculateCf
RN2
1=
Eg: Design an active notch filter for rejecting the mains frequency of 50Hz.
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SOLN: Given fN = 50Hz.
1. Choose the capacitor C= 0.47F
2. =
==
KCf
RN
8.61047.0502
1
2
16
ALL PASS FILTER:
It is a special type of filter which passes all the frequency components of the input signalto output without any attenuation. But it introduces a predictable phase shift for different
frequency of the input signal.
The all pass filters are also called as delay equalizers or phase correctors.
Session 12: OPAMP APPLICATIONSPrakash Biswagar
Asst. Professor
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E&C Engg. Dept
RV College of Engineering, Bangalore
ADC & DAC:
Most of the physical quantities such as temperature, pressure, displacement, vibration etcexist in analog form. But it is difficult to process, store or transmit the analog signal
because errors get introduced easily. Hence to enable these signals to be processed
digitally, these are to be represented in equivalent digital form. Hence the need for ADC.
Again, after processing is over, the digital signals are to be converted into
equivalent analog signals for human observations or activation of further circuits.For this,we need DAC.
There are two major types of DAC. (i) Binary weighted resistor DAC
(ii) R-2R ladder type DAC.
BINARY WEIGHTED RESISTOR AC:
Above figure shows a binary weighted resistor type DAC. Basically it uses a network ofbinary resistors & a summing amplifier. There is n number of switches, one per digit.
For e.g. when bit d1 =1, the first switch connects the 21R to a negative reference voltage (-
VR) and so on.Depending upon the position of various switches, the current I1 to In start
flowing through the resistors 21 to 2n R respectively.
Output voltage of this circuit is given as
)222(2
2
1
10
n
nF
R dddR
RVV
++=
The graph of digital input versus output voltage V0 is plotted.
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ADVANTAGES:
(i) Simple to construct
(ii) Economic
DISADVANTAGES:
(i) Accuracy & stability of this ADC depends on the resistors(ii) A wide range of resistors required
(iii) Finite resistance of the switches may disturb the currents.
R-2R LADDER DAC:
This circuit employs only two values of resistors. Output of this circuit is given by
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24
20
FSR
in
i
FVV
R
RV
R
RV =
=
=
ADVANTAGES OF R/2R LADDER DACs
1. Easier to build, as only two values of resistors are needed.2. It is possible to increase the no. of bits just by adding more sections of
same R/2R values.
Eg. The basic step size of a 4 bit DAC is 312.5mV.If 0000 represents 0V, calculate theanalog output voltage produced for the digital input of 1101.
SOLN: DAC output is given by
[ ]nnFS dddVV ++= 222 22
1
10 ----------------------- (1)
Here n=4,
4
4
3
3
2
2
1
10 2222 +++= ddddVV
FS ----------------------- (2)
Basic step size is 00014321 =dddd
Substituting into equation (2)
[ ]43210 21202020 +++= FSVV
Basic step size,1624
0FSFS VVV ==
But given that basic step size = 312.5Mv
VV
V
FS
FS
516105.312
16105.312
3
3
==
=
Now for the input 1101
VV 0625.4212021215 43210 =+++=
DAC SPECIFICATIONS:
For selecting a particular DAC we have to consuder following specifications
1. Resolution
2. Accuracy
3. Linearity4. Temperature5. Settling time
6. Speed
Resolution:
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TYPES OF ADCs:
Based on the method employed, ADCs are classified as
1. Flash ADC2. Counter type ADC
3. Successive approximation ADC
4. Dual slope ADC (Integrator type)
Successive Approximation ADC:
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The above figure shows the block diagram of a successive approximation ADC.
ORERATION:
1. The SAR receives the comparator output, clock & SOC signals & produces an n-bit digital output along with the EOC signal.
2. As soon as we initiate the SOC input, the SAR will set MSB, d1 = 1 with all the
other bits to zero. Thus the trial code at the SAR output is 1000 0000 for an 8 bitADC. This trial code is then applied to a DAC. T he DAC output VD is applied to
the comparator.If trial code is less than the correct digital representation then
comparator output goes high which is applied to SAR.
3. In response to high comparator output, the MSB d1 is maintained at 1 and thenext lower significant bit d2 is made 1.The trial code at the SAR output now
becomes 1100 0000. The corresponding DAC output is compared with VA and the
process continues as explained in step (ii).
4. However for the first trial code of 1000 0000 only if VA < VD , then thecomparator output will go low. The SAR will respond to it by resetting its MSB
bit d1 =0 and making the next bit d2 =1 so that the new trial code is 0100 0000.5. This procedure is repeated for all the subsequent bits one at a time, until all bit
positions are tested.
6. As soon as the DAC output VD crosses VA (i.e. VD >VA ), the comparator changes
state & this is taken as end of conversion command.
ADVANTAGES:
1. The conversion time is equal to the n clock cycle period for an n-bit ADC.Thus
it is very short.2. Conversiontime is constant and independent of the amplitude of analog signal .
ADC Characteristics:
The important characteristics of ADC are (i) Resolution (ii) Conversion time (iii)Quantization error.
Resolution: It can be defined as the ratio of the change in the value of the input
analog voltage VA required to change the digital output by 1LSB.
Hence Resolution =12 n
FSV
Conversion time: It is the time required to convert the analog input signal into a
corresponding digital output.The conversion time depends on the conversiontechniques for ADC.Also, the conversion time depends on the propagation delays
introduced by the circuit components. Conversion time should be as low as possible.
Quantization error:
When an analog signal is converted into digital, there will be some approximation due
to rounding of errors. This is called as quantization error.This is called as quantizationerror. It can be reduced by increasing the no of bits.
VOLTAGE REGULATORS:
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Electronic circuits need dc voltages for biasing. But the power available every where
is ac. Hence the ac is first converted into DC. The rectifier does this function. The
rectifier output contains ripples, which can be eliminated by filters. Again, the outputof a dc power supply varies with changes in load current as well as line voltage.
Hence, there is a need to regulate the output voltage inspire of the changes. This is
performed by the voltage regulator.A block diagram of a power supply is shown below.
\
Three terminal IC Regulators:
The discrete voltage regulators using zener are not much used in practice.Now a days,the voltage regulator circuits are available in the form of IC s.
Advantages of IC regulators:
1. Design of power supply become easy & quick.
2. IC regulators are cheap.
3. Being small in size, IC regulators make the power supply compact.4. They have fatures such as programmable output, facility to boost the output voltage
or current, internal protections such as thermal set down etc.
Regulators have only 3 pins. Hence they are called as 3 pin regulators.3 Pin IC regulators can be of fixed type or adjustable type. Both can be either +ve &
-ve.
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Above figure shows the blockdiagram of a 3 pin IC regulatorThe three terminals
used are Vin, common & V0.
Operation:
1. The resistors R1 & R2 form the sampling N/W to produce the feedback signal
proportional to the output voltage.2. The internally generated reference voltage is compared with the feedback signal,
to produce the control signal.
3. The control signal is routed through the thermal set down & current limiting blockto the series pass transistor, which is acting as the control element. The voltage
across the control element is varied by the control signal to get a constant output
voltage.
4. The thermal shut down & current limiting block provides the protection againstincreased internal temperature or over current.
The three terminal fixed voltage regulators: 78xx Series
Adjustable voltage regulator using 78xx series.
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From the above figure, we can write
Output voltage, 210 )( RIIVVVV RQRAR ++=+=
But1
1R
VI RR =
Hence, 21
20 RRVRIVV RQR ++=
2
1
20 1 RI
R
RVV QR +
+=
Thus the output voltage V0 is dependent on two factors. First is the R2 /R1 and theother is the product IQR2.
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