ATMEGA 8Phn I: l thuyt1. Cu trc harvar v von neumann:Cm t kin trc Harvard c dng ch nhng kin trc my tnh m trong phn bit r rng b nh d liu v b nh chng trnh, chng c nhng ng truyn (bus) ring truy cp vo b nh d liu v b nh chng trnh (ngc li, kin trc von Neumann c b nh v b nh chng trnh chung). Kin trc Harvard bt u vi my tnh Harvard Mark I, n cho php cc lnh c t trong cc tape c l (vi 24 bit) v d liu th c cha trong cc th (vi 23 k t). Nhng my tnh u tin ny rt gii hn dung lng d liu, n c cha hon ton trong b x l trung tm (CPU), v khng cho php truy cp vo khu vc cha lnh (chng trnh) nh vi d liu (lm cho vic to, load, sa cha, v.v. ton b chng trnh phi c thc hin offline).Trong mt my tnh s dng kin trc von Neumann, CPU c th c mt lnh, hoc c/ghi d liu t b nh. Tuy vy, c hai qu trnh tng tc vi lnh hoc vi d liu, khng th thc hin cng lc, v n s dng chung mt ng truyn v b nh. Trong mt my tnh kin trc Harvard, CPU c th va c mt lnh, va truy cp d liu t b nh cng lc. Mt my tnh kin trc Harvard c th chy nhanh hn, bi v n c th thc hin ngay lnh tip theo khi va kt thc lnh trc . Tc c tng ln nhng phi tr gi bng s thit k phn cng phc tp hn (c th nht m chng ta thy, l vic phi thit k 2 bus khc nhau cho d liu v chng trnh).Nhng nm gn y, tc CPU tng ln rt nhiu ln so vi tc truy cp vo b nh chnh. Ngi ta cn quan tm n vic gim s ln truy cp vo b nh m bo tc hot ng ca CPU. Nu, trong cng mt lc, mi lnh ca CPU cn phi truy cp vo b nh 1 ln, vy th vic tng tc CPU chng cn ngha g na, bi v n lun lun b gii hn bi vic truy cp vo b nh.B nh c th c thit k c tc truy cp cao, nhng n ng ngha vi vic gi sn xut s cao. Gii php l cung cp mt dung lng nh b nh m, vi tc truy cp rt cao, v chng ta gi l cache (b nh m). Khi b nh CPU cn tng tc ang nm trong cache, v vic tng tc vo tn t thi gian hn rt nhiu ln so vi khi cache phi thay i v ly d liu t b nh chnh a vo. Vic iu chnh cache l mt vn quan trng trong vic thit k my tnh.Nhng thit k chip CPU tc cao ngy ny thng kt hp hai kin trc Harvard v von Neumann. B nh cache trn chip c phn thnh cache chng trnh v cache d liu. Kin trc Harvard c dng khi CPU truy cp vo cache. Tuy nhin, trong trng hp khng c cache, d liu c ly t b nh chnh, m b nh chnh khng c chia thnh vng nh chng trnh v vng nh d liu. Nh vy, kin trc von Neumann c dng tm vc truy cp b nh chnh.Kin trc Harvard cng thng c dng trong mt s DSP chuyn dng, thng dng trong cc sn phm x l m thanh, hnh nh. V d nh vi x l Blackfin ca Analog Devices Inc. dng kin trc Harvard.Thm vo , hu ht cc vi iu khin thng dng c dng trong cc ng dng in t nh l PIC c sn xut bi Microchip Technology Inc v AVR ca hng Atmel Corporation, c pht trin da trn kin trc Harvard. Nhng vi x l ny c c tnh l c lng b nh d liu v b nh chng trnh nh, rt ph hp vi kin trc Harvard v tp lnh RISC m bo hu ht cc lnh c thc hin trong 1 chu k my. Vic phn chia b nh ra thnh b nh chng trnh v b nh d liu c th lm cho bus d liu v bus chng trnh c kch thc bng truyn khc nhau. V d nh cc vi iu khin PIC c bus d liu 8-bit (ph thuc vo dng PIC), nhng bus chng trnh c th l 12-bit, 14-bit hoc 16-bit word. iu ny cho php mi mt lnh n c ch cha cho mt gi tr hng. Nhng CPU RISC khc, v d nh ARM, thng cn t nht 2 lnh load mt hng s kch thc..
I. Chn ra vo I/O:
1. Set chn I/O: DDRx = 0xff => tt c chn PORTx l chn raTon b PORT: PORTx = value1 PIN trong PORT: PORTx.a = value
2. c chn I/O:DDRx = 0x00 => tt c chn PORTx l chn voPINx => tr v gia tr ca PORTxPINx.a => tr v gi tr chn th a trong PORTx
3. nh ngha chn vo/ra:Vo: #difine cb PINAx.aRa: #difine cb PORTx.a
II. Ngt ngoii vi atmega 8 th c 2 chn ngt ngoi l INT0 v INT11. Ci t trong main Thanh ghi iu khin MCU MCUCR => trng thi xy ra ngt
trong 2 bit ISC11:ISC10 dng cho INT1 v 2 bit ISC01:ISC00 dng cho INT0. Hy nhn vo bng tm tt bn di:
v d: bn mun set cho INT1 l ngt cnh xung (Falling Edge) trong khi INT0 l ngt cnh ln (Rising Edge), hy t dng lnh MCUCR =0x0B (0x0B =00001011 nh phn)
Thanh ghi iu khin ngt chung GICR
Thanh ghi c ngt chung GIFR (General Interrupt Flag Register) c 2 bit INTF1 v INTF0 l cc bit trng thi (hay bit c - Flag) ca 2 ngt INT1 v INT0.Nu c 1s kin ngt ph hp xy ra trn chn INT1, bit INTF1 c t ng set bng 1
Ngt ton cc: #asm(sei);
Code mu: GICR = (1
