© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:1
MIPS-Lite Single-Cycle Control
COE608: Computer Organization and Architecture
Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan
Electrical and Computer Engineering Ryerson University
Overview • Single cycle Data path Review • Data path Analysis for different instructions • Data path Control Signals. • ALU control Signals • Decoding Control Signals • Single-cycle Control and its Performance
Part of section 4.4 from the Textbook
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:2
Overview
5 steps to design a processor 1. Analyze instruction set => data path
requirements 2. Select set of data path components & establish
clock methodology 3. Assemble data path meeting the requirements 4. Analyze implementation of each instruction to
determine setting of control points that affects the register transfer.
5. Assemble the control logic MIPS makes it easier Single cycle data path
CPI=1
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:3
A Single Cycle Data path We have everything except control signals (underline). How to generate the control signals?
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
ExtOp
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
ExtOp
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:4
The Add Instruction
add rd, rs, rt
mem[PC] Fetch the instruction from memory R[rd] <= R[rs] + R[rt] Actual operation PC <= PC + 4 Calculate the next instruction’s address
Instruction Fetch Unit at the Beginning
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bitsopop rsrs rtrt rdrd shamtshamt functfunct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
PC E
xt
Adr
InstMemory
Adder
Adder
PC
Clk
00Mux
4
nPC_sel
imm
16
Instruction<31:0>PC
Ext
Adr
InstMemory
Adr
InstMemory
Adder
Adder
Adder
Adder
PC
Clk
00Mux
Mux
4
nPC_sel
imm
16
Instruction<31:0>
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:5
Data path during Add
R[rd] <= R[rs] + R[rt]
Memory Read when MemWr = 0
32
ALUctr = Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 1
Extender
Mux
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
32
ALUctr = Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 1
Extender
Mux
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:6
IFU at the end of Add PC <= PC + 4
This is the same for all instructions except: Branch and Jump
Adr
InstMemory
Adder
Adder
PC
Clk
00Mux
4
nPC_sel
imm
16
Instruction<31:0>Adr
InstMemory
Adr
InstMemory
Adder
Adder
Adder
Adder
PC
Clk
00Mux
Mux
4
nPC_sel
imm
16
Instruction<31:0>
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:7
Data path during ori R[rt] <= R[rs] or ZeroExt[Imm16]
The Rs field is fed to Ra address port: R[rs] is placed on busA. Other ALU operand will come from the immediate field.
32
ALUctr = Or
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 0
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
32
ALUctr = Or
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 0
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
Zero Extend
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:8
Data path during Load R[rt] <= Data Memory {R[rs] + SignExt[imm16]}
Add R[rs] to Sign Extended Immediate field to form memory address. Use memory address to access memory and write data back to R[rt].
32
ALUctr= Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = 1
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
32
ALUctr= Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = 1
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
Sign Extend
Addres
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:9
Data path during Store Data Memory {R[rs] + SignExt[imm16]} <= R[rt]
Store sends the contents of register specified by Rt to data memory.
32
ALUctr= Add
Clk
busW
RegWr = 0
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 1
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
32
ALUctr= Add
Clk
busW
RegWr = 0
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 1
AL
U
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:10
Data path during Branch if (R[rs] - R[rt] == 0) then Zero <= 1 ; else Zero <= 0
Subtracts the register specified in the Rt field from the register specified in the Rs field and set Zero condition accordingly.
32
ALUctr = Subtract
Clk
busW
RegWr = 0
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= “Br”
32
ALUctr = Subtract
Clk
busW
RegWr = 0
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= “Br”
Don’t care
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:11
IFU at the End of Branch
PC = PC + 4 + Imm16
When the branch condition Zero is true (Zero = 1).
Adr
InstMemory
Adder
Adder
PC
Clk
00Mux
4
nPC_sel
imm
16
Instruction<31:0>Adr
InstMemory
Adr
InstMemory
Adder
Adder
Adder
Adder
PC
Clk
00Mux
Mux
4
nPC_sel
imm
16
Instruction<31:0>
Sign Extend
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:12
Given Data path: RTL => Control
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr
PC
Instruction�memory
Read�address
Instruction�[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoRegALUOpMemWrite
RegWrite
MemReadBranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0M�u�x
0
1
Control
Add ALU�result
M�u�x
0
1
RegistersWrite�register
Write�data
Read�data 1
Read�data 2
Read�register 1
Read�register 2
Sign�extend
Shift�left 2
M�u�x
1
ALU�result
Zero
Data�memory
Write�data
Read�data
M�u�x
1
Instruction [15– 11]
ALU�control
ALUAddress
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:13
Summary of Control Signals
inst Register Transfer ADD R[rd] <= R[rs] + R[rt]; PC <= PC + 4 ALUsrc = busB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”
SUB R[rd] <= R[rs] – R[rt]; PC <= PC + 4 ALUsrc = busB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”
ORi R[rt] <= R[rs] + zero_ext(Imm16); PC <= PC + 4 ALUsrc = Imm, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”
LOAD R[rt] <= MEM[ R[rs] + sign_ext(Imm16)]; PC <= PC + 4 ALUsrc = Imm, Extop = “Sn”, ALUctr = “add”, MemWr = 0, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”
STORE MEM[ R[rs] + sign_ext(Imm16)] <= R[rt]; PC <= PC + 4 ALUsrc = Imm, Extop = “Sn”, ALUctr = “add”, MemWr = 1, nPC_sel = “+4”
BEQ if ( R[rs] == R[rt] ) then PC <= PC + sign_ext(Imm16)] || 00 else PC <= PC + 4 nPC_sel = “Br”, ALUctr = “sub”
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:14
Summary of Control Signals
add sub ori lw sw beq jump
RegDst ALUSrc
MemtoReg
RegWr
MemWr
nPCsel Jump
ExtOp
ALUctr <2:0>
1
0
0
1
0
0
0
x
Add
1
0
0
1
0
0
0
x Subtract
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
func
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
10 0000 See 10 0010 Don’t Care
add sub ori lw sw beq jump
RegDst ALUSrc
MemtoReg
nPCsel Jump
ExtOp
ALUctr <2:0>
00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
10 0000 10 0010
op target address
op rs rt rd shamt funct061116212631
op rs rt immediate
R-type
I-type
J-type
add, sub
ori, lw, sw, beq
jumpop target addressopop target address
op rs rt rd shamt funct061116212631
op rs rt rd shamt functop rs rt rd shamt functopop rsrs rtrt rdrd shamtshamt functfunct061116212631
op rs rt immediateopop rsrs rtrt immediate
R-type
I-type
J-type
add, sub
ori, lw, sw, beq
jump
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:15
Local Decoding
R - type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop <N:0>
1 0 0 1 0 0 0 x
“R - type”
0 1 0 1 0 0 0 0
Or
0 1 1 1 0 0 0 1
Add
x 1 x 0 1 0 0 1
Add
x 0 x 0 0 1 0 x
x x x 0 0 0 1 x
xxx
op 00 0000 R - type ori lw sw beq jump
RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop <N:0>
1 0 0 1 0 0 0 x
“R - type”
0 1 0 1 0 0 0 0
Or
0 1 1 1 0 0 0 1
Add
x 1 x 0 1 0 0 1
Add
x 0 x 0 0 1 0 x
Subtract
x x x 0 0 0 1 x
xxx
00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
MainControl
op6
ALUControl(Local)
func
N
6ALUop
ALUctr3
AL
U
MainControl
op6
ALUControl(Local)
ALUControl(Local)
func
N
6ALUop
ALUctr3
AL
U
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:16
The Encoding of ALUop
ALUop has to be 2 bits wide to represent: • (1) “R-type” instructions • “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, and (4) Subtract For full MIPS, ALUop has to be 3 bits to represent: (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (e.g. andi)
R-type ori lw sw beq jumpALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx
R-type ori lw sw beq jumpALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx
funct<5:0> Instruction Operation10 000010 001010 010010 010110 1010
addsubtractandorset-on-less-than
funct<5:0> Instruction Operation10 000010 001010 010010 010110 1010
addsubtractandorset-on-less-than
ALUctr<2:0> ALU Operation000001010110111
AddSubtract
AndOr
Set-on-less-than
ALUctr<2:0> ALU Operation000001010110111
AddSubtract
AndOr
Set-on-less-than
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:17
The Truth Table for ALUctr
R-type ori lw sw beqALUop(Symbolic) “R-type” Or Add Add Subtract
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 00 1 x x x x x Or 0 0 11 x x 0 0 0 0 Add 0 1 01 x x 0 0 1 0 Subtract 1 1 01 x x 0 1 0 0 And 0 0 01 x x 0 1 0 1 Or 0 0 11 x x 1 0 1 0 Set on < 1 1 1
funct<3:0> Instruction Op.00000010010001011010
addsubtractandorset-on-less-than
R-type ori lw sw beqALUop(Symbolic) “R-type” Or Add Add Subtract
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01
R-type ori lw sw beqALUop(Symbolic) “R-type” Or Add Add Subtract
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 00 1 x x x x x Or 0 0 11 x x 0 0 0 0 Add 0 1 01 x x 0 0 1 0 Subtract 1 1 01 x x 0 1 0 0 And 0 0 01 x x 0 1 0 1 Or 0 0 11 x x 1 0 1 0 Set on < 1 1 1
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 00 1 x x x x x Or 0 0 11 x x 0 0 0 0 Add 0 1 01 x x 0 0 1 0 Subtract 1 1 01 x x 0 1 0 0 And 0 0 01 x x 0 1 0 1 Or 0 0 11 x x 1 0 1 0 Set on < 1 1 1
funct<3:0> Instruction Op.00000010010001011010
addsubtractandorset-on-less-than
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:18
The Logic Equation for ALUctr<2>
ALUctr<2> = ALUop<2> & ALUop<0> +
ALUop<2> & func<2> & func<1> & func<0> The Logic Equation for ALUctr<1>
ALUctr<1> = ALUop<2> & ALUop<1> + ALUop<2> & func<2> & func<0>
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<2>
0 x 1 x x x x 11 x x 0 0 1 0 11 x x 1 0 1 0 1
This makes func<3> a don’t care
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<2>
0 x 1 x x x x 11 x x 0 0 1 0 11 x x 1 0 1 0 1
This makes func<3> a don’t care
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x 1ALUctr<1>
0 x 1 x x x x 11 x x 0 0 0 0 11 x x 0 0 1 0 11 x x 1 0 1 0 1
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x 1ALUctr<1>
0 x 1 x x x x 11 x x 0 0 0 0 11 x x 0 0 1 0 11 x x 1 0 1 0 1
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:19
ALU Control Block
The Logic Equation for ALUctr<0>
ALUctr<0> = ALUop<2> & ALUop<1>
+ ALUop<2> & func<3> & func<2> & func<1> & func<0> + ALUop<2> & func<3> & func<2> & func<1> & func<0>
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<0>
0 1 x x x x x 11 x x 0 1 0 1 11 x x 1 0 1 0 1
ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<0>
0 1 x x x x x 11 x x 0 1 0 1 11 x x 1 0 1 0 1
ALUControl(Local)
func
3
6ALUop
ALUctr3
ALUControl(Local)
ALUControl(Local)
func
3
6ALUop
ALUctr3
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:20
Logic for each control signal
nPC_sel <= if (OP == BEQ) then EQUAL else 0 ALUsrc <= if (OP == “R-type”) then “busB” else “immed” ALUctr <= if (OP == “R-type”) then funct
elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add”
ExtOp <= if (OP == ORi) then “zero” else “sign” MemWr <= (OP == Store) MemtoReg <= (OP == Load) RegWr <= if ((OP == Store) || (OP == BEQ)) then 0 else 1 RegDst <= if ((OP == Load) || (OP == ORi)) then 0 else 1
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:21
“Truth Table” for Main Control
MainControl
op6
ALUControl(Local)
func
3
6
ALUop
ALUctr3
RegDstALUSrc
:MainControl
op6
ALUControl(Local)
ALUControl(Local)
func
3
6
ALUop
ALUctr3
RegDstALUSrc
:
R - type ori lw sw beq jump
RegDst
ALUSrc
MemtoReg
RegWr
MemWr
Branch
Jump
ExtOp
ALUop (Symbolic)
1
0
0
1
0
0
0
x
“R - type”
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
ALUop <2> 1 0 0 0 0 x
ALUop <1> 0 1 0 0 0 x
ALUop <0> 0 0 0 0 1 x
R - type ori lw sw beq jump
RegDst
ALUSrc
MemtoReg
Branch
Jump
ExtOp
ALUop (Symbolic)
1
0
0
1
0
0
0
x
“R - type”
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
ALUop <2> 1 0 0 0 0 x
ALUop <1> 0 1 0 0 0 x
ALUop <0> 0 0 0 0 1 x
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:22
The “Truth Table” for RegWrite
RegWrite = R-type + ori + lw = op<5> & op<4> & op<3> & op<2> &
op<1> & op<0> + op<5> & op<4> & op<3> & op<2> &
op<1> & op<0> + op<5> & op<4> & op<3> & op<2> &
op<1> & op<0>
R-type ori lw sw beq jumpRegWrite 1 1 1 0 0 0
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010R-type ori lw sw beq jump
RegWrite 1 1 1 0 0 0
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
op<5>. . <0>
R - type ori lw sw beq jumpRegWr
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
op<5>. . <0>
R - type ori lw sw beq jump
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
op<5>. . <0>
R - type ori lw sw beq jump
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:23
PLA Implementation
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
R - type ori lw sw beq jump
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
R - type ori lw sw beq jump
op<0>
op<5>. . op<5> . .
<0>
op<5> . . <0>
op<5> . . <0>
op<5> . . <0>
op<5>. . <0>
R - type ori lw sw beq jump
ALUSrc
MemtoReg MemWr
Branch Jump
RegDst
ExtOp
ALUop <2> ALUop <1> ALUop <0>
RegWr
ALUSrc
MemtoReg
Branch Jump
RegDst
ExtOp
ALUop <2> ALUop <1> ALUop <0>
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:24
A Single Cycle Processor
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr
AL
UInstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
MainControl
op6
ALUControlfunc
6
3ALUop
ALUctr3
RegDst
ALUSrc:
Instr<5:0>
Instr<31:26>
Instr<15:0>
nPC_sel
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr
AL
UInstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
MainControl
op6
ALUControlfunc
6
3ALUop
ALUctr3
RegDst
ALUSrc:
Instr<5:0>
Instr<31:26>
Instr<15:0>
nPC_sel
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:25
Worst Case Timing (Load)
Clk
PC
Rs, Rt, Rd,Op, Func
Clk-to-Q
ALUctr
Instruction Memoey Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busARegister File Access Time
Old Value New Value
busBALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
ExtOp Old Value New Value
ALUSrc Old Value New Value
MemtoReg Old Value New Value
Address Old Value New Value
busW Old Value New
Delay through Extender & Mux
RegisterWrite Occurs
Data Memory Access Time
Clk
PC
Rs, Rt, Rd,Op, Func
Clk-to-Q
ALUctr
Instruction Memoey Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busARegister File Access Time
Old Value New Value
busBALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
ExtOp Old Value New Value
ALUSrc Old Value New Value
MemtoReg Old Value New Value
Address Old Value New Value
busW Old Value New
Delay through Extender & Mux
RegisterWrite Occurs
Data Memory Access Time
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:26
Single Cycle Processor: Drawback Long cycle time: Cycle time must be long enough for the load instruction:
PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew
Cycle time for load is much longer than needed for all other instructions. More Problems
• what if we had a more complicated instruction like floating point?
• wasteful of area One Solution:
• Use a “smaller” cycle time • Different instructions take different numbers of cycles • a “multi-cycle” data path
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:27
Single-cycle CPU Performance
Example: CPU-units operation time Memory: 200ps, ALU/Adder:100ps Reg-File: 50ps Assume other hardware units have zero delay and following instruction mix. Loads: 25%, Stores: 10%, ALU instructions: 45% Branches: 15%, Jumps: 5% Compare the following two implementations.
• Each instruction operates in 1 clock cycle of a fixed length. (CPI = 1)
• Each instruction executes in 1 clock cycle using a variable-length clock, which for each instruction is only as long as it needs to be (Impractical approach)
For both Implementations: Instruction Count and CPI are same.
When CPI = 1: CPU EXE-Time = Inst. Count x Clock-Cycle Time
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:28
Single-cycle CPU Performance Critical Path for Variable-Length clock CPU Instructions CPU units used by the Inst. Class R-type IF Reg Access ALU Reg Access Load IF Reg Access ALU Mem Access Reg-Wr
Store IF Reg Access ALU Mem Access Branch IF Reg Access ALU Jump IF
Instruction Class
Inst. Mem
Reg.Read
ALUOp
DataMem
Reg. Write
Total
R-type 200 50 100 0 50 400psLoad 200 50 100 200 50 600psStore 200 50 100 200 - 550psBranch 200 50 100 0 - 350psJump 200 - - 200ps
For Variable Clock machine, clock cycle varies from 200ps to 600ps. Average-time/instruction =
600*.25+550*.1+400*.45+350*.15+200*.05 = 447.5ps
Performance Ratio = 600/447.5 = 1.34
© G.Khan Computer Organization & Architecture-COE608: MIPS-Lite Control Page:29
Multi-cycle Approach
• We will be reusing functional units. – ALU used to compute address and to
increment PC – Memory used for instruction and data.
• Our control signals will not be determined solely by instruction
– e.g., what should the ALU do for a “subtract” instruction?
• We’ll use a finite state machine for
control