© Memec (MG 000-00) 04.01.04
MicroBlaze Overview
Theresa Chou
© Memec (MG 001-04) 02.27.04
Agenda
MB OverViewMB Bus & IPSW Flow MB OS & 3’th party tool
© Memec (MG 001-04) 02.27.04
MicroBlaze is a soft processor core that can be implemented into any Virtex architecture:
Embedded soft RISC Processor32-bit data32-bit instruction word (three addresses and two addressing modes)32 registers (32-bit wide)3 pipe stages (single issue)Big-endian format
BusesFull Harvard-architectureOPB (CoreConnect), instruction and dataLMB for connecting to local BRAM (faster), instruction and data
MB architecture
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MB architecture
BUSIF
PROGRAM COUNTER
INSTRUCTION BUFFER
INSTRUCTION DECODE
REGISTER FILE32b X 32b
BUSIF
MICROBLAZE CORE
ADD/SUB
SHIFT/LOGICAL
MULTIPLY
See more in http://www.xilinx.com/ipcenter/processor_central/microblaze/architecture.htm
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All instruction takes one clock cycle exceptLoad and store (two clock cycles)Multiply (two clock cycles)Branches (three clock cycles, can be one clock cycle)
MB performance
See more in http://www.xilinx.com/ipcenter/processor_central/microblaze/performance.htm
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MicroBlaze Memory Space
Memory and peripheralsThe MicroBlaze processor uses 32-bit addresses
Special addressesMicroBlaze processors must have user-writable memory from 0x00000000 through 0x00000017
BRAM size limitsThe amount of BRAM memory that can be assigned is limitedThe largest supported BRAM memory size for Virtex and Virtex-E is 16 kilobytes; for Virtex-II, it is 64 kilobytes 0x0000_0000
0x0000_00080x0000_0010
0xFFFF_FFFF
0x0000_0018
Reset AddressException AddressInterrupt Address
LMB Memory
OPB Memory
Peripherals
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IBM CoreConnect Bus
The IBM CoreConnect standard provides three buses for interconnecting cores, library macros, and custom logic:
Processor Local Bus (PLB)On-chip Peripheral Bus (OPB)Device Control Register (DCR) bus
See more in http://www-3.ibm.com/chips/products/coreconnect/
MasterMaster/Slave
Slave Slave Slave
Master ArbiterArbiter
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IBM CoreConnect Busses
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Local Memory Bus (LMB)32-bit high speed memory accessSingle-cycle to on-chip BRAMILMB (Instruction LMB)DLMB (Data LMB)
On-Chip Peripheral Bus (OPB)32-bit processor interface8/16/32-bit peripheral interfaceIOPB (Instruction OPB)DOPB (Data OPB)
MicroBlaze – Busses
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MicroBlaze Bus Example
MicroBlaze
DOPBBRAM
DLMB
IIC
OPB ARB
GPIO
UART
Ethernet
LCD
BRAM
INTC
IOPBILMB Ext Mem
ILMB Bus
DLMB Bus DOPB Bus
IOPB Bus
All buses are 32 bits
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ILMB
MicroBlaze Processor
Memory Controller
Instruction Memory
Data Memory
Dual Port Memory
(8K Bytes)
DLMB UART
JTAG UART
GPIO Input
GPIO Output
RS-232
JTAG Header
DIP Switches
7-Segment LED
Example MicroBlaze System
DOPB
50MHzClock
ResetSwitch
FPGA External
OPB Interface
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Free Cores
OPB ArbiterOPB TimeBase/WDTOPB Timer/CounterOPB GPIOOPB UART-LiteOPB JTAG UARTOPB EMC Memory Controller
Flash SRAM ZBT System ACE
OPB BRAM ControllerOPB DDR ControllerOPB SDRAM Controller
PPC System ResetDCR Interrupt ControllerDCR InterfacePLB ArbiterPLB EMC Memory ControllerPLB BRAM ControllerPLB DDR ControllerPLB SDRAM Controller
PLB2OPB BridgeOPB2PLB BridgeOPB2OPB BridgeOPB2OPB Bridge-Lite
Bus-to-Bus communication
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Custom IP Custom IP -- dkgpiodkgpio
dkgpio
opb_ipif_ssp0 dk_logic
OPB Bus
OPB IPIF InterfaceIPIC
Interface LED[0:3]
IPIC is a simplified IPIF interface
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Design Debug (HW and SW)
HW Block Diagram
HW Description
Synthesize
P&R
BIT File/ Download
SW Flow Chart
Create SW source
Compile Simulate
ELF File/ Download
Hardware Flow Software Flow
ISE
EDK
Hardware / Software Flow
DATA2BRAM
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Xilinx EDK
Embedded Development KitXilinx Platform Studio (XPS) – GUI interfaceSupports MicroBlaze and PPC developmentTools for HW and SW platform specificationXilinx Microprocessor Debug (XMD)Board Support Package (BSP) generatorInterface to industry standard simulation tools
MicroBlaze Core & LicensePeripheral IP (Parameterizable)GNU Tools (Compiler, Debugger)Application Examples
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Hardware Flow
PPC405 PLB /Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridge
OPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
Specify Processor,Bus & Peripherals,
Hardware Configuration
Automatic HardwarePlatform Generation
Xilinx Implementation Flow
Bitstream
Download to FPGA
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Hardware Flow – MHS
Microprocessor Hardware Specification File (MHS)
A text file that describes the hardware structure
ProcessorBus architecturePeripheralsConnectivity of the systemInterrupt request prioritiesAddress space
Specify Processor,Bus & Peripherals,
Hardware Configuration
Automatic HardwarePlatform Generation
Xilinx Implementation Flow
Bitstream
Download to FPGA
MHS
© Memec (MG 001-04) 02.27.04
BEGIN microblazePARAMETER INSTANCE = mblazePARAMETER HW_VER = 2.00.aPORT CLK = sys_clkBUS_INTERFACE DLMB = d_lmbBUS_INTERFACE ILMB = i_lmbBUS_INTERFACE DOPB = myopbEND
BEGIN lmb_v10PARAMETER INSTANCE = d_lmbPARAMETER HW_VER = 1.00.aPARAMETER C_EXT_RESET_HIGH = 0PORT LMB_Clk = sys_clkPORT SYS_Rst = sys_rstEND
BEGIN lmb_v10PARAMETER INSTANCE = i_lmbPARAMETER HW_VER = 1.00.aPARAMETER C_EXT_RESET_HIGH = 0PORT LMB_Clk = sys_clkPORT SYS_Rst = sys_rstEND
BEGIN opb_v20PARAMETER INSTANCE = myopbPARAMETER HW_VER = 1.10.bPARAMETER C_EXT_RESET_HIGH = 0PORT OPB_Clk = sys_clkPORT SYS_Rst = sys_rstEND
# ParametersPARAMETER VERSION = 2.0.0
# Global PortsPORT sys_clk = sys_clk, DIR = INPORT sys_rst = sys_rst, DIR = INPORT rx = rx, DIR = INPORT tx = tx, DIR = OUT
# Sub ComponentsBEGIN bram_blockPARAMETER INSTANCE = bram_lmbPARAMETER HW_VER = 1.00.aBUS_INTERFACE PORTA = ilmb_portaBUS_INTERFACE PORTB = dlmb_portb
END
BEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = my_ilmb_cntlrPARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0x0000_0000PARAMETER C_HIGHADDR = 0x0000_1FFFBUS_INTERFACE SLMB = i_lmbBUS_INTERFACE BRAM_PORT = ilmb_porta
END
BEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = my_dlmb_cntlrPARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0x0000_0000PARAMETER C_HIGHADDR = 0x0000_1FFFBUS_INTERFACE SLMB = d_lmbBUS_INTERFACE BRAM_PORT = dlmb_portb
END
Hardware Flow – MHS
IO Port DelcarationsMicroBlaze port connections, bus organization and parameters
LMB/OPB Bus Specifications
Peripherals (memory, etc…)
Auto-Generated MHS File
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Hardware Flow – MPD
Microprocessor Peripheral Definition (MPD)• Template that specifies ports
and parameters of peripherals and IPLists ports and default connectivity for bus interfacesLists parameters and default valuesAny MPD parameter is overwritten by the equivalent MHS assignment
Specify Processor,Bus & Peripherals,
Hardware Configuration
Automatic HardwarePlatform Generation
Xilinx Implementation Flow
Bitstream
Download to FPGA
MPD
MHS
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Hardware Flow – MPD FormatBEGIN opb_uartlite, IPTYPE=PERIPHERAL, EDIF=TRUE, HDL=BOTHOPTION SIM_MODELS = BEHAVIORAL : STRUCTURALBUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE
# Generics for vhdl or parameters for verilogPARAMETER C_BASEADDR = 0xFFFF8000, DT=std_logic_vectorPARAMETER C_HIGHADDR = 0xFFFF80FF, DT=std_logic_vectorPARAMETER C_OPB_DWIDTH = 32, DT=integerPARAMETER C_OPB_AWIDTH = 32, DT=integer PARAMETER C_DATA_BITS = 8, DT="integer range 5 to 8"PARAMETER C_CLK_FREQ = 125_000_000, DT=integerPARAMETER C_BAUDRATE = 9600, DT=integerPARAMETER C_USE_PARITY = 1, DT=integerPARAMETER C_ODD_PARITY = 1, DT=integer
# Global portsPORT OPB_Clk = "", DIR=IN, BUS=SOPB, SIGIS=CLKPORT OPB_Rst = OPB_Rst, DIR=IN, BUS=SOPBPORT Interrupt = "", DIR=OUT, EDGE=RISING, SIGIS=INTERRUPT# OPB slave signalsPORT OPB_ABus = OPB_ABus, DIR=IN, BUS=SOPB, VEC=[0:C_OPB_AWIDTH-1]PORT OPB_BE = OPB_BE, DIR=IN, BUS=SOPB, VEC=[0:C_OPB_DWIDTH/8-1]PORT OPB_RNW = OPB_RNW, DIR=IN, BUS=SOPBPORT OPB_select = OPB_select, DIR=IN, BUS=SOPBPORT OPB_seqAddr = OPB_seqAddr, DIR=IN, BUS=SOPBPORT OPB_DBus = OPB_DBus, DIR=IN, BUS=SOPB, VEC=[0:C_OPB_DWIDTH-1]PORT UART_DBus = Sl_DBus, DIR=OUT, BUS=SOPB, VEC=[0:C_OPB_DWIDTH-1]PORT UART_errAck = Sl_errAck, DIR=OUT, BUS=SOPBPORT UART_retry = Sl_retry, DIR=OUT, BUS=SOPBPORT UART_toutSup = Sl_toutSup, DIR=OUT, BUS=SOPBPORT UART_xferAck = Sl_xferAck, DIR=OUT, BUS=SOPB# uart signalsPORT RX = "", DIR=INPORT TX = "", DIR=OUT
END
Peripheral name, type and HDL source code type
Bus interface information
Parameters/Generics that can be customized by user. Includes default values and variable type.
OPB Port Declarations. These get automatically connected since they are specified to be part of the OPB Slave Bus Interface
User Ports.
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Hardware Flow – Platform GeneratorPlatform Generator (PlatGen)
Uses MHS and MPD files to create the hardware platformCreates netlist filesCreates support files for downstream toolsCreates HDL wrappers
Specify Processor,Bus & Peripherals,
Hardware Configuration
Automatic HardwarePlatform Generation
Xilinx Implementation Flow
Bitstream
Download to FPGA
MPD
MHS
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Hardware Flow – ImplementationImplementation Flow
XFLOW• Batch Mode Place & Route
flow.ProjNav
• ISE Project NavigatorGUI Place & Route flow
Specify Processor,Bus & Peripherals,
Hardware Configuration
Automatic HardwarePlatform Generation
Xilinx Implementation Flow
Bitstream
Download to FPGA
Xflow /ProjNav
MPD
MHS
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Software Flow
After peripheral hardware definition, the software flow is independent of the hardware flow.
Hardware Flow
Bitstream
Download to FPGAPPC405PLB /Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridgeOPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
GDB /XMD
Data2BRAM
Executable in on-chip memory
Specify SoftwareArchitecture
Automatic Software BSP/Library Generation
Software Compilation
Executable
Executable in off-chip memory
?
Download to FPGA
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PPC405PLB /Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridgeOPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
Software Flow – MSS
Hardware Flow
Bitstream
Download to FPGA
Specify SoftwareArchitecture
Automatic Software BSP/Library Generation
Software Compilation
Executable
Executable in off-chip memory
MSS
Executable in on-chip memory
GDB /XMD
Data2BRAM?
Download to FPGA
Microprocessor SoftwareSpecification (MSS)• Auto-generated/user
modifiable file• Contains all project
software options (C-compiler options, driver info, etc.)
© Memec (MG 001-04) 02.27.04
Software Flow – MSS Format
PARAMETER VERSION = 2.0.0PARAMETER HW_SPEC_FILE = system.mhs
BEGIN PROCESSORPARAMETER HW_INSTANCE = my_microblazePARAMETER DRIVER_NAME = cpuPARAMETER DRIVER_VER = 1.00.aPARAMETER EXECUTABLE = executable.elfPARAMETER COMPILER = mb-gccPARAMETER ARCHIVER = mb-arPARAMETER DEBUG_PERIPHERAL = my_jtaguartPARAMETER STDIN = my_uartlitePARAMETER STDOUT = my_uartliteEND
BEGIN DRIVERPARAMETER HW_INSTANCE = myethernetPARAMETER DRIVER_NAME = emacPARAMETER DRIVER_VER = 1.00.bPARAMETER LEVEL = 0PARAMETER LIBRARY = XilNetEND
BEGIN DRIVERPARAMETER HW_INSTANCE = my_uartlitePARAMETER DRIVER_NAME = uartlitePARAMETER DRIVER_VER = 1.00.bPARAMETER LEVEL = 0END
Auto-Generated MSS File
© Memec (MG 001-04) 02.27.04
Software Flow – Library Generator
Library Generator (LibGen)Configures libraries and device drivers
• Creates xparameters.h include file for driver definitions
• Creates libc.a, libm.a, libxil.a libraries that contain functions that the processor can access
Specify SoftwareArchitecture
Automatic Software BSP/Library Generation
Software Compilation
Executable
MSS
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Software Flow – Compiler
XPS SupportsGNU Compiler for MicroBlaze
Specify SoftwareArchitecture
Automatic Software BSP/Library Generation
Software Compilation
Executable
.c
MSS
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Easy to Use Flow
Design your Cpu and Cpu Bus by Graphic
Set each component attribute , port , memory mapping
Finish your CPU design
Use tool bar to run your HW and SW flow
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Starting a New Project
Step through the XPS Hardware FlowCreate a new projectSetup project optionsInsert peripheralsMake connectionsCreate portsSet parametersSet STDIO
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Starting a New Project
Open XPS by selecting Start>Programs>Xilinx Embedded Development Kit>Xilinx Platform Studio
Select the location of the Project File (.xmp)If you have an existing MHS file, Browse to ImportSelect the Target DevicePeripheral Repository Directory
Allows you to select the location of your peripherals if they are not local to your project area.
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From the XPS MenuOptions>Project Options
Target DeviceAllows you to retarget the design to another device
Peripheral Repository Directory
Allows you to specify the location of your peripherals
Project Options – Device and Repository
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Project Options – Hierarchy and Flow
Design HierarchyAllows you to place the design as a sub-module within another design
Netlist Generation Targets the synthesis tool and allows for flat netlist creation
Implementation Tool FlowTargets Xflow or ISE Project Navigator
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Project Options – HDL and Simulation
HDLSelects the language of the peripheral wrappers
SimulatorSelects between ModelSim or Verilog-XL
ModelSim Libraries PathBrowse to the directories where you have compiled the Xilinx Models
Simulation ModelsSelect the models desired for simulationRefer to “Getting Started Guide” for library compile info
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Processor Block DiagramProcessorBlockDiagram (PBD)• Auto-generated/user
modifiable file• Block diagram format of
MHS file• Good as reference, but
keep closed to avoid MHS conflicts
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Define Hardware Platform
All hardware information is stored in the MHS file and can be edited in multiple ways using XPS
Select Project>Add/Edit Cores…(dialog)
This dialog allows you to add Peripherals, Bus Connections, Ports, Parameters, etc.
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Hardware Implementation
Generate Netlist
Hardware Directories
Generate Bitstream
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Software Implementation
Generate Libraries
Library StructureLibraryDriver
MicroBlaze BSP
LibGen
MSSMHS
*.a*.hXmdstub.elf
MDDMDD
MDDLibraries
Drivers for IP
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Downloading Bitstreams
Downloading BitstreamsTools>DownloadRuns iMPACT in batch modeUses download.cmd batch file from the etc directory to properly describe JTAG chainUser must create download.cmd for their system
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DEMO Flow