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Winter – 14 EXAMINATION
Subject Code: 12262 Model Answer Page 1/ 23
Important Instructions to examiners:
1) The answers should be examined by key words and not as word-to-word as given in the
model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try
to assess the understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more
Importance (Not applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the
figure. The figures drawn by candidate and model answer may vary. The examiner may give credit for any
equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant
values may vary and there may be some difference in the candidate‟s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based
on candidate‟s understanding.
7) For programming language papers, credit may be given to any other program based on equivalent
concept.
1. A. Attempt any THREE of the following: (12 M)
(i) State the function of , , XTAL1 pins in 8051.
Ans:- ( Each function 1 marks )
1) PSEN (bar) : Program store enable it is active low O/P signal. It is used to enable external
program memory (ROM).
When [PSEN(bar)]= 0, then external program memory becomes enabled and
microcontroller read content of external memory location.
Therefore it is connected to (OE) of external ROM.
It is activated twice every external ROM memory cycle.
2)EA(bar):External enable
It is and active low I/P to 8051 microcontroller. When (EA)= 0, then 8051 microcontroller
access from external program memory (ROM) only.
When (EA) = 1, then it access internal and external program memories (ROMS).
3) and 4)
XTAL1 and XTAL2
These are two I/P line for on-chip oscillator and clock generator circuit.
A resonant network as quartz crystal is connected between these two pin.
8051 microcontroller also drives from external clock, then XTAL2 is used to drive 8051 from
external clock and XTAL1 should be grounded.
(ii) Write formula to generate variable baud rate. Which timer is used in which mode for
it?
Ans:- (formula : 2 mark , timer mode : 2marks , example can be given –not mandatory)
Timer1- is used to generate baud rate for mode-1 serial communication by using overflow
flag of the timer to determine the baud frequency. Timer-1 is used in timer mode 2 as an
auto-reloaded 8-bit timer. The data rate is generated by timer-1 using the following formula
fbaud= x
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where,
SMOD is the 7th
bit of PCON register
If timer1 is not run in mode 2, then baud rate is,
fbaud= X (timer1 overflow frequency)
timer 1 can be run using the internal clock, fosc/12 (timer mode ) or from any external source via pin T1
(P3.5) (counter mode)
example:
if a standard baud rate is desired, then 11.0592 MHZ crystal could be selected. To get a standard 9600 baud
rate, then assuming SMOD to be „0‟
9600= X
Or
256-TH1= X = 3
Or
TH1= 256-3 = FDH
In mode1, if SM2 is set to 1, no receive interrupt (RI) is generated unless a valid stop bit is received.
(iii) Draw the pin out of RS232.
Ans:- (2 marks for pin diagram and 2 marks for name of pins)
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(iv) Define Simulator & Debugger.
Ans:- Simulators:- (2 marks)
A simulator is the s/w that simulates a h/w unit like emulator, peripheral, network and I/O
devices on a PC .
It defines a processor or processing device as well as various versions for the target system
Monitors the detailed information of as source code part with labels and symbols during the
execution for each single step.
Provides the detailed information of the status of memory RAM and simulated ports,
simulated peripheral devices of the defined target system
Debugger: (2 marks)
A Debugger allows you to download your code to the emulator's memory and then control
all of the functions of the emulator from a PC. Common debugging features include the
capability to examine and modify the microcontroller's on-chip registers, data- and
program-memory; pausing or stopping program executing at defined program locations by
setting breakpoints; single-stepping (execute one instruction at a time) through the code;
and looking at a history of executed code (trace).
(B) Attempt any ONE of the following: (6 M)
(i) Draw structure of internal RAM of 8051 & Show how to select register bank.
(Internal RAM structure: 4 marks, bank selection table: 2 marks)
OR
Register selection table:
PSW format
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(ii) Write an assembly or C language program to send ‘YES’ on TXD LINE OF 8051.
Assume BR=9600 bps & crystal frequency= 11.0592 MHz
(Calculation 1 marks, program: 4 marks, comment 1 marks)
We are assuming crystal value 11.0592 MHz.
o Timer clock Frequency is = XTAL / 12
= 11.0592MHz / 12
= 921.6 KHz
o UART Frequency is = Timer clock Frequency / 32
= 921.6KHz / 32
= 28.8 KHz
o Baud rate = UART Frequency / COUNTER Value
o COUNTER Value = UART Frequency / Baud Rate
= 28.8 KHz / 9600
= 3
As timer in microcontroller is up counter / timer, so counter value is = -3
ASSEMBLY LANGUAGE PROGRAM:
MOV TMOD,#20H ;TIMER 1 MODE 2
MOV TH1,#-3 ;9600 BAUD RATE
MOV SCON,#50H ;8 BIT UART 1 Start bit – 8 data bit – 1 stop Bit
SETB TR1 ;start timer1
MOV SBUF, # “Y” ;send Y
WAIT: JNB TI,WAIT
CLR TI
MOV SBUF, # “E” ;send E
WAIT1: JNB TI,WAIT1
CLR TI
MOV SBUF, # “S” ;send S
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WAIT2: JNB TI,WAIT2
CLR TI
HERE: SJMP HERE
OR
ALTERNATE PROGRAM BY STRING
MOV TMOD, # 20H
MOV TH1, # -3
MOV SCON, # 50H
MOV DPTR, # “YES”
MOV R0, #4
SETB TR1
REPT: CLR A
MOVC A, @ A+DPTR,
MOV SBUF, A
HERE: JNB TI, HERE
INC DPTR
CLR TI
DJNZ R0, REPT
MESSAGE: DB „YES‟, 0
END
OR
C Language Program
/* This program uses the on-chip serial port as the standard output device; and sends "YES"
message to it. */
/* Initialize Serial Port */
/* It initializes serial port in Mode 1 for 4800 baud rate generated using Timer 1 @ 11.0592
MHz */
#include <Intel\8051.h>
#include <stdio.h>
void main ()
{
TH1 = 0xfd ; //LOAD COUNTER FDH I.E. 03H
TL1 = 0xfd ;
PCON &= 0x7f ; //SMOD = 0
SCON = 0x50 ; //SET UART IN MODE 1 I.E 1 START, 8 DATA, 1
STOP
TMOD = 0x20 ; //SET TMOD IN MODE 2 I.E. AUTO RELOAD
MODE
TCON = 0x40 ; //START TIMER
while(1)
{ printf(" YES !\n") ;
delay_ms(1000);
}
}
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Q2 Attempt any FOUR of the following: (16M)
(a) Enlist any four addressing modes with suitable examples.
(List any four -2 marks, example: 2 marks)
Ans:-List: There are eight modes available:
1) Register Addressing -Example, to add the contents of Register 7 to the accumulator, the
following instruction is used
ADD A, R7
2) Direct Addressing- Example, Ports 0 and 1 are assigned direct addresses 80H and 90H,
respectively. It is usually not necessary to know the addresses of these registers; the
assembler allows for and understands the mnemonic abbreviations "P0" for Port 0, "TMOD"
for timer mode register, etc.). Some assemblers, such as Intel's ASM51, automatically
include the definition of predefined symbols. Other assemblers may use a separate source
file containing the definitions. As an example of direct addressing, the instruction
MOV P1 , A
3) Indirect Addressing- Example, if R1 contains 40H and internal memory address 40H
contains 55H, the instruction
MOV A, @R1
moves 55H into the accumulator.
4 ) Immediate Addressing
Example,
MOV A, #12
loads the value 12 (0CH) into the accumulator. (It is assumed the constant "12" is in decimal
notation, since it is not followed by "H."
5) Relative Addressing
SJMP THERE
6 ) Absolute Addressing
example, if the label THERE represents an instruction at address 0F46H, and the instruction
AJMP THERE
7) Long Addressing
LCALL and LJMP
8) Indexed Addressing
JMP or MOVC
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(b) List alternate function of Port3.
Ans:- (½ marks for each pin function)
(c) Describe PCI bus protocol. (4M)
Ans;- PARALLEL BUS(PCI)- Parallel bus enables a host computer or system to communicate
simultaneously 32-bit or 64-bit with other devices or systems, example, to a network interface
card (NIC) or graphic card PCI Parallel Bus When the I/O devices in the distributed embedded
subsystems are networked all can communicate through a common parallel bus. . PCI connects
at high speed to other subsystems having a range of I/O devices at very short distances (<25 cm)
using a parallel bus without having to implement a specific interface for each I/O device. display
monitor, printer, character devices, network subsystems, video card, modem card, hard disk
controller, thin client, digital video capture card, streaming displays, 10/100 Base T card,
Card with 16 MB Flash ROM with a router gateway for a LAN and Card using DEC 21040 PCI
Ethernet LAN controller. When the I/O devices in the distributed embedded subsystems are
networked, all can communicate through a common parallel bus.
(d) Tell the steps to design an Embedded System. (4M)
Ans:- Steps to design an embedded system:
1. Proposal: - An innovative idea or system that makes life easier and/or reduces the amount
of human effort required completing a task.
2. Definition: - Next, the whole system needs to be designed, including what it will do under
all possible sets of input conditions. This definition is perhaps the most critical part, as
any error here will affect the working of whole system.
i. I/O Considerations: - Defines that for a particular input, what the output of the system
will be, considering the system as a black box.
ii. Mathematical Modeling: - Design the algorithm for the system to work as desired.
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iii. Functional Modeling: - Design the functions of the system which will accept input and
produce the desired output.
3. Technology Selection: - Based on the above points, designers then review available
technology and select which devices will fulfill all the requirements while balancing
efficiency, cost, and time-to-market.
4. Integration & PCB design: - List all the components, which you need to implement your
functions and design their placement on the PCB. Traces and all other paths must have
the least possible electromagnetic interference (EMI) and should be free from various
errors. While designing the PCB, special attention must be given to the ground as well as
all the components on the PCB that use ground.
5. Firmware Development & Debugging: - Since hardware needs instructions to execute the
way we want, we need to write the code for every component used by the hardware. This
is exactly what is done by the firmware i.e. the application code. Firmware should be of
minimum complexity. Moreover, as we write the code, we face many errors or bugs and
for this we need a proper debugging protocol.
6. Testing: Debugging tests the piece of code but in testing we test the whole system i.e.
hardware as well as the software that drives that hardware.
7. Documentation: Anyone who accesses your complete application should never ask you
“what does this mean?” or “How does this thing work?” and for this we need to
document everything.
(e) Describe the working of DMA.
Ans:- (Diagram : 1marks , working: 3 marks)
Working: A direct memory access (DMA) is an operation in which data is copied
(Transported) from one resource to another resource in a computer system without the
involvement of the CPU.
The task of a DMA-controller (DMAC) is to execute the copy operation of data from one
Resource location to another. The copy of data can be performed from:
- I/O-device to memory
- Memory to I/O-device
- Memory to memory
- I/O-device to I/O-device
A DMAC is an independent (from CPU) resource of a computer system added for the
concurrent execution of DMA-operations. The first two operation modes are ‟read from‟ and
‟write to‟ transfers of an I/O-device to the main memory, which are the common operation
of a DMA-controller. The other two operations are slightly more difficult to implement and
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Most DMA-controllers do not implement device to device transfers. The DMAC replaces
the CPU for the transfer task of data from the I/O-device to the main memory (or vice versa)
which otherwise would have been executed by the CPU using the programmed input output
(PIO) mode. PIO is realized by a small instruction sequence executed by the processor to
copy data. The ‟memcpy‟ function supplied by the system is such a PIO operation. The
DMAC is a master/slave resource on the system bus, because it must supply the addresses
for the resources being involved in a DMA transfer. It requests the bus whenever a data
value is available for transport, which is signaled from the device by the REQ signal.
The functional unit DMAC may be integrated into other functional units in a computer
system, e.g. the memory controller, the south bridge, or directly into an I/O-device.
(f) Discuss different types of memory used in Embedded System.
Ans:- ( Any 4 memories - 1 mks each)
1) R AM
RAM stands for Random Access Memory. RAMs are simplest and most common form of
data storage. RAMs are volatile.
2 ) DPRAM (Dual Port RAM)
DPRAM are static RAMs with two I/O ports. These two ports access the same memory
locations - hence DPRAMs are generally used to implement Shared Memories in Dual
Processor Systems. The operations performed on a single port are identical to any RAM.
3 ) Dynamic RAM
Dynamic RAMs use a different storage technique for data storage. A Static RAM has four
transistors per memory cell, whereas Dynamic RAMs have only one transistor per memory
cell. The DRAMs use capactive storage However, DRAMs have a very high storage density
(as compared to static RAMs) and are much cheaper in cost. DRAMs are generally accessed
in terms of rows, columns and pages which significantly reduces the number of address
buses (another advantage over RAM).
4 ) OTP- EPROM, UV-EPROM and EEPROM
EPROMs (Electrically Programmable writable Read Only Memory) are non-volatile
memories. Contents of ROM can be randomly accessed - but generally the word RAM is
used to refer to only the volatile random access memories. The operating voltage for writing
in to the EPROMs is much higher than the operating voltage.
OTP-EPROMs are One Time Programmable. Contents of these memories cannot be
changed, once written. UV-EPROM are UV erasable EPROMs. Exposure of memory cells,
to UV light erases the exisiting contents of these memories and these can be re-programmed
after that. EEPROM are Eletricaly Erasable EPROMs. These can be erased electrically
(generally on the same programming station where you write in to them).
5 ) Flash (NOR)
Flash (or NOR-Flash to be more accurate) are quite similar to EEPROM in usage and can be
considered in the class of EEPROM (since it is electically erasable). However there are a
few differences. Firstly, the flash devices are in-circuit programmable. Secondly, these are
much cheaper as compared to the conventional EEPROMs.
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6) NAND FLASH
These memories are more dense and cheaper than NOR Flash. However these memories are
block accessible, and cannot be used for code execution. These devices are mostly used for
Data Storage (since it is cheaper than NOR flash). However some systems use them for
storing the boot codes (these can be used with external hardware or with built-in NAND
boot logic in the processor).
7 ) SD-MMC
SD-MMC cards provide a cheaper mean of mass storage. These memory cards can provide
storage capacity of the order of GBytes. These cards are very compact and can be used with
portable systems. Most modern hand-held devices requiring mass storage (e.g. still and
video cameras) use Memory cards for storage.
8 ) Hard Disc
Hard Discs are Optical Memory devices. These devices are bulky and they require another
bulky hardware (disk reader) for reading these memories. These memories are generally
used for Mass storage. Hence they memories do not exist in smaller and portable systems.
However these memories are being used in embedded systems which require bulk storage
without any size constraint.
Q3 Attempt any FOUR of the following: 16 M
(a) Write any four instructions to read/write data from/to external RAM.
Ans:- Four instructions -1 Mark each (explanation not expected)
MOVX A,@DPTR ;This moves into the accumulator a byte from external memory whose
address is specified in DPTR.
MOVX @DPTR,A ;This moves the content of accumulator to the external memory location
whose address is specified in DPTR.
MOVX A, @Ri ;This moves to the accumulator a byte from external memory whose 8-bit
address is specified by R0 or R1.
MOVX @Ri, A ;This moves a byte from register A to an external memory whose 8-bit
address is specified by R0 or R1.
(b) Draw format of TCON register. What is the function of TRO & TRI bits?
Ans:- (Format-2 Marks, function of TR0 and TR1 – 1Mark each)
TR0: Timer 0 run control bit:
This bit controls the timer 0 operation. When this bit is set (TR0=1) Timer 0 will start
counting the pulses. If reset, timer 0 will stop.
TR1: Timer 1 run control bit:
This bit controls the timer 1 operation. When this bit is set (TR0=1) Timer 1 will start
counting the pulses. If reset, timer 1 will stop.
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(c) Name vector addresses for any four interrupts.
Ans:- Any four interrupts with vector address -4m (1m each)
Interrupt Vector address
INT0 (External interrupt 0) 0003h
T0/TF0(Timer/counter 0) 000Bh
INT1(External interrupt 1) 0013h
T1/TF1(Timer/counter 1) 001Bh
Serial port interrupt 0023h
(d) What do you mean by context switching? (4 M)
Ans:- Each task has its own context, which is the state of the CPU registers required each
time it is scheduled to run. A context switch occurs when the scheduler switches from one
task to another.
Every time a new task is created, the kernel also creates and maintains an associated task
control block (TCB). TCBs are system data structures that the kernel uses to maintain
task-specific information. TCBs contain everything a kernel needs to know about a
particular task.
As shown in above figure when the kernel‟s scheduler determines that it needs to stop
running task 1 and start running task 2, it takes the following steps:
i. The kernel saves task 1‟s context information in its TCB.
ii. It loads task 2‟s context information from its TCB, which becomes the current
thread of execution.
iii. The context of task 1 is frozen while task 2 executes, but if the scheduler needs to
run task 1 again, task 1 continues from where it left off just before the context switch.
(e) Describe starvation & deadlock.
Ans:- Deadlock (2 marks)
A deadlock is a situation in which two threads are each unknowingly waiting for resource
held by other.
Assume thread T1 has exclusive access to resource R1. Thread T2 has exclusive access to
resource R2. If T1 needs exclusive access to R2 and T2 needs exclusive access to R1,
Neither thread can continue. They are deadlocked.
The simplest way to avoid a deadlock is for threads to:
1) Acquire all resources before proceeding
2) Acquire the resources in the same order
3) Release the resource in the revere order
Starvation: (2 marks)
1) Multiple shared resources have multiple semaphores associated with them.
2) he semaphores are all independent of one another. If one task takes semaphore x them
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another task can take semaphore Y, without blocking.
3) But this property can lead to deadlock.
4) For example, suppose task 1 calls function to take semaphore X & get it but before it can
call the function to take semaphore Y the RTOS stops the execution of task 1 & runs task 2.
5) The task2 calls the function to take semaphore & gets it.
6) But when task2 calls the function to take the semaphore X, it is blocked since, the Task1
has already taken the semaphore X.
7) The RTOS now switch back to task 1, which now calls the function to take semaphore Y.
since task2 has semaphore Y, task 1 is also now blocked.
8) There is no escape from this for either tasks, since now both are blocked, waiting for
semaphores that the other has.
9) This problem due to multi-tasking is called Starvation, where a task is denied necessary
resources repeatedly without those resources the task will never be completed.
10) Deadlock is a special case of Starvation.
Q4 A . Attempt any THREE of the following: 12
(a) Describe function of following instruction with examples:
(i) SWAP A
(ii) RRC A
(iii)CJNE A, #25h, NEXT
(iv) DJNZ Rz, NEXT
Ans:- For each instruction – explanation – ½ mark, example – ½ mark any relevant
example (any other relevant examples should be considered)
1) SWAP A :interchanges the low and high-order nibbles of the accumulator. The
operation can also be thought of as a four bit rotate instruction.
Example: MOV A, #25H
SWAP A
Result: A = 52H
2) RRC A :The eight bits in the accumulator and the carry flag are together rotated one bit
to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into
the bit 7 position.
Example: CLR C
MOV A, #0C5H
RRC A
After the execution, A=62H and Cy=1
3) CJNE A,#25H,NEXT :
CJNE compares the contents of Accumulator with immediate value 25H, and branches if
they are not equal. The branch destination is computed by adding the signed relative
displacement in the last instruction byte to the PC, after incrementing the PC to the start
of the next instruction.
Example: CJNE A,#30H, DOWN
4) DJNZ Rz, NEXT
DJNZ decrements the contents of Rz(R0-R7 of any register bank), and branches to the
label NEXT if the current contents of Rz is not zero. The branch destination would be
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computed by adding the signed relative-displacement value in the last instruction byte to
the PC, after incrementing the PC to the first byte of the following instruction.
The following two formats are supported by this instruction.
Example: DJNZ R3, HERE
OR
DJNZ 40H, NEXT
(b) Enlist any four examples of embedded systems.
Any four examples – 1M each
Ans:- (Any other relevant examples should be considered)
Telecom
Smart Cards,
Missiles and Satellites,
Computer Networking,
Digital Consumer Electronics, and Automotive
Mobile phone
Digital camera
Robots
Point of sales terminals
Automatic Chocolate Vending Machine
Stepper motor controllers for a robotics system
Washing or cooking system
Multitasking Toys
Microcontroller- based single or multi-display
Digital panel meter for voltage, current, resistance and frequency
Keyboard controller
(c) Describe structure unit in processor.
Ans:-Listing and explain any 8- 1mks for each unit
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(d) Compare desktop OS with RTOS.
Ans:- (Any four points – 1 mark each)
RTOS Desktop OS
Predictable schedule Unpredictable but efficient schedule
More deterministic Less deterministic
Ability to scale up and down to meeting
application needs (scalable)
Less scalability
Fast context switching higher context switch latency
Uses priority preempitve scheduling Uses round robin way of scheduling.
Support for diskless embedded systems by
allowing executables to boot and run from RAM
or RAM
Has to be booted from disk
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Reduced memory requirements More memory requirements
Faster performance Slower
(B) Attempt any ONE of the following: 06
a) Describe CAN protocol.
Ans:- (Frame format: 2 marks; Explanation: 4 marks)
The ARBITRATION FIELD consists of the 11bit address and the RTR-BIT The address
is also referred as Identifier (ID). These bits are transmitted in the order from ID-10 to
ID-0. , which gives the identity of data. The Remote Transmission Request bit (RTR) will
be dominant for DATA FRAMEs and will be recessive for a REMOTE FRAME.
CONTROL FIELD: The CONTROL FIELD consists of six bits. It includes the DATA
LENGTH CODE and two bits reserved for future expansion. The reserved bits have to be
sent ‟dominant‟. The number of bytes in the DATA FIELD is indicated by the DATA
LENGTH CODE.
DATA FIELD : the length of data may be from 0-64 bits. The length depends on the data
length code in the control field.
CRC field: Contains the cyclic redundancy check (CRC) SEQUENCE for error checking
followed by a CRC DELIMITER.
ACK field: The ACK FIELD is two bits long and contains the ACK SLOT and the ACK
DELIMITER. In the ACK SLOT the transmitting station sends a recessive‟ bit. A
RECEIVER which has received a valid message correctly, reports this to the
TRANSMITTER by sending a ‟dominant‟ bit during the ACK SLOT (it sends ‟ACK‟).
The ACK DELIMITER is the second bit of the ACK FIELD and has to be a recessive‟
bit.
End of Frame (EOF) : Each DATA FRAME and REMOTE FRAME is delimited by a
flag sequence consisting of seven ‟recessive‟ bits
b) Describe parallel port device driver with example
Ans:- (Explanation – 3marks, example – 3 marks)
Note: any relevant example may be considered
When a device is connected to the parallel port of microcontroller, then the device can be
driven in three steps:
1. Initialize the device: to initialize the device we should be aware of the connected device
hardware, the pins which are used for controlling the device. Also the format of control
ARBITRATIO
N 12 bits
(11 bit address
and 1 RTR bit)
CONTROL
6 bits
DATA
0 – 64
bits
CRC
16 bit
ACK
2bits
(ACK and ACK
delimiter)
EOF
7 bits
(0000000)
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registers should be known. After knowing these we can write the assembly instructions
for initialization of the device.
2. Reading the status of the device and accordingly calling the ISR (interrupt Service
Routine): after sending the control word, the device may send some response for
indicating the status of device or the microcontroller will poll the status bit of device.
After getting the status, the microcontroller will decide which ISR is to be called.
3. Executing the ISR: in embedded system, the device driver will perform the function or
execute the ISR as per the code written for particular device, at the time of installing the
device driver.
Example:
If 2 line, 16 character LCD display is interfaced to 8051.
So the program should be written for device driver of LCD in the microcontroller, such
that the driver will take care of initialization of LCD by sending commands to the
command register of LCD. Check the status of LCD whether it transfer the data to the
LCD.
To display a message on the LCD module, it is essential to initialize the LCD module by
writing a series of command codes in the command register in the appropriate sequence.
The initialization includes command codes for clearing display, returning home and
shifting cursor automatically after a character is written.
To write data we need to make R/ signal low, RS signal high, data on respective port
and hold E signal high for at least 450 ns.
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Q.5. Attempt any four.
a) Draw the architecture of 8051.
Ans:- ( 4 mks for proper diagram)
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b) Write an ALP or C language program to generate square wave of 1kHz frequncy on P1-0.
(4 Mark for correct logic program (Correct assembly language program can also be considered
for assessment, sample program is given below) )
Ans:
C Program to generate a square wave of 50 Hz frequency on pin P1.2
#include <reg51.h>
sbit WAVE =P1^2;
void timer0() interrupt 1 {
WAVE=~WAVE; //toggle pin
TL0=0x00;
TH0=0xDC;
}
void main() {
unsigned char x;
TMOD=0x01;
TL0=0xOC;
TH0=0xFE;
IE=0x82; //enable interrupts
TR0=1; //start timer 0
while (1); //wait until interrupted
c) Demonstrate I2C protocol.
Ans:-
Points I2C
1. Network concepts
Multiple masters, multiple
slaves Two
2. Number of signal lines
Two (SCL,SDA)
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3. Network voltage
From 1.8 to 5.5v device
specific
4. Transmission
Ms bit first plus Ack bit, half
duplex
5. Address format
7 bits C10bits defined but not
implemented
6. Gross data rate
Standard :~0to 100k bps; Fast
:~0to 400k bps High speed:
~0 to 3.4M bps.
7. Data protection
N/A
8. Collision detection
Yes (multi master operation
only)
d) Show how to select processor for Embedded System.
Ans:- ( 4 points – 4 mks)
For a system designer, following are the important considerations for selecting a processor.
1. Instruction set.
2. Maximum bits in an operands in a single arithmetic or logical operation.
3. Clock frequency and processing speed in Million Instructions Per Second (MIPS).
4. Processing ability and capability to handle complex algorithms.
e) Enlist any four specifications of RTOS.
Ans: ( Any 4 and their explanation 1 mks each)
Specifications of RTOS:
1) Reliability -
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Embedded systems must be reliable. Depending on the application, the system might need to operate for
long periods without human intervention.
A common way that developers categorize highly reliable systems is by quantifying their downtime per
year, as shown in following table. The percentages under the 'Number of 9s' column indicate the percent
of the total time that a system must be available.
2) Predictability
The RTOS used in this case needs to be predictable to a certain degree. The term deterministic describes
RTOSes with predictable behavior, in which the completion of operating system calls occurs within
known timeframes.
3) Performance
This requirement dictates that an embedded system must perform fast enough to fulfill its timing
requirements.
Typically, the processor's performance is expressed in million instructions per second (MIPS).
Throughput also measures the overall performance of a system, with hardware and software combined.
One definition of throughput is the rate at which a system can generate output based on the inputs
coming in.
4) Compactness
In embedded systems, where hardware real estate is limited due to size and costs, the RTOS clearly must
be small and efficient. In these cases, the RTOS memory footprint can be an important factor.
5) Scalability
Because RTOSes can be used in a wide variety of embedded systems, they must be able to scale up or
down to meet application-specific requirements. Depending on how much functionality is required, an
RTOS should be capable of adding or deleting modular components, including file systems and protocol
stacks.
f) Which are problems in interprocessors communication? How to solve it? (1M each)
Ans: :- Starvation, deadlocks , data inconsistency and synchronization are some of the problems that occur
in interprocessors communication. Detailed explanation and method towards its solution is as follows:
starvation-A starvation condition can occur when multiple processes or threads compete for access to a
shared resource. One process may monopolize the resource while others are denied access
deadlock-\ A deadlock condition can occur when two processes need multiple shared resources at the same
time in order to continue.
A Computer Example of Deadlock:
Thread A is waiting to receive data from thread B. Thread B is waiting to receive data from thread A. The
two threads are in deadlock because they are both waiting for the other and not continuing to execute
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Data inconsistency:
When shared resources are modified at the same time by multiple resources, data errors or inconsistencies
may occur. Sections of a program that might cause these problems are called critical sections. Failure to
coordinate access to a critical section is called a race condition because success or failure depends on the
ability of one process to exit the critical section before another process enters the critical section. It is often
the case that two processes are seldom in the critical section at the same time; but when there is overlap in
accessing the critical section, the result is a disaster
Shared buffers problems:
An example of data inconsistency that can occur because of a race condition is what can happen with a
shared bank account. Dear Old Dad adds money to an account and Poor Student withdraws from the
account. When either accesses the account, they execute a critical section consisting of three steps.
1. Read account balance
2. Update the balance
3. Write the new balance to the account
6. Attempt any four of the following 16
a) Which steps are executed by µC while handling interrupt?
Ans: ( 4 mks for proper steps)
µC finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack
It saves the current status of all the interrupts internally
It jumps to a fixed location in memory called the interrupt vector table
The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it and starts to execute the ISR until it reaches the last instruction RETI
The microcontroller returns to the place where it was interrupted, it gets the PC address from the stack by popping the top two bytes of the stack into the PC and then it starts to execute from that address.
b) Write an assembly/C language program to generate ASCII code for 4 using lookup table.
Ans: Assembly language or C language – 4 mks
C program to display ASCII values
#include<stdio.h> int main(){ int i; for(i=0;i<=255;i++) printf("ASCII value of character %c: %d\n",i,i); return 0; }
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c) What do you mean by device driver? Give example.
Ans: (Explain 2 mks, Example 2 mks)
Device drivers are the primary components of the I/O subsystem. Each device driver is responsible for
managing input/output on a single type of device at the lowest level by managing the device‟s controller.
In computing, a device driver or software driver is a computer program that operates or controls a particular
type of device that is attached to a computer. A driver typically communicates with the device through the
computer bus or communications subsystem to which the hardware connects. When a calling program
invokes a routine in the driver, the driver issues commands to the device. Once the device sends data back to
the driver, the driver may invoke routines in the original calling program. Drivers are hardware-dependent
and operating-system-specific. They usually provide the interrupt handling required for any necessary
asynchronous time-dependent hardware interface. Because of the diversity of modern hardware and
operating systems, drivers operate in many different environments. Drivers may interface with:
printers
video adapters
Network cards
Sound cards
Low-bandwidth I/O buses of various sorts (for pointing devices such as mice, keyboards, USB, etc.)
Computer storage devices such as hard disk, CD-ROM, and floppy disk buses (ATA, SATA, SCSI)
Image scanners
Digital cameras
d) Define task. Which are different states of task?
Ans:
(TASK definition 2 M)
TASK: Task─ term used for the process in the RTOSes for the embedded systems. Task can be defined as
that executing unit of computation, which is controlled by some process at the OS scheduling mechanism,
which lets it execute on the CPU and by some process at OS for a resource-management mechanism that lets
it use the system memory and other system-resources such as network, file, display or printer. (2marks)
States of a Task in a system (2 Marks)
(i) Idle state [Not attached or not registered]
(ii) Ready State [Attached or registered]
(iii) Running state
(iv) Blocked (waiting) state
(v) Terminated
e) Illustrate multitasking.
Ans:- Types of multitasking
1) Cooperative multitasking (1MKS)
a) Multiple tasks execute by voluntarily ceding control to other tasks.
b) One defines a series of tasks and each task gets is own subroutine stack.
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c) Idle task calls an idle routine
d) Another architecture used is an event queue, removing events and calling subroutines based on
their values.
e) Pros & Cons: Same as control loop except that more modular approach. But due to non-determinism of
time factor, not used in embedded systems. Multitasking types(contd.)
2) Pre-emptive multitasking ( 1 MKS)
a) Used in most of the embedded systems.
b) Time-slices allotted to processes.
c) Process context-switched with the next process in the scheduling queue due to following reasons:
• The process has consumed its time slice, and the system clock interrupt pre-empts the process
• The process goes to wait state (often due to planned sleeping, waiting for an I/O event to happen, or
just Mutual exclusion)
• A higher priority process becomes ready for execution, which causes a pre-emption
• The process gives away its time slice voluntarily
• The process terminates itself
Multitasking implemented in embedded systems ( 2 MKS)
1) High priority tasks are executed first.
2) Since embedded systems operations are time constrained systems.
3) Hence even if the highest priority task is in waiting state, it is pre-empted by next highest priority task,
and so on.