Etch Products Business Group
Integrated Dual Damascene Etching for 65nm Technology and Beyond
Yan Ye, Ph.D.Dielectric Etch Technology DevelopmentApplied Materials,PEUG Meeting, Aril 13, 2004
Etch Products Business Group
Content
! Trends in dual damascene development! Integrated dual damascene etch process! Challenges for integrated etch process. ! Feasibility of integrated dual damascene etch process.
Integrated etch process is one of major challenges for dual damascene etch applications of 65nm technology and Beyond
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Low-K Dual Damascene Trends Observed
I-line
248nm Litho
k-va
lue
Technology Node250nm 180nm 130nm 90nm 65 nm
1.5
2.0
2.5
3.0
3.5 FSG/SiN
OSG-I/SiC-I
193nm Litho
157nm Litho?
OSG-II/SiC-II
Porous OSG/SIC-II
45 nm
USG4.0
Trench FirstVia first
Via FirstTrench first
New DD structure?Via First
Both low-k material and lithography are the driving forces for new dual damascene schemes
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BARC Etchback Approach
Pre M2 etch Ash+ Barrier open
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Pre BARC etch M2 etch 2
Dual Damascene with Full-Filled BARC
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Dual Damascene with Bi-layer ResistPre Mask etch Trench etch
Ash Barrier open
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Why Integrated Etch Process is Needed
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Low-K Dual Damascene Process
BD Via EtchM1 Trench Etch
BD DD 2nd Trench etch and Blok open
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All-in-One
Wet Dip
Dip
Wet Dip
Dip
TraditionalEtch Scheme
Lithography PR StripTrench Etch Barrier Open Cu Deposition
4 tools / ~4.5 hrs cycle time4 tools / ~4.5 hrs cycle time
Wet Dip
Enabler: Cycle Time Advantage
1 tool/~30min1 tool/~30min
Representative Fab Layout
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Challenges Faced For Integrated Etch Process
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Etch of Diverse Low-κ Materials and Integration Schemes is Required
Large Operation Window is Required for an All-in-One Dual Damascene Process
BD Via Etch
BD Trench Etch
BLOκκκκ Open
PR Strip
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500O2/10-900mT/100-4500Wb/0-2000Ws
Oxygen Emission intensity (774nm)
Vrf measured fromCathode (Volts)
Time (s)
-2000
-1000
0
1000
2000
3000
4000
0 50 100 150 200 250
Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8
Fast transition between steps is Required for an All-in-One Dual Damascene Process
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All-in-1 Process Requires Tunability for Both Charged Species and Neutral Species Distribution in Each Step
Independent control of both charged and neutral species distribution is necessary to achieve complete tunability of etch rate uniformity and profile/CD uniformity
Independent control of both charged and neutral species distribution is necessary to achieve complete tunability of etch rate uniformity and profile/CD uniformity
-40-35-30-25-20-15-10
-50
0.50 1.00 1.50 2.00 2.50
∆CD
[nm
]
CtrEdge
Edge∆∆∆∆CD: 32 nm
Center
Center Edge∆∆∆∆CD: 3 nm
Effect of Neutral Species Distribution Tuning
3000
6000Across-Wafer Etch
Rate Profile
ER
(A/m
in)
CTR EDGE CTR EDGE CTR EDGE
Center-Fast Edge- Fast~1.% unif.
Effect of Charged Species Distribution Tuning
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TOP CTR BTM
Main etch
Identical process performance is required Identical process performance is required
CTR TOP
CTR TOP
TOPCTR
Over etch
2-in-1PR Strip in a clean chamber
All-in-1Etch, PR Strip, chamber clean
Integrated Etch Process Requires Process Transferable: All-in-1 via etch comparison with 2-in-1 etch
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Feasibility of Integrated Etch Process
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Integrated BD Dual Damascene M2 Trench Etch
Etch Insitu Ash BLoK Open
All-in-1 BD Dual Damascene Trench etch is DemonstratedAll-in-1 BD Dual Damascene Trench etch is Demonstrated
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All-in-1 Low-K Film Integrity Repeatability Test:BD I M2 etch profile after ash & HF dip
Ash
HF Dip
Wafer #1 Wafer #200 Wafer #1000
No Low-k film integrity change in 1000 wafer burn-in
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00 500500 10001000 15001500 20002000 Post PMPost PM
2000 Wafer Burn-in Result for All-in-1 BD M2 Trench:Process and Particle Performance
Process and particle performance are stable through 2000 wafers burn-in.
Cycle Wafer Count 0 500 1000 1500 2000 Post PM
Fence (A) 0 0 0 0 0 0U-loading (%) -2.6 -1.6 -2.9 0.3 -0.6 -2.1
ED (A) 3180 3120 3180 3080 3100 3100NonU(%) 3.3 1.8 2.9 2.4 1.1 2.4
RF-on Particle Chart
0
5
10
15
20
0 25 100
200
300
400
500
750
1000
1250
1500
1750
2000 PM
2050
Wafer count #
Part
icle
Add
er
0
5
10
15
20
>.12um >10um >.12um >10um
The average particle adders are 3.9 and 2.9 for
>.12um and >0.20um
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3 Level Metal Copper BD Interconnect Built Through Integrated Etch process
3 level Copper Interconnect with 95-99% yield 10 Million via chain as well as stacked 1 Million Via Chain
Via1
Stacked Via
3 level Copper Interconnect
M3V2M2V1M1
Via 2
Via resistance (ΩΩΩΩ)
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All-in-1 CDO (k~2.3) Trench Etch with 193nm PR
DICD 109nm1σ=2.8nm
FICD 93nm1σ=2.8nm
Ctr
Edge
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Integrated Porous OSG (ELK) Etch
M 1(Cu)
Oxide
Porous Silica 4.0K
Porous Silica 4.0KSiC 2.0KSiO 0.5K
SiC 1.0K
SiC 1.0K
Demonstrated all-in-1 capabilityDemonstrated all-in-1 capability
All-in-1 Result
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Summary
! Requirement for integrated dual damascene etch processes has been observed. It requires new etch tool with large process window, better tunability for both charge species and neutral species in each step, smooth step transition, effective clean without low-k film damage, and so on. Feasibility to achieved required etch performance for several integrated dual damascene scheme has been demonstrated.
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