Flexible Electronics: Materials,
Circuits, and Design Methodology
Chris H. Kim
Dept. of Electrical and Computer Engineering
University of Minnesota, Minneapolis, MN
www.umn.edu/~chriskim/
Presentation Outline
• Motivation and Applications
• Fabrication Methods and Transistor
Characteristics
• Design Methodology and Circuit Examples
• Case Study: Flexible Dynamic Random
Access Memory (DRAM) Array
• Closing Remarks
Acknowledgements Collaborator: Prof. C. Dan Frisbie, Chemical Engineering Dept., Univ. of Minnesota Students and post-docs: Wei Zhang, Mingjing Ha, Daniele Braga
Funding: National Science Foundation (NSF), Office of Naval Research (ONR)
2
Large Area Flexible Electronics
• Devices: Transistors, LEDs, batteries, sensors
• Flexible, large area, low temperature processing, low
cost, printable
• Applications: Flexible displays, e-paper, RFID, solar
cells, sensor sheets/tapes, lighting, …
• Market size: $9.4B in ‘12, projected to top $63B by ‘22
Flexible circuit E-paper Solar Cell
3
Flexible Electronics: Today
Display Solar cell
Battery
4
Next Generation Flexible Electronics
Problem: Traumatic brain injury for
soldiers exposed to repeated blasts.
Goal: To create a low cost, flexible blast
dosimeter to monitor pressure,
acceleration, sound and light. Non-
volatile memory will record data for one
week
DARPA Funded Project, PARC
5
Holst Centre / IMEC
Digital signal
processing
Memory
Ele
ctro
de
Amp ADC
Large area MxN sensor array
Battery
CPU and
wireless
transmitter
(silicon chip)
Power
management
+
-
Flexible electronics
(this work)Silicon electronics
(conventional)
control
Existing EEG system Proposed EEG system
Electrode sheet
Flexible electronics
...... ...
Next Generation Flexible Electronics
6 MURI/ONR funded project, Minnesota
3V, 6-bit analog-to-digital
converter (Stanford)
15V, delta-sigma analog-to-digital
converter (IMEC)
15V 8-bit microprocessor
(IMEC)
20V, 64b RFID tag
(IMEC)
Challenge: Complex System Integration
7
Presentation Outline
• Motivation and Applications
• Fabrication Methods and Transistor
Characteristics
• Design Methodology and Circuit Examples
• Case Study: Flexible Dynamic Random
Access Memory (DRAM) Array
• Closing Remarks
8
One Strategy: Stretchable Silicon Electronics
John Rogers, UIUC
9
Another Strategy: Printing Circuits
Roll-to-Roll
(dynamic, high-volume)
Sheet-to-Sheet
(static, low-volume,
high precision)
10
Sheet-to-Sheet Printing Methods
Each method has advantages/disadvantages and specific ink requirements
Ink Filament
Printing
Aerosol Jet
Printing
Inkjet
Printing
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Ion-Gel Top-Gated OTFT
Gate
Ion-gel
Channel
S D
Substrate
Gate contact: PEDOT:PSS in water
(Baytron P)
Dielectric: 90 wt% ethyl acetate
8 wt% [EMIM][TFSI]
(Solvent Innovation)
2 wt% PS-PMMA-PS
S/D Contacts: Au
Substrate: Kapton or PEN (Dupont)
or Silicon
Semiconductor: 2 mg/ml P3HT(Merck)
90 vol% Chloroform
10 vol% Terpineol
12
I-V of Ion-Gel Top-Gated OTFT
• High gate capacitance
– Low voltage operation
- 1 . 0 - 0 . 5 0 . 0 0 . 5 1 . 01 0
- 1 1
1 0- 1 0
1 0- 9
1 0- 8
1 0- 7
1 0- 6
1 0- 5
1 0- 4
1 0- 3
I (A
)
VG
( V )
VD
= - 0 . 1 V
VD
= - 1 . 0 V
0.0 0.5-0.5-1.0
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
1E-11
VDS = -1.0V
VDS = -0.1V
VGS (V)
|I D
S|
(A)
1.0
~0.4mA drain current
@ Vdd=1.0V
Substrate
PEDOT:PSS
Ion GelP3HT
Au Au
13
-1.0
-0.5
0.0
0.5
1.0
-1.5
-1.0
-0.5
0.0
VA (100Hz)
VB (200Hz)
VOUT VDD = -1V
0 5 10 15 20
Time (ms)
Input V
oltage (
V)
Outp
ut
Voltage
(V
)
25 30
NAND Logic Gate
VDD
GND
VA VB
VOUT
Transistors
Resistor
500 um
VA VB VOUT
0 0 1
1 0 1
0 1 1
1 1 0 VDD
GND
VA VB
VOUT
14
Ring Oscillator with Tunable Load
0 10 20 30 40 50-2
-1
0
VDD
TL6
TD6
Vout
TL5
TD5
TL4
TD4
TL3
TD3
TL2
TD2
TL1
TD1
VBIAS
VDD = -2V VBIAS = -2.25V f ~ 150 Hz
Time (ms)
VO
UT (
V)
1mm
VBIAS
GND
VDD
VOUT
15
Presentation Outline
• Motivation and Applications
• Fabrication Methods and Transistor
Characteristics
• Design Methodology and Circuit Examples
• Case Study: Flexible Dynamic Random
Access Memory (DRAM) Array
• Closing Remarks
16
Process Design Kit (PDK): Taking a Page Out of
Silicon’s Playbook
Tool vendors, $5B (2010)
Fabless semiconductor
companies, $75B (2010)
IP companies, $3B
(2010)
Foundry, $25B
(2010)
PDK environment
17
Systematic Design Flow Based on a PDK
Basic cell
layout
Basic cell
schematic
-1.0 -0.50
-1
-2
-3
0.0
Cu
rre
nt
(mA
)
Voltage
Single device
measurementsRing oscillator
measurements
Array
circuit
layout
Array
circuit
schematic
Circuit
simulation
Automated
script-based
printing
Measurements
and testing
De
sig
n
itera
tion
G
D
SDevice
compact
model
Circuit
simulation
using HSPICE
Layout Versus
Schematic (LVS)
check
De
sig
n
itera
tion
Printing
Input File
Aerosol-Jet®
printing system
(Optomec, Inc.)
Design Rule
Check (DRC)
Ref: opdk.umn.edu 18
2 mm
VDD
D
CLK
GND
VDD
Q
Q
Reset
NAND Gate Inverter Crossover
D Flip-Flop Circuit (= 1 bit memory)
19
-1.5
-1.0
-0.5
0.0
-1.5
-1.0
-0.5
0.0
CLK (5Hz) Data (2.5Hz)
Q VDD = -1.5V
0 0.2 0.4 0.6
Time (s)
Input V
oltage (
V)
Ou
tput
Voltage (
V)
0.8
VDD
D
CLK
GND
VDD
Q
Q
1
Timing
Parameter
Output Data Pattern
“0” to “1” “1” to “0”
TC-Q 35ms 48ms
TSETUP 10ms 40ms
D flip-flop with Reset function
8 NAND gates + 3 Inverters
20
D Flip-Flop Circuit (= 1 bit memory)
Presentation Outline
• Motivation and Applications
• Fabrication Methods and Transistor
Characteristics
• Design Methodology and Circuit Examples
• Case Study: Flexible Dynamic Random
Access Memory (DRAM) Array
• Closing Remarks
21
General Purpose DRAM Array for
Display/Sensor Applications
• Low voltage, low
power
• Random access
• Compatible with
existing OTFT
logic circuits*
ONON OFF ...
...
FlexibleBattery VDD
GND
INV, NAND,
ROSC, etc.
RBL’s
*Y. Xia, et al., Adv. F
unc. Mater., 2010
22
Previous Organic Memory Reseach
• Non-volatile memory
– Floating-gate structure
– Ferroelectric materials
• Volatile memory
– Write-only SRAM (JSSC07)
• Braille sheet display
• Static power problem
– No previous work on
general purpose DRAM BIAS
VDD VDD
WL
BL
VSSVSS
M. Takamiya, JSSC 2007
Floating Gate
Control Gate
T. Sekitani, Science 2009
23
Electrolyte Gated OTFT with an
Unusually High Gate Capacitance
• Polarized ions enable Cgate=10~100µF/cm2 *
– High gate capacitance ideal for DRAM cells
– 65nm LP CMOS: Cgate~1.4µF/cm2
*Y. Xia, et al., Adv. Func. Mater., 2010
Gate
Source Drain
Substrate
Channel
--
-
--
---
--
+
~5µm
R
S
S S
R R
R
S
S
R
Transistor OFF
Gate
Source Drain
Substrate
Channel
- - - - - - - - - -R
S
S S
R R
R
S
S
R
+ + ++ +
Transistor ON
24
P-type Only 3T DRAM Gain Cell
• Ideal memory cell for electrolyte gated OTFTs
– Long retention time (> 1 minute), compared to 65nm
CMOS (~100µs [4])
– P-type only implementation possible, no static power
RWL = VDD
WWL=0
VDDWBL =
VDD / 0
RBL
= 0
0
VDDVDD / 0 RBL
VDD
VDD+ΔV
VDDVDD / 0 0
Leakage
for ‘0’
Write mode Hold mode Read mode
VDD+ΔV
[4] K. Chun, et al., VLSI symp., 2009
25
8x8 Printed Organic DRAM Array
24 mm
Process
Channel
Array size
TRETENTION
PSTANDBY
Ion-gel organic TFT
Poly(3-Hexylthiophene)
64 bits (8 WLs, 8 BLs)
> 60sec @ 1.30V WWL
5.5 nW/bit
Read delay < 12 msec
Write delay < 20 msec
Array dim 24 x 25 mm2
Supply 0.8V - 1.2V
PACTIVE 8 µW/bit
TR dim. W/L = 500µm / 25µm
Photograph of Printed
Organic DRAM Array
ISSCC 2011, EE Times, MIT Tech Review
26
Array Retention Time Measurements
• Worst case retention time: 30 sec for WWL=1.25V
• Retention time over 1 minute for WWL=1.30V
WWL = 1.25V
WWL = 1.30V
30 40 50 60
0%
10%
20%
30%
Retention time (sec)%
of
failin
g c
ells
201 2 3 4 5 6 7
8
1
2
3
4
5
6
7
Wo
rdlin
e #
Bitline #
> 60
50
40
308
1 2 3 4 5 6 7 8 9
1
2
3
4
5
6
7
8
9
-60
-55
-50
-45
-40
-35
-30
(sec)1 2 3 4 5 6 7 8 9
1
2
3
4
5
6
7
8
9
-60
-55
-50
-45
-40
-35
-30
27
Power Consumption Comparison
• 12X+ power savings in active mode
• < 10nW/bit refresh power in retention mode
1000 4T+2R SRAM
100
10
1
0.1
0.01
0.001
98µW
8µW 8µW
Po
we
r c
on
su
mp
tio
n (
µW
/bit
)
11nW 5.5nWWW
L=
1.2
5V
SRAM
(Pstatic only)
DRAM
(active)
DRAM
(active)
DRAM
(stdby)
DRAM
(stdby)
WW
L=
1.3
0V
WW
L=
1.2
5V
WW
L=
1.3
0V
IDC
1/12
1/17,818
‘1’ ‘0’
BL BLB
WL WL
RWL
WBL RBL
3T DRAM
WWL
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Closing Remarks • Flexible electronic products are already here
– Displays, solar cells, batteries
• Next generation flexible electronics systems
– Multi-functional electronic sheets for sensing,
detection, processing, storage, and communication
– Complex integration of various circuit components
• Multi-disciplinary effort key to success
– Ink and material development
– Transistors and interconnect design
– Fabrication methods (R2R, sheet based)
– Circuit design and computer-aided-design tools
– Application and systems
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