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ECE145/218A CAD Assignment #4:
Reactively Tuned Amplifier Design.
November 29, 2020
OVERVIEW. .............................................................................................................................................. 2
PART 1: .................................................................................................................................................... 3
PART 2 ..................................................................................................................................................... 7
PART 3 ..................................................................................................................................................... 8
PART 4 ..................................................................................................................................................... 9
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Overview.
In this exercise, you will design, generate the mask layout, and simulate the performance
of a reactively-matched amplifier.
The transistor is an InP HBT with a 0.25 micron width by 4 micron length emitter stripe.
It is to be used in common-emitter mode, and should be biased at Vce=1.1Volts and Ic=4
mA. The design frequency is 100GHz. The amplifier must be unconditionally stable at
that frequency (ece145A and ece218A students) and (ece218A students only) must also
be unconditionally stable at all frequencies.
The design will be in steps.
1) You will first simulate the bare performance of the transistor to determine its
maximum available or maximum stable gain at 100GHz. You will then, by your preferred
method, stabilize the transistor at the 100GHz design frequency. After stabilizing the
transistor, you will determine the maximum available gain *after stabilization*, and the
source and load impedances that must be presented to the transistor to obtain this gain.
2) You will then, using *circuit* simulations and *library* elements (not EM
simulations) in ADS, design impedance-matching networks to present to the transistor the
source and load impedances required for the transistor to provide this maximum gain.
You must also provide bias networks that provide DC bias to the transistor without
substantially degrading the 100GHz performance. You will simulate the resulting circuit
for input match (S11), output match (S22), forward insertion gain (S21), reverse insertion
gain (S12), and stability factors (K and B1) as a function of frequency.
3) For ece218A students only, you will examine the stability factors (K and B1) and, if
necessary, the source and load stability circles, and will add additional stabilization
networks to provide stability over DC-fmax.
4) For both ece145a and ece218A students, you will then generate a mask layout of the
amplifier, with physical layouts for the resistors, capacitors, and transmission-line
elements. You will model these, either individually, on as one single unit for the input
network and another for the output networks, using ADS's electromagnetic simulation
tools. Using the results of these electromagnetic simulations, you will then simulate the
entire amplifier circuit for input match (S11), output match (S22), forward insertion gain
(S21), reverse insertion gain (S12), and stability factors (K and B1) as a function of
frequency.
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Part 1:
Start with the basic "gain_testbench" circuit file, with the subcircuit "biased HBT" to
be simulated.
Figure 1: Circuit simulation of transistor alone.
The "biased HBT" uses some tricks that would work in CAD, but not in a real circuit, to
bias the transistor. The course SRC5 forces the desired DC collector current, while SRC1
forces the *base-collector* DC voltage. Since Vbe is about 0.9V, with SRC1 set to 0.2V,
Vce is about 1.1 V.
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Figure 2: biased transistor.
Double-click on the transistor itself and make SURE that you have the following
parameters set in the simulation.
Figure 3: Required HBT model parameters.
If we now return to the gain testbench, and simulate the circuit, we should obtain a gain
plot as below. At 100GHz, the transistor has a "MAG" of 14.6dB (actually, this is MSG,
as the K-factor, a.k.a. stabfact1, is less than 1). At 740GHz, the unilateral gain and the
MAG are both 0dB, hence this frequency is fmax.
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Figure 4: Simulated transistor gains.
You now seem that the transistor has 14.6dB maximum stable gain, at this bias, and in
common-emitter mode, at 100GHz. Be sure to show this simulation in your report.
You goal is to design an unconditionally stable amplifier which provides close to this
gain.
You must first stabilize the transistor at 100GHz. Go back to the gain testbench, and
simulate the transistor from 100GHz to 100GHz (!). Then the "gain circles" tab on the
"gain plot" will show source and load stability circles, together with the circles of
operating gain and available gain. Be sure to show this simulation in your report.
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Figure 5: Source and load stability circles, together with the circles of operating gain and
available gain, for the the raw transistor.
Before we can go further, we must use a physically realistic means of biasing the
transistor. One means would be as below (Figure 6A). IF the two lines (TL1 and TL2) are
quarter-wavelength at the design frequency, then the lines present an open-circuit to the
transistor at that frequency. We set the resistor Rb1 to obtain some base current, and the
collector current is beta times larger than this. Use the function "DC annotation" under
the "simulate" menu to check the DC collector current. This, by the way, is too sensitive
to variations in beta to use in a production design, but we will choose to be sloppy in this
project. We will discuss better bias design techniques. Be sure to show bias circuit
diagram in your report.
We can then add (Figure 6B,C,D,E) series or shunt stabilization resistance on either input
or output. This is the basic technique covered in the lecture notes.
But, we can be more clever in our design: we may find it useful to make the degree of
stabilization vary with frequency. In Figure 6F we have added the parallel network Rstab,
Cstab; this adds a series impedance whose real part, 2 2 2/ (1 )R R C , decreases with
frequency.
In Figure 6G we have added the resistor Rstab2 in series with TL1. If TL1 is quarter-
wavelength at the 100GHz design frequency, Rstab 2 will provide no shunt stabilization
(and no loss in gain) at 100GHz, and the circuit will be stabilized only by Rstab. But
Rstab2 will provide much more shunt stabilization at lower frequencies, helping us
design for low-frequency stability. Or, we can omit Rstab, and make TL1 somewhat less
than quarter-wavelength at 100GHz. Then Rstab2 provides a great deal of shunt loading
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at low frequencies, some shunt loading at 100GHz, and less shunt loading at higher
frequencies.
Be sure to show your stabilization technique in your report.
Figure 6: (A) One way to bias the transistor. (B,C,D,E) adding simple series or shunt
stabilization on input or output. (F,G) Adding frequency-dependent stabilization.
Part 2
Once we have stabilized the transistor, the operating gain, available gain, and stability
circles will look something like below. The centers of the Ga and Gp circles are the
impedances we must present to the transistor. Be sure to show this simulation in your
report.
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Figure 7: Example of operating gain, available gain, and stability circles after stabilization.
You must then, using *circuit* simulations and *library* elements (not EM simulations)
in ADS, design impedance-matching networks to present to the transistor the source and
load impedances that correspond to the centers of the Ga and Gp circles, as in the
examples displayed above.
Do this by noting these impedances (or, equivalently, reflection coefficients) and, in a 2-
port ADS simulation, design an input matching network whose S22 is the source
reflection that you wish to present to the transistor. Then design an output matching
network whose S11 is the source reflection that you wish to present to the transistor. Be
sure to show this simulation in your report.
You then combined these networks with the biased and stabilized transistor to obtain the
full amplifier. Simulate the resulting circuit for input match (S11), output match (S22),
forward insertion gain (S21), reverse insertion gain (S12), and stability factors (K and B1)
as a function of frequency. Be sure to show this simulation in your report.
Part 3
For ece218A students only, you will examine the stability factors (K and B1) over the
DC-fmax frequency range. Be sure to show this simulation in your report. If necessary,
design additional stabilization networks (using library elements, not electromagnetic
simulations) to provide stability over DC-fmax. Again, be sure to show this simulation
in your report.
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Part 4
For both ece145a and ece218A students, you will then generate a mask layout of the
amplifier, with physical layouts for the resistors, capacitors, and transmission-line
elements. You will model these, either individually, on as one single unit for the input
network and another for the output networks, using ADS's electromagnetic simulation
tools. Using the results of these electromagnetic simulations, you will then simulate the
entire amplifier circuit for input match (S11), output match (S22), forward insertion gain
(S21), reverse insertion gain (S12), and stability factors (K and B1) as a function of
frequency. Show the completed mask layout in your report, and show the
comparison of simulations with library elements vs. electromagnetic simulations.