Compact Modeling of Semiconductor Devices: MOSFET
Yogesh S. Chauhan Assistant Professor and Ramanujan Fellow
Nanolab, Department of Electrical Engineering IIT Kanpur
Email: [email protected] Homepage – http://home.iitk.ac.in/~chauhan/
Outline
• Compact Modeling • MOSFET • Drain Current in MOSFET • Smoothing Functions • Terminal Charges • Scaling • FinFET
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Compact Modeling or SPICE Modeling
• Excellent Convergence • Simulation Time – ~µsec • Accuracy requirements
– ~ 1% RMS error after fitting • Example: BSIM6, BSIM-
CMG
Medium of information exchange
Good model should be Accurate: Trustworthy simulations. Simple: Parameter extraction is easy.
Balance between accuracy and simplicity depends on end application
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Industry Standard Compact Models
• Standardization Body – Compact Model Coalition
• CMC Members – EDA Vendors, Foundries, IDMs, Fabless, Research Institutions/Consortia
• CMC is by the industry and for the industry
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What is MOSFET?
• MOSFET is a transistor used for amplifying or switching electronic signals.
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Gate
Drain
Source
Introduction to MOSFET
• Building block of Gb memory chips, GHz microprocessors, analog, and RF circuits.
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Basic MOSFET structure and IV characteristics
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Polysilicon gate & SiO2
How can we simulate MOSFET based circuits?
• We need – Currents
𝐼𝐼𝑑𝑑𝑑𝑑 = 𝑊𝑊.𝑄𝑄𝑖𝑖𝑖𝑖𝑖𝑖. 𝜈𝜈 = 𝑊𝑊.𝑄𝑄𝑖𝑖𝑖𝑖𝑖𝑖.𝜇𝜇𝑖𝑖𝑑𝑑𝐸𝐸
𝐼𝐼𝑑𝑑𝑑𝑑 = 𝑊𝑊.𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝑔𝑔𝑑𝑑 − 𝑉𝑉𝑡𝑡 .𝜇𝜇𝑖𝑖𝑑𝑑𝑑𝑑𝑉𝑉𝑐𝑐𝑐𝑑𝑑𝑑𝑑
– Charges (for capacitance)
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Energy Band Diagram in Equilibrium
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Depletion and Inversion
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Surface is depleted of holes Surface is inverted
Threshold Condition and Threshold Voltage
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Threshold (of inversion): ns = Na , or (Ec–Ef)surface= (Ef – Ev)bulk , or A=B, and C = D
ox
BsaBfbgt C
qNVthresholdatVV
φεφ
222 ++==
ox
Bsaox C
qNV
φε 22=
𝑉𝑉𝑔𝑔 = 𝑉𝑉𝑓𝑓𝑓𝑓 + 𝜓𝜓𝑑𝑑 + 𝑉𝑉𝑜𝑜𝑜𝑜
𝜓𝜓𝑑𝑑𝑡𝑡 = 2𝜙𝜙𝑓𝑓 = 2𝑘𝑘𝑘𝑘𝑞𝑞𝑙𝑙𝑙𝑙
𝑁𝑁𝑎𝑎𝑙𝑙𝑖𝑖
Amount of band bending at surface is called “Surface Potential”.
Inversion Layer Charge • Applied Gate Voltage
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ox
invt
ox
inv
ox
BsaBfb
ox
inv
ox
depBfbg
CQ
V
CQ
CqN
V
CQ
CQ
VV
−=
−++=
−−+=
22
2
2
φεφ
φ
Inversion Layer Charge )( tgoxinv VVCQ −−=
MOSFET Vt and the Body Effect
Yogesh S. Chauhan, IIT Kanpur 12
maxd
sdep W
C ε=
sbdeptgsoxeinv VCVVCQ +−−= )(
))(( sboxe
deptgsoxe V
CC
VVC +−−=
• Two capacitors => two charge components
sbtsboxe
deptsbt VVV
CC
VVV α+=+= 00)(
• Redefine Vt as Cdep
Coxe
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Uniform Body Doping • In earlier generations of MOSFETs, the body
doping density is more or less uniform and Wdmax varies with Vsb.
• In that case, the theory for the body effect is more complicated.
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)22(
)22(2
0
0
BsbBt
BsbBoxe
satt
VV
VC
qNVV
φφγ
φφε
−++≡
−++=
γ is the body-effect parameter.
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Threshold Voltage Modeling
• Long/Wide Channel Model With Uniform Doping – VFB=flat band voltage – VTH0=threshold voltage of device at zero substrate
bias – γ is the body bias coefficient given by
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Threshold Voltage Modeling • As channel length gets shorter Vth shows a greater dependence on
– Short-channel effect Higher Off Current Leakage – DIBL Higher Off Current Leakage at high Vds
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Threshold Voltage Modeling
• The complete Vth model implemented in SPICE as
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Surface Mobility
• Scattering mechanisms – Phonon scattering – Coulomb scattering – Interface roughness scattering
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L V V V WC
L V WQ
WQ v Q W I
ds ns t gs oxe
ds ns inv
ns inv inv ds
/ ) (
/
µ
µ
µ
− =
=
= × × = E
Vg = Vdd , Vgs = Vdd
Ids
Vds > 0
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Surface Mobility • Mobility is a function of the average of the fields at the
bottom and the top of the inversion charge layer, Eb and Et .
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From Gauss’s Law, Eb = – Qdep/εs
oxedepstfbt CQVV /−+= φ
) ( st fb t s
oxe b V V C E φ
ε − − = Therefore,
) (
) ( /
/ ) (
st fb gs s
oxe
t gs s
oxe b s inv b
s inv dep t
V V C
V V C E Q E
Q Q E
φ ε
ε ε
ε
− − =
− + = − =
+ − =
oxe
t gs
t gs s
oxe
st fb t gs s
oxe t b
T V V
V V C
V V V C E E
6 V 2 . 0
) V 2 . 0 ( 2
) 2 2 ( 2
) ( 2 1
+ + =
+ + ≈
− − + = +
ε
φ ε
∴
oxsfbg VVV ++= ψ
NMOS with n+ poly-Si gate Vfb≈-0.5 and ψst≈0.4
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Universal Surface Mobilities
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•Surface roughness scattering is stronger (mobility is lower) at higher Vg, higher Vt, and thinner Toxe.
Surface mobility (cm
2/V-s)
Empirical fitting
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Mobility Modeling in BSIM4
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oxe
tgsteffeff
oxe
tgseff
oxe
tgseff
TVV
E
TVVtV
E
TVV
E
62
62
6
+=
+−=
+=
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Current in subthreshold region • Subthreshold conduction
– Transistor is in depletion • Surface potential is determined by
depletion under the gate, which is constant everywhere (ψS≈ ψsa).
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dxdVWQxI CB
ieffds µ=)(
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22
42
−++−=≈ FBGBsasa VVγγψψ
+−=
−
t
MGCn
VV
t
CBf
AsI e
V
NqQ φφ
φ
ε'
'
22
2
Current in subthreshold region
• Integrating from source to drain,
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∫∫ ⋅⋅⋅=L
CBieff
L
ds dVQWdxxI00
)( µ
∫ ⋅=DB
SB
V
VCBieffds dVQ
LWI µ
∫ ⋅
+=
−−DB
SB
t
THCBGBV
VCB
nVVV
t
CBf
Aseffds dVe
V
NqL
WI φφφ
εµ
'22
2
−=
−−
t
THGD
t
THGSn
VVn
VV
ds eeII ϕϕ0
−=
−−
t
DS
t
THGSnV
nVV
ds eeII ϕϕ 10
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Current in subthreshold region
• Note – VTH is a function of body bias. – If VB increases in negative direction, VTH
increases.
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−=
−−
t
DS
t
THGSnV
nVV
ds eeII ϕϕ 10
( )000 φφγ −++= SBTTH VVV
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Subthreshold slope • It is defined as the amount of gate voltage
required to change the gate current by 1-decade.
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( )ds
GS
IddVSlog
=
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At room temperature
( )
+≈
+=
ox
dep
ox
dep
CC
mVCC
S 1601)30.2(85.25
Drain Current and Qinv in MOSFET
• Qinv = – Cox(Vgs – Vcs – Vt0 – α (Vsb+Vcs) • = – Cox(Vgs – Vcs – (Vt0 +α Vsb) – α Vcs) • Qinv = – Cox(Vgs – mVcs – Vt) • • m ≡ 1 +α = 1 + 3Toxe/Wdmax ≈1.2 • m is called the body-effect factor or bulk-charge factor.
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( ) ( )cbtGCoxTHGCoxI VVVCVVCQ α−−−=−−= 0'''
• Channel voltage Vc=Vs at x = 0 and Vc=Vd at x = L.
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Drain Current Calculation
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cs
L V
tcsgsnsoxeds dVVmVVWCdxI ds )(0 0∫ ∫ −−= µ
Ids = WCoxe(Vgs– mVcs – Vt)μnsdVcs/dx
Now,
Integrating the above equation over the channel length L, gives the current voltage relation as follows:
IdsL = WCoxeµns(Vgs – Vt – mVds/2)Vds
dsdstgsoxensds VVmVVL
WCI
−−=
2µ
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I-V characteristics
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0dVdI
ds
ds =
0)mVV(VμCL
Wdsattgsnsoxe =−−
mVV
V tgsdsat
−=
Vds ˂ Vdsat Linear Region Vds ≥ Vdsat Saturation region
2)(2 tgsnsoxedsat VVC
mLWI −= µ
Drain current in saturation regio
Linear Region Saturation region
• transconductance: gm= dIds/dVgs )( tgsnsoxemsat VVCmLWg −= µ
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I-V characteristics
What happens at Vds=Vdsat & why Ids remains constant beyond Vdsat At Vds=Vdsat , Qinv near the drain end of the
channel becomes zero ! i.e. Pinch off. Ids = WQinvµnsE (Large E and and negligible Qinv)
At Vds >Vdsat , A very short region near the drain end where the Qinv = 0, a very high electric field exist due to the drop of the additional Vds - Vdsat . Yogesh S. Chauhan, IIT Kanpur 28 12/3/2014
Velocity Saturation
• At low E • The inversion-layer electron velocity saturates
at high field
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ν = μnsE
sat
ns
/1 ξξ+ξµ
=ν
satξ is the field at which velocity saturation becomes dominant.
ξ satξ<< ξµ=ν ns
satnssat ξµνν == ξ satξ≥
,
,
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Velocity Saturation and I-V Model
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( )
sat
cs
csns
tcsgsoxeds
dxdV
1
dxdV
VmVVWCI
ξ+
µ−−=
cssat
dstcsgsnsoxe
L
0
V
0ds dVI)VmVV(WCdxI ds
ξ−−−µ=∫ ∫
sat
ds
dstdsgsnsoxe
ds
LV
VVVmVCL
W
I
ξ
µ
+
−−
=1
2
Ids = WQinvν
Drain current when ν ˂ νsat
sat
ns
/1 ξξ+ξµ
=ν
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Velocity Saturation and I-V Model
• If L is large then will be negligible, then:
• Effect of velocity saturation on Ids:
• In short channel devices
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sat
ds
LVξ
dsdstgssoxeds VVmVVCL
WI )2
( −−= µIt is called the long channel I-V model
Ids = (Long channel Ids)/( sat
ds
LV1ξ
+ )
11 >+sat
ds
LVξ
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Velocity Saturation and I-V Model • Drain current for Vds ≥Vdsat
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( )
LmVV
1
VVC
mL2WI
sat
tgs
2tgs
nsoxedsat
ξ
−+
−µ= =Long channel Idsat/(
LmVV
1sat
tgs
ξ
−+ )
Very short channel case:
• Idsat is proportional to Vgs–Vt rather than (Vgs – Vt)2 , •Not as sensitive to L as than long channel case (∝1/L).
( )LmEVVCWvI sattgsoxesatdsat −−=tgssat VVLE −<<
Long channel case:
( )2
2 tgsnsoxedsat VVCmLWI −≈ µ
tgssat VVLE −>>
( )tgsoxesatdsat VVCWvI −≈
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I-V Characteristics
• Long Channel Short Channel
• Ids ∝ (Vgs-Vt)2 Ids ∝ Vgs-Vt DITS +CLM+ DIBL
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I-V Characteristics
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Curves for a particular gate voltage
Curves for a different gate voltages
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Compact Modeling is Art based on Science
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Smoothing function and I-V Model
• Smoothing function is required for a smooth transition between two functions. – This stems from the need to have a single equation
valid in all regions of operation. • BSIM3 introduced use of smoothing functions
to get single equation valid in all regions of biases. – This gave continuous and smooth I-V and C-V
making it popular model for analog design.
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Linear to Saturation transition • First generation SPICE models used this kind of equation,
𝐼𝐼𝐷𝐷 =
𝑊𝑊𝐿𝐿 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐺𝐺 −
𝑚𝑚2 𝑉𝑉𝐷𝐷𝐺𝐺2 ,𝑉𝑉𝐷𝐷𝐺𝐺 < 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡
𝑊𝑊𝐿𝐿 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′
(𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇)2
2𝑚𝑚 ,𝑉𝑉𝐷𝐷𝐺𝐺 ≥ 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡
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𝐼𝐼𝐷𝐷 and 𝑑𝑑𝐼𝐼𝐷𝐷𝑑𝑑𝑉𝑉𝐷𝐷𝐷𝐷
are continuous at
𝑉𝑉𝐷𝐷𝐺𝐺 = 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡 but 𝑑𝑑2𝐼𝐼𝐷𝐷
𝑑𝑑𝑉𝑉𝐷𝐷𝐷𝐷2 is not.
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Linear to Saturation transition • For numerical robustness, the derivatives of arbitrary order must be
continuous at all voltage values of interest. This property is sometimes referred to as ∞-differentiability.
• Single equation approach used in BSIM3. Define an effective drain-source bias VDSeff,
𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 = 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡 −12 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡 − 𝑉𝑉𝐷𝐷𝐺𝐺 − Δ + (𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡 − 𝑉𝑉𝐷𝐷𝐺𝐺 − Δ)2+4Δ𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡
• 𝑉𝑉𝐷𝐷𝐺𝐺 ≪ 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡, 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 ≈ 𝑉𝑉𝐷𝐷𝐺𝐺 • For 𝑉𝑉𝐷𝐷𝐺𝐺 ≫ 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡, 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 ≈ 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡
• Drain current equation becomes (VGS>VT),
• 𝐼𝐼𝐷𝐷 = 𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 −
𝑚𝑚2𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓2
• Derivatives are continuous.
Yogesh S. Chauhan, IIT Kanpur 38
Increasing Δ
Δ determines the degree of smoothness.
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Sub-threshold to strong inversion transition • For 𝑉𝑉𝐺𝐺𝐺𝐺 ≪ 𝑉𝑉𝑇𝑇,
𝐼𝐼𝐷𝐷 = 𝐼𝐼0𝑒𝑒(𝑉𝑉𝐺𝐺𝐷𝐷−𝑉𝑉𝑇𝑇−𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜)
𝑖𝑖𝑛𝑛𝑇𝑇/𝑞𝑞 1 − 𝑒𝑒−𝑉𝑉𝐷𝐷𝐷𝐷𝑛𝑛𝑇𝑇/𝑞𝑞
– This is not valid in strong inversion. It leads to excessively high current for 𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇
• For 𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇
𝐼𝐼𝐷𝐷 =𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 −
𝑚𝑚2𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓2
– This is not valid in sub-threshold and leads to negative current for 𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝑇𝑇 • First method – Single equation:
𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷,𝑑𝑑𝑠𝑠𝑓𝑓 + 𝐼𝐼𝐷𝐷,𝑖𝑖𝑖𝑖𝑖𝑖
Yogesh S. Chauhan, IIT Kanpur 39
• Good enough for Digital applications, but the derivatives are discontinuous making it unsuitable for Analog cases. 12/3/2014
Sub-threshold to strong inversion transition • Second method – Single equation: Use effective
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 as
𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 =
2𝑙𝑙𝑘𝑘𝑘𝑘𝑞𝑞 𝑙𝑙𝑙𝑙 1 + exp 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇
2𝑙𝑙𝑘𝑘𝑘𝑘/𝑞𝑞
1 + 2𝑙𝑙 𝑒𝑒𝑑𝑑𝑒𝑒 −𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 − 2𝑉𝑉𝑜𝑜𝑓𝑓𝑓𝑓
2𝑙𝑙𝑘𝑘𝑘𝑘/𝑞𝑞
• 𝑙𝑙 is the ideality factor and lies between 1 and 2. • Voff is a parameter for fringing from width side.
Assume Voff=0 for further analysis. • For 𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇, the exponential term inside ln() is
larger than 1 making 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 • For 𝑉𝑉𝐺𝐺𝐺𝐺 ≪ 𝑉𝑉𝑇𝑇,
𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 ≈𝑘𝑘𝑘𝑘𝑞𝑞𝑒𝑒𝑑𝑑𝑒𝑒
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑙𝑙𝑘𝑘𝑘𝑘/𝑞𝑞
Yogesh S. Chauhan, IIT Kanpur 40 12/3/2014
Single equation for drain current • Use 𝑉𝑉𝐷𝐷𝐺𝐺,𝑑𝑑𝑎𝑎𝑡𝑡 = 𝑉𝑉𝐺𝐺𝐷𝐷𝑇𝑇,𝑒𝑒𝑜𝑜𝑜𝑜+2𝑛𝑛𝑇𝑇/𝑞𝑞
𝑚𝑚, where 2𝑘𝑘𝑘𝑘/𝑞𝑞 is added for numerical stability
when 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 ≪ 2𝑘𝑘𝑘𝑘/𝑞𝑞. • We have written ID as follows valid from linear to saturation-
𝐼𝐼𝐷𝐷 =𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 −
𝑚𝑚2𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓2
𝐼𝐼𝐷𝐷 =𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 −
𝑚𝑚2𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓 𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓
• Now drain current becomes,
𝐼𝐼𝐷𝐷 =𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 −
𝑚𝑚2𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓
𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓
𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 + 2𝑘𝑘𝑘𝑘/𝑞𝑞𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓
𝐼𝐼𝐷𝐷 =𝑊𝑊𝐿𝐿𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 1 −
𝑚𝑚2
𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓
𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 + 2𝑘𝑘𝑘𝑘/𝑞𝑞𝑉𝑉𝐷𝐷𝐺𝐺,𝑒𝑒𝑓𝑓𝑓𝑓
• This is valid for all Vgs and Vds.
Yogesh S. Chauhan, IIT Kanpur 41 12/3/2014
Terminal Charges and Charge Partition
• AC and Transient simulation need capacitances.
• Quasi-static approximation – The Channel charge is assumed
to respond instantaneously to any change in the bias voltage.
• From 𝑄𝑄𝑖𝑖′, we need to find QG, QB, QS and QD.
Yogesh S. Chauhan, IIT Kanpur 42 12/3/2014
Total inversion charge • Before delving into QG, QS and QD. Let us find the total
inversion charge in the channel, 𝑄𝑄𝑖𝑖. • The charge per unit area, 𝑄𝑄𝐼𝐼′, is given as
𝑄𝑄𝐼𝐼′ = −𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 − 𝑚𝑚𝑉𝑉𝐶𝐶𝐺𝐺 𝑑𝑑 • We need to know 𝑉𝑉𝐶𝐶𝐺𝐺 𝑑𝑑 =?
• Define α = 1 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑜𝑜𝑜𝑜
𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 which gives,
𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑜𝑜𝑜𝑜
𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠= 1 − α,
Thus
𝑽𝑽𝑪𝑪𝑪𝑪 =𝑽𝑽𝑮𝑮𝑪𝑪𝑮𝑮,𝒆𝒆𝒆𝒆𝒆𝒆
𝒎𝒎𝟏𝟏 − 𝟏𝟏 −
𝒙𝒙𝑳𝑳𝟏𝟏 − 𝜶𝜶 𝟐𝟐
Yogesh S. Chauhan, IIT Kanpur 43 12/3/2014
Total inversion charge • The charge per unit area, 𝑄𝑄𝐼𝐼′, is given as
𝑄𝑄𝐼𝐼′ = −𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 − 𝑚𝑚𝑉𝑉𝐶𝐶𝐺𝐺 𝑑𝑑
𝑄𝑄𝐼𝐼′ = −𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 1 −𝑑𝑑𝐿𝐿
1 − 𝛼𝛼 2
• Thus total inversion charge
𝑄𝑄𝐼𝐼 = −𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜′ � 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 1 −𝑑𝑑𝐿𝐿
1 − 𝛼𝛼2 𝑑𝑑𝑑𝑑𝐿𝐿
0
• Total inversion charge
𝑄𝑄𝐼𝐼 = −23𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓
1 + 𝛼𝛼 + 𝛼𝛼2
1 + 𝛼𝛼
Yogesh S. Chauhan, IIT Kanpur 44 12/3/2014
Source-Drain charge partitioning • We know, 𝑄𝑄𝐼𝐼 = 𝑄𝑄𝐺𝐺 + 𝑄𝑄𝐷𝐷 but not the exact share of each. • The assignment of the channel charge to the source and
drain charges is called charge partition. • Charge partitioning
– 50/50 partition: Arbitrarily assign 50% of 𝑄𝑄𝐼𝐼 to 𝑄𝑄𝐺𝐺 and 50% to 𝑄𝑄𝐷𝐷.This is valid only when 𝑉𝑉𝐷𝐷𝐺𝐺 is small. For 𝑉𝑉𝐷𝐷𝐺𝐺~0, MOSFET is symmetrical and 𝑄𝑄𝐺𝐺~𝑄𝑄𝐷𝐷~𝑄𝑄𝐼𝐼/2.
– 0/100 partition: This is based on the logic that in saturation, the pinch off region implies that 𝑄𝑄𝐷𝐷 = 0, which is actually not correct.
– 40/60 partition: This is a more physical distribution of charges. One should note that the charge distribution under this scheme is 40/60 only in saturation. However this partition scheme is valid in all regions.
Yogesh S. Chauhan, IIT Kanpur 45 12/3/2014
Source-Drain charge • Ward-Dutton partitioning scheme
𝑄𝑄𝐷𝐷 = 𝑊𝑊∫ 𝑜𝑜𝐿𝐿𝑄𝑄𝐼𝐼′𝑑𝑑𝑑𝑑
𝐿𝐿0 , 𝑄𝑄𝐺𝐺 = 𝑊𝑊∫ 1 − 𝑜𝑜
𝐿𝐿𝑄𝑄𝐼𝐼′𝑑𝑑𝑑𝑑
𝐿𝐿0
• Drain charge
𝑄𝑄𝐷𝐷 = 𝑊𝑊�𝑑𝑑𝐿𝐿 𝑄𝑄𝐼𝐼
′𝑑𝑑𝑑𝑑𝐿𝐿
0= −𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓 �
𝑑𝑑𝐿𝐿 1 −
𝑑𝑑𝐿𝐿 1 − 𝛼𝛼2 𝑑𝑑𝑑𝑑
𝐿𝐿
0
𝑄𝑄𝐷𝐷 = −2
15𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓3𝛼𝛼3 + 6𝛼𝛼2 + 4𝛼𝛼 + 2
(1 + 𝛼𝛼)2
• Similarly, 𝑄𝑄𝐺𝐺 = 𝑊𝑊∫ 1 − 𝑜𝑜
𝐿𝐿𝑄𝑄𝐼𝐼′𝑑𝑑𝑑𝑑
𝐿𝐿0 = − 2
15𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜′ 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓
2𝛼𝛼3+4𝛼𝛼2+6𝛼𝛼+31+𝛼𝛼 2
Yogesh S. Chauhan, IIT Kanpur 46
Ref.: S.-Y. OH, D. E. WARD and, A. W. DUTTON, “Transient Analysis of MOS Transistors,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 4, AUGUST 1980.
12/3/2014
Gate and Bulk charge • Total gate charge
𝑄𝑄𝐺𝐺 = 𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜′ �𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑓𝑓𝑓𝑓
𝑚𝑚𝑚𝑚 − 1 +
23∙
1 + 𝛼𝛼 + 𝛼𝛼2
1 + 𝛼𝛼
+ 2 𝑚𝑚 − 1 2𝜙𝜙𝐹𝐹 − 𝑉𝑉𝐵𝐵𝐺𝐺 �
• Finally Bulk charge, 𝑄𝑄𝐵𝐵 = − 𝑄𝑄𝐺𝐺 − 𝑄𝑄𝐼𝐼
• Capacitance 𝐶𝐶𝑚𝑚𝑖𝑖 = 𝜕𝜕𝑄𝑄𝑚𝑚
𝜕𝜕𝑉𝑉𝑛𝑛
Yogesh S. Chauhan, IIT Kanpur 47 12/3/2014
Charge and Capacitance plots
Yogesh S. Chauhan, IIT Kanpur 48 12/3/2014
Real Device Effects
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 49
Parasitic Source-Drain Resistance
• The main effect of the parasitic resistance is that Vgs in the Ids equations is reduced by Rs·Ids
Yogesh S. Chauhan, IIT Kanpur 50
)(1 0
0
tgs
sdsat
dsatdsat
VVRI
II
−+
≈
12/3/2014
High-Frequency performance
Yogesh S. Chauhan, IIT Kanpur 51
S
GRin
Rd
Rs
D
Low FrequencyModel
S
GRin
Rd
Rs
D
Low FrequencyModel
High-frequency performance is limited by input R and/or C.
iielectrodegin RRR += −
Intrinsic input resistance Gate-electrode resistance
12/3/2014
Gate-Electrode Resistance
Yogesh S. Chauhan, IIT Kanpur 52
Multi-finger layout greatly reduces the gate electrode resistance
212/ fggelectrodeg NLTWR ρ=−
ρ : resistivity of gate material, Wf : width of each gate finger, Tg : gate thickness, Lg : gate length, Nf : number of fingers.
Drain
Source
Rg-electrode
12/3/2014
Bulk MOSFET
• Drain current in MOSFET (ON operation)
𝐼𝐼𝑂𝑂𝑂𝑂 = 𝜇𝜇𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝐻𝐻 2
• Drain current in MOSFET (OFF operation)
𝐼𝐼𝑂𝑂𝐹𝐹𝐹𝐹 ∝ 10𝑉𝑉𝐺𝐺𝐷𝐷−𝑉𝑉𝑇𝑇𝐻𝐻
𝐺𝐺 • Desired • High ION (↓L, ↑Cox, ↑VDD-VTH) • Low IOFF (↑VTH, ↑S)
12/3/2014
Cox=εox/tox=oxide cap. S – Subthreshold slope
Yogesh S. Chauhan, IIT Kanpur 53
Technology Scaling • Each time the minimum
line width is reduced, we say that a new technology node is introduced.
• Example: 90 nm, 65 nm, 45 nm – Numbers refer to the
minimum metal line width.
– Poly-Si gate length may be even smaller.
Yogesh S. Chauhan, IIT Kanpur 54 Figure source - Wikipedia
12/3/2014
Technology Scaling • Scaling – At each new node, all geometrical
features are reduced in size to 70% of the previous node.
• Reward – Reduction of circuit size by half. (~50% reduction in area, i.e., 0.7 × 0.7 = 0.49.) – Twice number of circuits on each wafer – Cost per circuit is reduced significantly.
• Ultimately – Scaling drives down the cost of
ICs.
Yogesh S. Chauhan, IIT Kanpur 55 12/3/2014
Scaling and Moore’s Law • Number of components per IC function will double every
two years – April 19, 1965 (Electronics Magazine) • Shorthand for rapid technological change!
Source: http://www.intel.com/pressroom/kits/events/moores_law_40th/
Still working!
Yogesh S. Chauhan, IIT Kanpur 56 12/3/2014
Threshold Voltage Roll-Off
Energy band diagram from source to drain when Vgs=0V and Vgs=Vt. A-b long channel; c-d short channel.
Vt decreases at very small Lg. It determines the minimum acceptable Lg because Ioff is too large when Vt becomes too low or too sensitive to Lg.
Yogesh S. Chauhan, IIT Kanpur 57 12/3/2014 Source: Chenming Hu – Modern Semiconductor Devices for Integrated Circuits
Channel Length Modulation Pinch off point moves towards the source as Vds increases
DS DSsatV V∆ ∝ −
long channel Short channel
0 01 1 ds dsatDsat Dsat Dsat
A
V VLI I IL V
−∆ = + = +
Esat Em
C.Hu, Modern Semiconductor Devices for IC, 2009 Prentice Hall
Av reduces 12/3/2014 Yogesh S. Chauhan, IIT Kanpur 58
Technology Trend
12/3/2014
Product
Source : www.intel.com
Performance
Yogesh S. Chauhan, IIT Kanpur 59
Wasn’t that smooth ride?
• Where is the bottleneck?
𝐼𝐼𝑂𝑂𝑂𝑂 = 𝜇𝜇𝑊𝑊𝐿𝐿𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝐻𝐻 2
• VTH can’t be decreased – why? • Subthreshold slope gets worse!
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 60
Thin Depletion Layer - Problem
Gate
Source Drain
Body
Oxide Cg
• QG = Qi+Qb • Charge sharing
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 61
Short Channel – Big Problem
Gate
Source Drain
Oxide Cg
Cd
MOSFET becomes “resistor” at small L. Chenming Hu, “Modern Semiconductor Devices for ICs” 2010, Pearson
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 62
Making Oxide Thin is Not Enough
Gate
Source Drain
Leakage Path
Gate cannot control the leakage current paths that are far from the gate.
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 63
What can we do?
12/3/2014
Gate
Source Drain
Leakage Path
Yogesh S. Chauhan, IIT Kanpur 64
May 4, 2011 The New York Times Front Page
• Intel will use 3D FinFET at 22nm
• Most radical change in decades
• There is a competing SOI technology
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 65
One Way to Eliminate Si Far from Gate Thin body controlled By multiple gates.
Gate
Gate
Source Drain
FinFET body is a thin Fin.
N. Lindert et al., DRC paper II.A.6, 2001
Gate Length
Sour
ce
Drai
n
Fin Width Fin Height
Gate Length
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 66
40nm FinFET – 1999
30nm Fin allows 2.7nm SiO2 & undoped body
ridding random dopant fluctuation.
66mV/dec
X. Huang et al., IEDM, p. 67, 1999 12/3/2014 Yogesh S. Chauhan, IIT Kanpur 67
Introduced New Scaling Rule
Leakage is well suppressed if
Fin thickness < Lg 10nm Lg AMD
2002 IEDM 5nm Lg TSMC
2004 VLSI 3nm Lg KAIST
2006 VLSI
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 68
Two Improvements Since 1999
• 2002 FinFET with thin oxide on Fin top F.L.Yang et al. (TSMC) 2002 IEDM, p. 225.
• 2003 FinFET on bulk substrate T. Park et al. (Samsung) 2003 VLSI Symp. p. 135.
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 69
State-of-the-Art 14nm FinFET
Source: Anandtech
Taller and Thinner Fins for increased drive current and performance
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 70
BSIM Family of Compact Device Models
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 71 BSIM: Berkeley Short-channel IGFET Model
1990 2010 2000 1998 2005 1995
BSIM3
BSIM4
BSIMSOI
BSIM-CMG & BSIM-IMG
BSIM6
Conventional MOSFET
Silicon on Insulator MOSFET
Multi-Gate MOSFET
New
BSIM-CMG and BSIM-IMG
• Berkeley Short-channel IGFET Model
• First industry standard SPICE model for IC simulation
• Used by hundreds of companies for IC design since 1997
• BSIM FinFET model became industry standard in March 2012
It’s Free 12/3/2014 Yogesh S. Chauhan, IIT Kanpur 72
Common-Multi-Gate Modeling • Common Multi-gate (BSIM-CMG):
– All gates tied together
– Surface-potential-based core I-V and C-V model – Supports double-gate, triple-gate, quadruple-gate,
cylindrical-gate; Bulk and SOI substrates
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 73
BSIM-CMG Model
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 74
Surface potential obtained by solving the 1D Poisson’s equation
2
2Body DopingInversion Carriers
chB BqVqφ qφqψi kT kT kT kT
Si
qnψ e e e ex ε
− − ∂= ⋅ ⋅ ⋅ + ∂
Vg
Vg
x
n+ n+ y Vs Vd NA
Net Surface Potential Inversion Carriers only Perturbation due to finite doping
inv pertψ ψ ψ= +
M. V. Dunga et al.,TED 2006
A Perturbation approach is used to handle finite body doping
BSIM-CMG Model • Drain current derived from drift-diffusion
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 75
0.0 0.5 1.0 1.50
500µ
1m
Vg = 0.9V
Vg = 1.2V
Vg = 1.5V
Na = 3e18cm-3
Drai
n Cu
rrent
(A)
Drain Voltage (V)0.0 0.5 1.0 1.50
500µ
1m
Drai
n Cu
rrent
(A)
Gate Voltage (V)
Na = 3e18 cm-3
Vd = 0.1 Vd = 0.2 Vd = 0.4 Vd = 0.6
M. V. Dunga, UCB Ph.D. Thesis
Global fitting with 30nm–10µm FinFETs
BSIM-CMG
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 76
Modeling of Germanium FinFETs @10nm
• Ge FinFET may be used in 10nm node for better P-FinFET.
• Industry standard BSIM FinFET model can now model Ge FinFET.
• Early availability of a unified Si/Ge FinFET model facilitates technology-circuits co-development.
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 77
Modeling of Germanium FinFETs @10nm
• Due to the lower m* of holes in Ge the charge-centroid is farther away from the oxide interface resulting in a weaker SR scattering.
• Ge mobility has a weaker dependence on Eeff up-to ∼0.5 MV/cm as the impact of SR scattering is only seen at much higher Eeff in Ge as compared to Si.
20nm
S. Khandelwal et. al., "Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model", IEEE Electron Device Letters, July 2014.
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Modeling of InGaAs FinFET @10nm
Data from: J. J. Gu et al. IEDM 2012 L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4.
S. Khandelwal et. al., "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling, Washington D.C., USA, June 2014. 12/3/2014 Yogesh S. Chauhan, IIT Kanpur 79
Transistor Pathway
Source: Applied Materials 12/3/2014 Yogesh S. Chauhan, IIT Kanpur 80
FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard
Authors Chapters Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan, Samsung Sourabh Khandelwal, UCB Ai Niknejad, UCB Chenming Hu, UCB
1. FinFET- from Device Concept to Standard Compact Model 2. Analog/RF behavior of FinFET 3. Core Model for FinFETs 4. Channel Current and Real Device Effects 5. Leakage Currents 6. Charge, Capacitance and Non-Quasi-Static Effect 7. Parasitic Resistances and Capacitances 8. Noise 9. Junction Diode Current and Capacitance 10. Benchmark tests for Compact Models 11. BSIM-CMG Model Parameter Extraction 12. Temperature Effects
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Book
Acknowledgement
• My students • BSIM team • CMC members
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