Characterization and production testing of a quad 12-bit 40 Ms/sec A/D converter with automatic digital range selection for calorimetry.
11th Workshop on Electronics for LHC and Future ExperimentsHeidelberg, September 12-16, 2005
K. Kloukinas, S. Bonacini, A. Marchioro CERN PH/MIC-DG
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Outline
The AD41240 A/D Converter
Work MotivationDesign Architecture
Prototype Characterization
Production Testing
Summary
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Work Motivation
Required the development of an ADC and a Preamplifier chip: Preamplifier with 3 parallel channels of different gains. ADC having 12 bit resolution plus 2 bits of range selection. Range switching decision is made on the ADC digital logic.
Digital range switching avoids the design difficulties of an analog range switching system.
1
6
12
MGPA
12 bits
2 bits
LOGIC
Multi-channel ADCopto-electricbarrel: APDendcap: VPT
CMS Electromagnetic Calorimeter (ECAL) readout Requirements for High precision and Wide dynamic range.
Would require an ADC of ~14-bit resolution, 40MHz, low power. Radiation hardness requirement render unusable most commercial components.
Solution: a system of multiple gain ranges to span the overall dynamic range. Digitizing and transmitting only the highest unsaturated range.
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The ADC Macro CellADC Macro cell
Key features Dual channel Pipeline ADC macro cell Pipeline stages: 6 High Resolution: 12-bit High Speed: 40 MSPS Low power: <150 mW/ch @ 2.5V, 40 MHz CMOS 0.25 μm commercial process
using Radiation Tolerant layout design techniques
Developed by ChipIdea Microelectronica S.A.
Lisbon, Portugal Macro cell design has been presented at the
9th LECC Workshop,Amsterdam, 2003. Dual channel ADC
Architecture Resolution Speed
Flash 8 bits 250Msps – 1Gsps
SAR 10 bits – 16 bits 7s ksps – 250 ksps
Integrating > 18 bits < 50 ksps
Sigma-Delta > 16 bits > 200 ksps
Pipeline 12 bits – 16 bits 1 Msps – 80 Msps
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The AD41240 Multi-channel ADC
A/D macro cell
A/D macro cell
A/DA/D
A/DA/D
Selection logic
Ain_0
Ain_1
Ain_2
Ain_3
DoutA <11:0>
DoutB <11:0>VCM
Vbg Key features Quad channel Pipeline ADC Single 2.5 V power supply 600 mW total power dissipation
All channels active, @ 2.5V, 40MHz Possibility to power down unused channels. On-chip Bandgap Voltage generator (Vbg)
and Common Mode Voltage generator (VCM) Very few external components.
Input signal differential 1.78 Vpp Vcm = 1.15 V – 1.35 V
Dual 12-bit LVDS output data busses. Digital output Selection Logic permits various
modes of operation.
Joint development of CERN and ChipIdea Microelectronica S.A. ADC Macro cell
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Single ADC Mode Single ADC, Multi-Range operation
14-bit Data Output bus @ 40MHz DoutA <11:0> : 12-bit digitized data DoutB<1:0> : 2 range selection bits
Two sub-modes: Direct
The first non-saturated ADC channel is selected. Hysteresis
Range selection switching is delayed for 5 clock cycles for decreasing signals.
Preserves the sampling of a pulse within one gain range.
Output Data Busses operating in the “Single Channel” mode
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns
CLKin
DoutA[11:0]
DoutB[1:0]
[D11:D0] data bits[D11:D0] data bits [D11:D0] data bits [D11:D0] data bits [D11:D0] data bits
[R1:R0] range bits[R1:R0] range bits [R1:R0] range bits [R1:R0] range bits [R1:R0] range bits
tod3
tod4
A/D macro cell
A/DA/D
A/DA/D
Selection logic
DoutA <11:0>
DoutB <1:0>VCM
VbgAin_0
Ain_1
Ain_2
Ain_3
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Quad ADC Mode Quad ADC
Unused channels can be powered down.
Two multiplexed 12-bit output data busses operating in Double Data Rate mode (80MHz).
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns
CLKin
DoutA[11:0]
DoutB[11:0]
ch.#0ch.#0 ch.#1 ch.#0 ch.#1 ch.#0 ch.#1
ch.#2ch.#2 ch.#3 ch.#2 ch.#3 ch.#2 ch.#3
tod1 tod2
A/D macro cell
A/DA/D
A/DA/D
Selection logic
Ain_0
Ain_1
Ain_2
Ain_3
DoutA <11:0>
DoutB <11:0>VCM
Vbg
Output Data Busses operating in the “Quad Channel” mode
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The AD41240
VCMIBIAS
A/D macro cell
Digital Selection Logic
Microphotograph of the AD41240 chip.
A/D macro cell
Vbg
Features A/D Macro Cell Area = 3.96mm2
Total Die size = 11.8mm2
Radiation Tolerant, 0.25 μm CMOS. Package: 13x13mm, 144 pin fpBGA 1.7mm heigh, 1.0mm pitch
144 pin fpBGA Package
Pin-out layout that:minimizes signal crosstalk,separates analog – digital signalsand eases PCB design
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AD41240 applications CMS ECAL
Single ADC mode with hysteresis.
CMS Preshower Quad ADC mode.
LHC Beam Loss Monitoring System Prevents the superconducting magnets from quenching. 3,600 detectors placed at various locations
around the LHC machine ring. Radiation Environment
VFE board
Motherboard
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ADC Characterization
Device characterization performed by: ChipIdea S.A. Testing & Characterization division. Equipment availability. QMS-ISO 9001 certified Test procedure know how. ADC macro cell designers. CERN supervision.
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ADC specifications definitionOutup
Code
VinVLSBVcode(n)
Code(n)
SFDR
Sp
noise floor
Fs/2
A0
H1 H2 H3H4H5H6H7
freqFin F H 1
Outup Code
Vin
INLcode(n)
LSB
LSBncode
V
VVnDNL
)()(
Differential Non Linearity
0)12()0(,)()(1
Nn
m
INLINLmDNLnINL
Integral Non Linearity
2/
1 1)())((
)(
Fs
n nFHnnf
Fin
PP
PSNR
Signal to Noise Ratio
2/
1))((
)(
Fs
nnf
Fin
P
PSINAD
Signal to Noise and Distortion Ratio
02.6
763.1SINAD
ENOB
Effective Number of Bits
Finf
Fin PincludingnotPMAX
PSFDR ,
)( )(
Spurious Free Dynamic Range
Static Parameters
Dynamic Parameters
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ADC Characterization Setup
Data Out Capture Memory
Digital VectorMemory
DUT
Clock & Synchronization
clk
ADCWaveformSynthesizer
Digital Signal Processing
DSP-based ADC characterization method. Sinusoidal input waveform (Full scale signal) Coherent sampling Histogram Testing Fast Fourier Transform Testing
Industry Standard methodology.
Histogram
FFT
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Characterization Method Static Parameters
Histogram Testing
Dynamic Parameters FFT Testing
Probability Density Function of a sine wave input signal.
)(
)()()(
iH
iHiHiDNL
ideal
ideal
,)()(1
i
j
jDNLiINL
Spectral Analysis
SNR, SINAD
ENOB, SFDR
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AD41240 Characterization Results
Fin (input signal) set to -0.7dB(Full Scale) @ 2.5MHz
Fin = 1MHz Fin = 2.5Mhz Fin = 10MHz
INL ±0.66 ±0.65 ±0.77 LSB
DNL ±0.31 ±0.35 ±0.42 LSB
ENOB 11.2 11.1 10.8 Bit
SINAD 68.9 68.8 66.9 dB
SNR 69.3 69.2 67.5 dB
THD -76.3 -75.9 -72.8 dB
SFDR 78 78 74 dB
Final characterization results
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AD41240 Characterization Results
DNL & INL variation with input signal frequency.
Test conditions: Quad ADC mode Temp: 25OC Fs = 40MHz Fin = -0.5dB(full scale)
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AD41240 Characterization Results
SNR & SINAD variation with input signal frequency.
Test conditions: Quad ADC mode Temp: 25OC Fs = 40MHz Fin = -0.5dB(full scale)
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Irradiation Tests Irradiation of a sample set @ CERN
Chips from engineering run in ceramic packages. Radiation Source: X-ray machine. (Dose rate = 2.04 Mrad/h). Samples were biased and clocked during irradiation. Pre & post-irradiation characterization of the sample set.
Up to the 10 Mrad Total Ionizing Dose (SiO2 TID). All samples were functional. Analog performance was maintained. Power consumption showed no significant increase.
Bandgap Voltage changes with TID. ΔVbg = 11.8 % @ 10 Mrad Saturation reached at 1Mrad. Affected parameters:
VCM: <0.40 %, Offset error: <0.70 %, Gain error: <0.22 %
Can be corrected through calibration cycles.0,00
0,02
0,04
0,06
0,08
0,10
0,12
0,14
0,16
0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 8,0 9,0 10,0
Dose [MRads]
ΔV
BG
[V
olt
s]
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AD41240 Production Testing
Production volume : 100,000 ADC chips
High fabrication process yield expected. Demonstrated in prototype run & engineering run
=> Production testing on packaged chips.
ADC requires a Mixed Signal Production Tester.
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AD41240 Production Testing
Outsourcing to external company(s) Two step procedure:
Testbench development Device Interface Board design and fabrication. Definition of Test Specifications Characterization test-bench to Production test-bench correlation.
Production Testing performed on Automated Test Equipment.
Three companies have been contacted. High development cost for the testbench.
In house testing at CERN Low development cost for the testbench.
Slightly higher production cost due to manual labor. Significantly longer testing time.
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Production Testbench at CERN
GP
IB
Visual Basic for: System automation Graphical User Interface
MATLAB scripts for: Data analysis
BP Filter
Agilent 33220A
Agilent 35970A
DUTLVDS
to CMOS
CMOS to LVDS
Single to differential
FPGA
USB 2
Wavetech
40MHz clock
mode
:2 :2
:2
SRAM1MB
Agilent E3631A
USB
Control PC
Input signal1MHz
GPIBDevice Interface Board
Power Supply
Digital Multimeter
Clock Generator
Idc,Vbg, Vcm
analogdigital power
Signal Generator
Data Capture Board
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Production Testing Lab
Engineers:Kostas KloukinasSandro Bonacini
Testing Lab in building 11 at CERN Production Tester
operated by one technician.
Manual chip handling.
Testing times per chip Testing: 12 secs Handling: 13 secs Total: 25 secs
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Test Flow Diagram
Static (DC) Tests
Functional Tests
REJECTACCEPT
Fail
Fail
Fail
Pass
Pass
Pass
DC Measurements: Idc (total current consumption),Vbg (bandgap voltage),Vcm (common mode voltage)
Functional Tests:Histogram shape.Range Switching.
Performance Tests:
Static Parameters:Offset & DC gain, INL, DNL
Dynamic Parameters:THD, SNR, SFDR, ENOB
Apply Power to DUT
Performance Tests
Release Power to DUT
Acquire ADC channels
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Graphical User Interface
Easy to use No technical expertise
needed by the operator.
Datalogs for testbench calibration & monitoring.
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Tester Calibration
LTL & UTL readjustments during the first days of operation Reject marginal devices by tightening LTL & UTL.
Preference to disqualify than to ship bad devices.
LSL LTL UTL USL
Passing Region
Failing Region
Failing Region
ε ε
LSL: Lower Specification LimitUSL: Upper Specification Limit
Setting acceptance levels for the test parameters. Dealing with the uncertainty of the measurements in the tester. Tester’s measurement error (σ) estimated from
repetitive acquisitions performed on the same device. ‘Guardbanding’
LTL: Lower Threshold LimitUTL: Upper Threshold Limit
ε: measurement uncertainty (ε = 3σ)
pdff(x)
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Statistical Process Control
Monitor statistical distributions of performance parameters on day-to-day basis.
Verify that the mean value and the spread does not fluctuate.
Identify device parameters that exhibit excessive variations.
tim
e
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Test Results Logging
Typical log file analysis results Log file generation on day-to-day basis. Record parameters for every tested chip. MATLAB scripts for data analysis
Monitor production tester operation. Component failure analysis
Similarity of production testbench with the characterization testbench made easier the correlation of their measurements.
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Production Test Results
70,000 chips tested. (12/9/2005)
Observations: Small spread of specification parameter
distributions. Stable parameters through different production lots. Good parameter matching with characterization
measurements as reported on the final product ‘Characterization Test Report” by ChipIdea.
Production Yield : 82.3 %
Failures due to:
Functionality cuts : 14.2 %(Including Idc, Vbg, Vcm out of specs)
Performance cuts : 3.5 %(INL, DNL, ENOB, SNR, SINAD, SFDR)
μ σ
Idc 0.257 mA 0.002 mA
Vbg 1.183 V 0.003 V
Vcm 1.205 V 0.001 V
DNL 0.40 LSB 0.07 LSB
INL 0.70 LSB 0.09 LSB
SFDR 79.40 db 0.82 db
ENOB 11.07 bits 0.036 bits
Cumulative results
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Production Testing
Production rate: 150 chips/hour. Daily schedule: 8 hours/day. Average production: 1,100 chips /day
Good chips are placed in trays, sealed and labeled before shipping.
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Production Status & Planning
ADC Deliveries as of today CMS ECAL Barrel -> 66,000 chips CMS Preshower -> 300 chips LHC machine -> 30 chips
Scheduled Deliveries CMS ECAL EndCaps : 12,800 chips CMS Preshower : 2,700 chips LHC machine : 1,700 chips
Planning 33,000 chips pending for testing. Restarting production testing.
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Summary
AD41240 a key component for the CMS ECAL readout system. Other users: CMS Preshower, LHC machine Beam Monitor system.
AD41240 successful collaboration of CERN & ChipIdea S.A. ChipIdea S.A. received the “CMS Gold Award of the year 2005”.
Component characterization Performance parameters in compliance with design specifications. Fulfils target application requirements.
Production testing performed on a custom made testbench at CERN delivering on time all necessary component quantities. In house production testing proved to be a cost effective solution. High production yield attained: 82.3 %
The AD41240 is a general purpose ADC for applications requiring high
resolution, high speed and low power in a high Radiation environment.
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