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A S-VHS compatible 1/3” 720(H) * 588(V) FT-CCD
with low dark current by surface pinning
Ja n T. Rosiers, Herman L. Peek, Agnes C. Kleimann, Noortje J . Daemen,
Edwin Roks, Arjen C;. van der Sijde, RenC M. Jansen, Peter Opmeer
Philips Research L aboratories Eindhoven - WAG-1
P.O. Box 80 000, 5600 dA. Eindhoven, The Netherlands
ABSTRACT A cross-section along the transport direction is shown in
Fig.2.
A CCD imager for a low-cost com pact S-VHS camcorder
is presented. Wit h th e introduction in a frame-transfer CCD
of mosaic color filters, fast frame shift, on-chip drivers and
surface pinning, t he optical form at for S-VHS resolution coulld
be reduced fr om 2/3” to 1/3” with out sacrificing performance. d’e’eCtr’C oxide
XB /I XA U XB 11 XA/;1 T;\ R
~ - -N
INTRODUCTION OP
The trend i n consumer camcorders is clearly towards mare
compa ct cameras with increasing resolution and improved lowlight-level imaging. The FT-CCD imager presented here was
especially designed for such an application: the required phys-
ical volume in the camcorder was reduced by using a snlitll
CC D ( 1 /3” image diagonal format), by a low smear operation
without mechanical shutter through fast frame shift and by
the use of on-chip drivers. The combination of mosaic color
filters with an FT-CCD and a significant reduction of dark
current by surface pinning allow high resolution color imag,es
with low noise even at low illumination levels.
IMAGE PIXEL
The basic image pixel is a four phase cell constructed of
two polysilicon layers, using two short poly-1 (XA) an d tw o
long poly-2 (XB) electrodes per pixel. A perspective view of
th e image pixel is given in Fig.].
( X A )2A
Fig.l .Perspective view of ima ge cell
Fig.2.Cross section of image cell along transport direction
A conventional n-channel CCD in a profiled p-well on a n-
substr ate is used for vertical antiblooming [l]. The CC D pro-
files are optimised such th at electronic shutter operation, used
for variable ex posure t imes, is achieved by sett ing all image
electrodes to the low clock level, thus flushing the collected
electrons to the n-substrate (called ”charge reset”).
FAST FRAME SHIFT
Since no mechanical shutter can be used in a compact
camco rder , the frame-shift frequency of an FT-CC D has to
be increased to limit smear. This requires a reduction of
th e RC time constants in th e CCD electrode network. Ca-
pacitances were lowered by significantly reducing th e overlap
of th e polysilicon electrodes. Th e resistances of the CCD
network were drastically reduced by using vertical aluminum
straps ( IN ) , 1 .2 pm wide, over th e light-insensitive pt chan-
nel stops (SP). Thus the frame-shift frequency could be in-
creased from 1 to 15 MHz without any loss in performance.
80dB smear suppression is obtained, comparable t o 1/3” S-
VHS IL-CCD’s [ 2 , 3 ] . (Smear is defined as the spurious signal
collected during fr ame shift, from a highlight l/lOth of the
image height.)
Note that with decreasing image diagonals, an FT-CCD can
achieve lower smear values, since the RC time constants are
reduced. In IL-CCD’s, reducing the CCD size tends to in-
crease the smear since the IL-CCD’s become smaller, and
thus more susceptible to direct collection of light-generated
electrons.
! 5 . 1 . 1
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DESIGN OF STORAGE SECTION, SERIAL
REGISTER AND OUTPUT AMPLIFIER
driver t y p e
switching voltage (VDD=lOV)
power supply voltage V D D
The storage cell is almost identical to the image pixel.
The two-phase readout register was designed using only the
same two poly layers as used in the image cell, as shown in
Fig.3. T he CS mask allows direct contacts from XB to XA
by etching part of th e oxide above XA .
C M O S inverters
2.8V
8 V to 1 2V
gatedielectric
number of poly layers
number of metal layersarea 1 driver
cscontact oxide
2
2
2. 4 1mn2
DP
~ __ ~~-~
Nsub
-~~- ~~ ~.Fig.3.Cros.s section of two-phase serial register
Also the double source-follower output amplifier was con-
structed with only these poly layers.
ON-CHIP DRIVERS
To reduce the number of external components required
to operate the CCD, 15 MHz CMOS-drivers for the image
and storage electrodes were included on-chip. They are po-
sitioned above the image- and below the storage section. A
schematic diagram showing the principle of one image driver
is given in Fig.4.
VDH VDR
VD L
Fig .4 . Schematic diagram of one image driver
CMOS inverters with increasing transistor width gradually
drive increasing capacitive loads. Th e separate power supply
VDR is used for electronic shuttering: when settin g VDR to
GND, the output of the driver is switched to low level, in-
discriminate of t he logical inp ut I N . This provides a simple
method t o implement electronic shutter by charge reset. Th e
layout of one inverter stage is shown in Fig.5.
One extr a p-well implant DP2 is required in t he CCD process
to obtain the correct threshold voltage for the nMOS transis-tors. The input signal is stan dar d logic, the supply voltage
can be varied from 8V to 12V. One driver occupies approx.
2 .4 mm2. The characteristics are summarised in Table 1.
XA oxide XA1
1
\ DP /
Nsub
Fig.5. Layout of one invert er stage
rise time tr (InF load)fall time t f (1nF load)charge reset time (VDR )
35 11s
4011s
10 ps
Table 1 .Summary of on-chip driver characteristics
MOSAIC COLOR FILTERS ON FT-CCD’S
Previously reported FT-CCD’s use R GR o r (:y-Gr-Ye
stri pe color filters for color imaging. To obtain S-VHS resolu-
tion, approx. 1200 pixels per line are required when using on
chip stripe filters [l]. With mosaic filters, S-VHS resolxtion
is obtained with only 72 0 pixels [3].
Color filters were deposited in a mosaic pattern as shown in
Fig.6. Cyan (C y), yellow (Ye) and ma gent a (Mg) filters were
evapor ated and p atte rned using a lift-off process. Green fil-
tering is achieved by overlapping cyan and yellow filters. The
gaps between the filters lie either above the light-insensitive
metal straps, o r above the narrow XA gates. Th e optical sen-
sitivity of these gates is reduced significantly with o u r vertical
n-p-n structur e by setting both of them to the low clock volt-
age durin g integratio n (i.e. ap proach ing charge-reset condi-
tion), t hus limiting th e contribution of ”white” , non-filtered
light on the sensor to obtain good color rendition.
IN
XA
Fig.6. Layout of color filters
5.1.2
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REDUCTION OF DARK CURRENT BY Vertical anti-blooming with electronic shutter is not compro-
SURFACE PINNING mised and charge-transfer efficiency is not degra ded. How-
ever, charge-stora ge capacity is reduced from 70 00 0 electrons
per pixel to 30 000 in AGP mode. Blue sensitivity is notreduced by the shallow layer of holes at the interface, but is
increased since th e 2-phase stru cture allows larger "windows"
TO mprove the performance at low light levels, the mal-
j o r source of noise, FPN (fixed-pattern noise) from surface-
generated dark current had to be reduced.
A way to completely suppress interface sta te generatio n is to
invert the surfac e, i.e. have a layer of holes at the Si-Si02
interface during integration[4]. This was introduced in the
photodiodes of consum er IL-CCD's [5] and in "scientific" full-
frame CCD's [6].
However, introduction in a consumer FT-CCD of an image
cell with a completely inverted surface is not straightforward
since the function of integration and transport are combined
into the same cell, and the other properties of the pixel (anti-
blooiiiing protection, electronic shutter, efficient transport)
may not be compromised when modifying the pixel struc-
ture for pinned operation. Thus, untill now, only the charge-
pumping technique [7] was used in most FT-CCD's: the image
electrodes are pulsed consecutively to a low voltage to invert
the surface. However, this only yields a partial reduction in
surface dark current: for practical reasons, charge-pumping
is limited to the line blanking periods; and at higher tem-
peratures (4OoC), the time constant fo r the recovery rate of
interface-state generation becomes significantly shorter thanthe line time.
We have achieved a CCD pixel for an FT-CCD that has all
gates pinned (AGP) during the whole integration time with-
out sacrificing othe r properties such a s vertical anti-blooming,
electronic reset and efficient charge transport. Only a small
modification to the existing design was required, as shown in
Fig.7. Since all gates are set low for pinning, an a ddition ,d
implant DN2 is introduced self-aligned on XA under the XB
gates to keep the charge packets separate d. This also allows
2-phase operation. The resulting potential profiles are shown
in Fig.8.
gate CSdieleclric contact oxide
Nsub
Fig.7. Cross section of AGP cell along transport direction
Pinning is achieved with the gates 9V below the externallly
applied SP voltage. Th e dark current at 60°C is reduced from
1000 pA/cm2 without pinning to 50 pA/cm2 in AGP mode.
Dark current vs. pinning voltage V P (offset between exter-
nally applied SP voltage and image electrod e voltage) a t 80°C
is shown in Fig.9: in AG P mode, only bulk dark cu rrent Gom
the top 2 pm Si is collected. Dark curren t vs. te mpera ture is
shown in Fig.10.
Note that the dark current accumulated during frame shift(when the image section is not pinned), and in the storage
section does not contribute to the FPN since it is averaged
over 295 lines.
(image area's not covered with polysilicon) in the image pixel
(Fig.11).
0
DN DP Nsub 1
0 2 4 6 8 1 0 1 2
Depth in SI prn)
Fig.8. Potent ial profiles for AGP ope ration
under XA (curve 1) and XB (curve 2 )
1500
N
$ 1000Q
C
-
0* 500
0"
0
7 8 9 10 11 12 13 14
Pinning voltage VP (V )
Fig.9. Dark current vs. pinning voltage
40 60 80 100 120
Temperature (OC)
Fig.10. Dark current vs. temperature
5.1.3
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400 500 60 0 70 0 800
Wavelength (nm)
C C D type
Nuniber of lines
Fig.11. Quantum efficiency vs. wavelength
for conventional and AGP versions
Fiame transfer, 113”
588 (2:l interlacel
TECHNOLOGY
Minimum dimensions in sensor fabrication are 0.8 p m .
A conventional vertical n-p-n structure to achieve blooming
protec tion is used. As already menti oned, only two layers of
polysilicon (0.3 pm, 25 O / o ) are needed. A first aluminum
layer (0.5 pm , 0.05 O / o ) is used for the vertical straps. The
second layer (1.0 pm, 0.025 O/O) is used for all other inter-
connections and for the light screen over the storage area.
The ”pinning” version only needs one additional self-aligned
implant DN2. Th e sensor da ta are summarised in Table 2.
Fig.12 shows a conventional 4-phase device with on-chip ini-
age and storage drivers.
Iage drivers -
image section +
storage section -+
I
storage drivers -+
Fig.12. Chip photo
CONCLUSIONS
A 1 /3” FT-CXD image sensor with 15 MH z frame shift,
on chip drivers and significantly reduced dark current through
surface pinning was presented. S-VHS compatible color imag-
ing is achieved with 720 pixels/line by using mosaic color fil-
ters. Optimi sation of the pixel design in pinned mode is being
carried out to increase the charge storage capacity.
Number of active pixels/line
Pixel size
Clup size
Minimum features
Frame shift frequency
Readout frequency
Smear suppression
Maximum charge-capacity
conventional
AGP
conventional
AGP
Dark current (6OOC)
Image and storage clock swing
Serial clock swing
Color filters
Minimum exposure time
Outamp sensitivity
Outamp noise (5 MHz BW )
720
6. 9 p m H) * 12.6pin (V )
5. 7 (H ) mni * 10.6 (V ) niin
0.8pm
15 MHz
13.5 MHz80 dB
70 000 electroils
30 000 electroils
1000 pA/cm2
5 0 pA/an2
1ov5v
Cy-Gr-YeMg inosaic
1/4000 s
1 2 pV/electron
15 electroils RMS
Table 2. 1 / 3” FT CCD specification and perf ormance
ACKNOWLEDGEMENTS
The authors would like to thank their colleagues in the
CCD group at the Philips Research Laboratories for their
valuable contributions. Especially the assistance of M. teke-
lenburg with the on-chip drivers is acknowledged.
REFERENCES
[l]. J . Bosiers et al., A 2/3” 1188(H) * 484(V) frame-transfer
CCD for ESP and Movie, 1982 Intl. Electron Dev. Conf.,
IEDM’88 Digest pp.70-73.
[Z]. H. Akimoto at al., ”A 1/3-in 410 000-pixel CCD im-age sensor with feedback field-plate amplifier,” IEEE J . Solid
Sta te Circuits, , vo1.38 no.12 pp.1907-1914 (1991).
[3]. C. Mizouchi et al., ”1/3-inch 410 000 pixel IT-CXD im-
age sensor, Proc. In tl. Television Engineering Conference
1992 (ITEC’ 92), pp. 453-454.
[4]. N.S.Saks, ”A technique for suppressing dark current gen-
erated by interface states in buried channel CCD imagers”,
IEEE Electron Dev. Lett., vol.1 no.7, 1980
[5]. N . Teranishi et al., ” N o image lag photodiode structure
in t he interline CCD image sensor”, 1982 Jntl. Electron Dev.
Conf., IEDM’82 Digest pp.324-327.
[6]. J. Janesick, T. Elliot, G. Fraschetti, S.Collins, ”Charge-
coupled device pinning technologies”, SP IE Conf on Optical
Sensors and Electronic Photography, Los Angeles, CA, 1989,
Proc. SPI E vol. 1071-15.
[7]. B. Burke and S. Ciajar, ”Dyna mic Suppression of interface-
state dark current in buried-channel CCD ’s”, JEE E Trans.
Electr . Dev., vo1.38 no.2 pp.285-290 (1991).
5 .1 .4
100-IEDM 92
A th i d li d li it d t T h i I l S h l f T h l D l d d D b 28 2009 t 12 48 f IEEE X l R t i ti l