Zero-Voltage Switching Flyback-Boost Converter with Voltage …koasas.kaist.ac.kr/bitstream/10203/169280/1/Zero-voltage... · 2017-04-13 · Zero-Voltage Switching Flyback-Boost Converter

Zero-Voltage Switching Flyback-Boost Converter with Voltage-Doubler Rectifier for High Step-up Applications

Hyun-Wook Seong, Hyoung-Suk Kim, Ki-Bum Park, Gun-Woo Moon, and Myung-Joong Youn

Department of Electrical Engineering, KAIST 373-1 Guseong-dong, Yuseong-gu, Daegeon, Republic of Korea, 305-701

[email protected]

Abstract -- A zero-voltage switching (ZVS) flyback-boost (FB) converter with a voltage-doubler rectifier (VDR) has been proposed. By combining the common part between a flyback converter and a boost converter as a parallel-input/series-output (PISO) configuration, this proposed circuit can increase a step-up ratio and clamp the surge voltage of switches. The secondary VDR provides a further extended step-up ratio as well as its voltage stress to be clamped. An auxiliary switch instead of a boost diode enables all switches to be turned on under ZVS conditions. The zero-current turn-off of the secondary VDR alleviates its reverse-recovery losses. The operation principles, the theoretical analysis, and the design consideration are investigated. The experimental results from a 250W and 42V-to-400V prototype are shown to verify the proposed scheme.

Index Terms—Zero-voltage switching (ZVS), Voltage-doubler rectifier (VDR), and Step-up ratio.

I. INTRODUCTION

The DC-DC conversion systems powered by battery sources such as high intensity discharge (HID) lamps, uninterruptible power supplies (UPS), fuel cell systems, and LED drivers call for high-performance step-up converters [1]. The major concerns for the step-up converters are how to extend a step-up ratio and how to alleviate the voltage spike across the switching devices led from the leakage inductance of the transformer.

To handle the mentioned concerns, several non-isolated converter topologies have been proposed, since the galvanic isolation is not the critical requirement for those applications [1]-[6]. In [2]-[3], it has been demonstrated that the voltage-doublers using additional diodes and capacitors on the output stage effectively contribute to extend a step-up ratio without the penalty of the extreme duty ratio and to limit the voltage stress of the output rectifiers. However, dissipative protection circuits across the switches increase the cost, losses, and design complexity. Another approach to extend a step-up ratio is using clamp-mode coupled-inductor boost converters [1], [4]. Since the leakage energy can be recycled due to the non-dissipative clamp circuits across the switch, it can achieve a high efficiency as well as protect the switch from the high peak voltage. Nevertheless, the resonance between the leakage inductance and the parasitic capacitance of the

output rectifier produces the high voltage spike. Thus, the snubber network is required across the output rectifier, which results in a degraded efficiency.

As an attractive solution over aforementioned topologies, the flyback-boost (FB) converter was proposed as shown in Fig. 1 [5], [6]. It can achieve a higher step-up ratio due to both a transformer and a parallel-input/series-output (PISO) configuration. Since the voltage spike across the switch is limited to the output voltage of the boost converter, no protection circuit is required. Furthermore, since the energy stored in the leakage inductance is effectively recycled and transferred to the load, a high efficiency can be achieved.

However, despite of those advantageous features, the voltage spike across the output rectifier is inevitable. Thus, to achieve the voltage clamping of the switch and output rectifiers simultaneously, the concept of the voltage-doubler presented in [2], [3] can be adopted in an FB converter [7]. It can protect the output rectifiers from a high peak voltage as well as provide a higher step-up ratio than an FB converter. Moreover, since the boost diode and output rectifier are turned off at zero current, the reverse-recovery losses can be alleviated. Hence, among various alternatives, the FB converter with a VDR is one of the most attractive candidates for high step-up applications.

However, most of abovementioned circuits including the FB converter with a VDR suffer from considerable switching losses due to the hard switching. It confines to increase the switching frequency and to minimize the size of magnetic components and filter capacitors.

Fig. 1. Circuit diagram of the flyback-boost (FB) converter.

978-1-4244-5287-3/10/$26.00 ©2010 IEEE 823

In order to reduce switching losses while maintaining the

advantageous features, a zero-voltage switching (ZVS) FB converter with a VDR is proposed as shown in Fig. 2. By using an auxiliary switch instead of a boost diode in the FB converter, all switches can be turned on under ZVS conditions. Therefore, the proposed converter can ensure the higher operating frequency, higher step-up ratio, lower voltage stresses across the switches and output rectifiers with an improved conversion efficiency. The operation principle and the theoretical analysis are investigated. The experimental results are then presented for the verifications.

II. OPERATION PRINCIPLES OF THE PROPOSED CONVERTER

Fig. 2 shows the circuit diagram of the proposed ZVS FB converter with a VDR. The structure of the proposed converter is the same as that of the FB converter except for the existence of a VDR and an auxiliary switch Q2. The VDR is composed of a link capacitor Cb and rectifying diodes DO1 and DO2. The auxiliary switch Q2 is turned on and off in a complementary way to the main switch Q1. To illustrate the steady-state operation, several assumptions are made as follows: The values of the output capacitors are large enough to be regarded as constant voltage sources VCo1 and VCo2. The link capacitor Cb is kept on being charged with a constant voltage VCb. The magnetizing current ILm is always positive. The leakage inductor Llkg is much less than the magnetizing inductor Lm.

Fig. 3 and Fig. 4 illustrate the steady-state waveforms and topological states of the proposed converter, respectively. To present the operation of each mode sequentially, it is assumed that the switch Q1 was turned off and the switch Q2 was turned on before t0. Due to an auxiliary switch Q2, the regenerated current from the output capacitor CO1 flows to the input source. Thus, the direction of the primary current Ilkg(t) is reversed with a negative slope before t0.

Mode 1 (t0-t1) : At t=t0, the switch Q2 is turned off. The primary leakage current Ilkg(t) charges the junction capacitor of Q2 to VCo1 and discharges that of Q1 to 0V, respectively in a resonant manner for a very brief time. Then, it flows

through the anti-parallel diode of Q1. Therefore, the zero voltage across Q1 is maintained. Since the voltage across the magnetizing inductor VLm is -(VCo2-VCb)/n due to the forward-biased output rectifier DO2, Ilkg(t) is increased linearly as given by the following equation.

20 0

( ) /( ) ( ) ( )I Co Cb

lkg lkglkg

V V V nI t t t I t

L

(1)

Mode 2 (t1-t2) : At t=t1, the switch Q1 is turned on under ZVS conditions while its anti-parallel diode is conducting. The current Ilkg(t) continuously increases with the slope expressed in (1) and reaches the magnetizing inductor current at t2. It means that the rectifier DO2 is turned off at zero current, which can alleviate the reverse-recovery problem.

Mode 3 (t2-t3) : At t=t2, the diode DO2 is turned off. After that, the diverted current through the transformer charges the junction capacitor of DO2 to VCo2 and discharges that of DO1 to 0V for a short time, respectively. Then, it flows through the output rectifier DO1 to charge the link capacitor Cb. Because the applied voltage across Lm is VCb/n, the current Ilkg(t) can be expressed as follows:

2 2

/( ) ( ) ( )I Cb

lkg lkglkg

V V nI t t t I t

L

(2)

Mode 4 (t3-t4) : At t=t3, the switch Q1 is turned off. The current Ilkg(t) charges the junction capacitor of Q1 to VCo1 and discharges that of Q2 to 0V rapidly. Then, it flows through the anti-parallel diode of Q2. Since the voltage across Q1 is clamped to VCo1 due to the anti-parallel diode of Q2, no

DTS (1-D)TS

Q1 Q1Q2

Ilkg

ILm

VQ1

VQ2

VCo1

t0 t1 t2 t3 t4 t5 t6 t7

VLmVCb/n

(VCo2 VCb)/n

VlkgVI VCb/n VI+(VCo2 VCb)/n

VI-VCo1-VCb/n VI VCo1+(VCo2 VCb)/n

ICb

IQ1

IQ2

IDo1

IDo2

VDo1

VDo2

VCo2

Fig. 3. Steady-state waveforms of the proposed converter.

Q1

Co2

Ro VO

Llkg

Q2

Ilkg

Co1

VCo2

1:n

Lm

VCo1

VI

IOVLm

VCb

Cb Do2

Do1

ILm

IDo2

IQ2

ICb

IDo1

Vlkg

IQ1

Fig. 2. Circuit diagram of the proposed ZVS FB converter with VDR.

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protection circuit is required and the conduction loss can be reduced by using lower voltage-rated power switches. The conducted anti-parallel diode provides the zero voltage across Q2 until the next mode. The current Ilkg(t) can be easily obtained as follows:

13 3

/( ) ( ) ( )I Co Cb

lkg lkglkg

V V V nI t t t I t

L

(3)

Mode 5 (t4-t5) : At t=t4, the switch Q2 is turned on under ZVS conditions. The current Ilkg(t) continuously decreases until it reaches the magnetizing current at t5. Since, at t5, the rectifier DO1 is turned off at zero current, the reverse-recovery losses can be reduced.

Mode 6 (t5-t6) : At t=t5, the diode DO1 is turned off. After that, the diverted current through the transformer charges the junction capacitor of DO1 to VCo2 and discharges that of DO2 to 0V for a short time, respectively. Then, it results in conducting the output rectifier DO2 and discharging the link capacitor Cb. The applied voltage across Lm is -(VCo2-VCb)/n and the current Ilkg(t) can be expressed as follows:

1 25 5

( ) /( ) ( ) ( )I Co Co Cb

lkg lkglkg

V V V V nI t t t I t

L

(4)

Mode 7 (t6-t7) : The current Ilkg(t) reaches zero at t6 and keeps the negative slope as (4) until the switch Q2 is turned

off at t7. The reverse-directed current Ilkg(t) flows to the input source.

III. ANALYSIS AND DESIGN CONSIDERATION OF THE PROPOSED

CONVERTER

A. Step-up Ratio

Due to the series-output configurations, each output capacitor voltage is put together and the overall output voltage is extended as

1 2O Co CoV V V . (5)

By imposing the node equations across the output capacitor Co2, the steady-state output current equation can be derived as

2 2( ) ( )O Q DoI I t I t , (6)

where <*> denotes the average value of *. As a matter of convenience to derive the step-up ratio, the

relatively narrow intervals, t0-t2 and t3-t5, are assumed to be zero and the ripple-free current ILm(t) is assumed. Figure 5 shows the simplified current waveforms under these assumptions. By applying the volt-second balance rule on Llkg and Lm and the current-second balance rule on Cb while considering (5) and (6), the step-up ratio of overall system, M,

(a) (b) (c)

(d) (e) (f)

(g)

Fig. 4. Topological states of the proposed converter (a) Mode 1 (t0-t1), (b) Mode 2 (t1-t2), (c) Mode 3 (t2-t3), (d) Mode 4 (t3-t4), (e) Mode 5 (t4-t5), (f) Mode 6 (t5-t6), and (g) Mode 7 (t6-t7).

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can be found as

2

2

1

21

O

I

V nM

V nD Q

D

, (7)

where the dimensionless parameter Q is defined as (LlkgfS)/RO. Provided that Q is small enough, M can be approximated to (n+1)/(1-D) which can represent the step-up ratio of the classical boost converter when n=0.

The step-up ratio of the proposed converter is higher than that of the flyback and FB converter as shown in Fig. 6 (a). Figure 6 (b) shows the step-up ratio M according to Q variations depending on the leakage inductor, output current, and switching frequency fS. As shown in this figure, since the overall step-up ratio M falls as Q increases, the turns-ratio n and the nominal duty ratio D should be selected by considering the damping effect of Q. In practice, because the value of the leakage inductor is a dominant factor affecting the effect of Q, a smaller leakage inductor is preferable to the higher step-up ratio.

However, for a different point of view, the value of the leakage inductor should be higher than the designated value for the ZVS of all switches as will be presented in following section.

B. ZVS Conditions

To achieve the ZVS of the switch Q1, the energy stored in the leakage inductor at t0 must be large enough to fully charge and discharge the junction capacitor of Q2 and Q1, respectively, before the switch Q1 is turned on. Following equations are the ZVS conditions of the switch Q1.

2 20 1 2 10.5 ( ) 0.5( )lkg lkg OSS OSS CoL I t C C V (8)

0

2( ) ( )

1O

lkgO

VnI t M

D R

(9)

COSS1 and COSS2 denote the junction capacitor of Q1 and Q2, respectively. Similarly, the ZVS conditions of the auxiliary switch Q2 can be found as

2 23 1 2 10.5 ( ) 0.5( )lkg lkg OSS OSS CoL I t C C V (10)

3

2( ) ( ) O

lkgO

VnI t M

D R . (11)

To assure the ZVS of all switches, (8) should be satisfied. The desired leakage inductor which decides the ZVS range according to the load current ratio can be determined as shown in Fig. 7.

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0 2 4 6 8 10 12 14 16 18 20

Leakage inductor for ZVS (μH)

Llkg=10μH

IO=0.15A (25% load)

Zero-Voltage Switching

Hard Switching

Fig. 7. Minimum load current for the ZVS of all switches according to the leakage inductor.

Ste

p-up

Rat

io

(a)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

5

10

15

20

25

Duty Ratio (D)

Q= 0.109Q= 1.094Q= 4.375Q= 7.656Q=10.937

X10-4

X10-4

X10-4

X10-4

X10-4

VO / VI

VCo2 / VI

VCo1 / VI

M=9.52D=0.61

(b)

Fig. 6. Step-up ratio when n=3.5 (a) Comparison of the step-up ratios when Q=0 and

(b) VCo1/VI, VCo2/VI, and VO/VI according to Q variations.

Fig. 5. Simplified current waveforms.

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C. Output Capacitors CO1 and CO2

By calculating the quantity of electric charge or discharge on CO1 and CO2 with assumptions used in Section III-A, the voltage ripple of each output capacitor can be derived as follows:

1

14Co

O O O S

V n

V DR C f

(12)

22

2

(1 )

4Co

O O O S

V D

V R C f

. (13)

The overall output voltage ripple is smaller than the sum of (12) and (13). From this fact, CO1 and CO2 can be selected while satisfying desired voltage ripple conditions.

D. Link Capacitor Cb

With the same process used in the selection of the output capacitors, the necessary value of the link capacitor can be determined from the following voltage ripple equation.

1Cb

O O b S

V

V R C f

(14)

E. Device Stresses

Since the maximum current of the switch Q1 or Q2 is equal to that of the primary leakage current at t3, i.e., Ilkg(t3), the current stress of the switches can be inferred as (15).

1_ max. 2_ max.

2( ) O

Q QO

VnI I M

D R (15)

Meanwhile, the maximum currents of the output rectifiers DO1 and DO2 are the peak absolute values of the secondary link capacitor current as given by following equations.

1_ max.

2 ODo

O

VI

DR (16)

2_ max.

2

(1 )O

DoO

VI

D R

(17)

Fig. 8 shows the current stresses of the devices normalized by the output current. As can be seen in Fig 8(a), the current stress of the switches relies on the transformer turns-ratio n, the duty ratio D, and the previously defined parameter Q. As n increases, both current stresses of switches increase. The current stress of the switches consists of ILm and nIDo1, where ILm increases and IDo1 decreases as the duty ratio increases. Thus, the current stress of the switches is parabolic in shape. In addition, the current damping effect also appears due to the parameter Q. Fig. 8(b) plots the current stress of the output rectifiers. As the duty ratio increases, the current stress of Do1 decreases and that of Do2 increases. The current stresses of the proposed converter are actually lower than the indicated values in Fig. 8 due to the assumptions in section III-A.

It is clear that the voltage stresses of the switches and output rectifiers are VCo1 and VCo2, respectively, because the switches and output rectifiers can be clamped to VCo1 and VCo2.

IV. EXPERIMENTAL RESULTS

To verify the validity of the proposed circuit and analysis, a 250W prototype converter is implemented with design specifications and circuit parameters as indicated in Table I.

TABLE I DESIGN SPECIFICATIONS AND CIRCUIT PARAMETERS

Input Voltage, VI 42V

Output Voltage, VO 400V

Maximum Output Power, PO_max. 250W

Switching Frequency, fS 70kHz

Transformer

NP : NS 18 : 63 (n=3.5)

Lm 280μH

Llkg 10μH

Link Capacitor, Cb 8.8μF/630V

Output Capacitors, CO1 and CO2 100μF/400V

Power Switches, Q1 and Q2 FQA38N30 (38.4A/300V)

RDS(on)= 85mΩ and COSS=670pF

Rectifiers, DO1 and DO2 FFP04U40DN (4A/400V)

Nor

mal

ized

cur

rent

str

ess

of t

he s

witc

hes

(IQ

_m

ax. /

I O)

(a)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.92

4

6

8

10

12

14

16

18

20

22

Duty Ratio (D)

IDo2_max.=3.2A @ full load

IDo1_max.=2.0A @ full load

(b)

Fig. 8. Normalized current stresses (a) IQ_max./IO according to n and Q variation and (b) IDo1_max./IO and

IDo2_max./IO.

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Fig. 9 indicates the key experimental waveforms of the

prototype converter at the full load, which are well coincided with aforementioned theoretical results. Fig. 9(a) shows the primary leakage current and secondary link capacitor current of the prototype converter. Fig. 9(b) shows current and voltage waveforms of the switches and Fig. 9(c) shows the current and voltage waveforms of the output rectifiers. As can be seen in these figures, the voltages across the switches and output rectifiers are well clamped to VCo1 and VCo2, respectively, and a zero current turned-off of each output rectifier is also achieved. Fig. 10 shows that the switches Q1 and Q2 are turned on after VQ1 and VQ2 drop to 0V, i.e., the ZVS of all switches is achieved. With the values of the leakage inductor and junction capacitors of the switches used

in the experiment, the ZVS of all switches is guaranteed from 25% to 100% load conditions. Fig. 11 shows the measured

(a)

(b)

(c)

(d)

Fig. 10. ZVS waveforms of the switches (a) Q1 at full load, (b) Q1 at half load, (c) Q2 at full load, and (d) Q2 at

half load.

(a)

(b)

(c)

Fig. 9. Key experimental waveforms at the full load (a) primary leakage current and secondary blocking capacitor current, (b)

current and voltage waveforms of the switches, and (c) current and voltage waveforms of the output rectifiers.

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efficiency compared to the FB converter with a VDR according to the output power. The efficiency improvement by using an auxiliary switch to obtain the ZVS turn on is noticeable in the ZVS load range.

V. CONCLUSION

In this paper, the ZVS FB converter with a VDR has been proposed. Its auxiliary switch can not only absorb the voltage surge across the turned-off switch, but achieve the ZVS of all switches as well. The circuit configuration of the proposed converter can extend a step-up ratio without the penalty of the extreme duty ratio. The VDR also alleviates the reverse-recovery losses of the output rectifiers. The experimental results demonstrate that the proposed converter can improve the overall efficiency because of those advantageous features. As a result, the proposed converter is well suited for high frequency step-up applications.

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[7] Ju-Won Baek, Myung-Hyo Ryoo, Tae-Jin Kim, Dong-Wook Yoo, and Jong-Soo Kim. “High Boost Converter Using Voltage Multipler,” in Proceeding of IECON 2005 31th Annual Conference of IEEE, pp. 567-572, Nov, 2005.

[8] Sung-Soo Hong, Sang-Keun Ji, Young-Jin Jung, and Chung-Wook Roh, “Analysis and Design of a High Voltage Flyback Converter with

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[9] Sang-Kyoo Han, Hyun-Ki Yoon, Gun-Woo Moon, Myung-Joong Youn, Yoon-Ho Kim, and Kang-Hee Lee, “A New Active Clamping Zero-Voltage Switching PWM Current-Fed Half-Bridge converter,” IEEE Transactions on Power Electronics, vol. 20, no. 6, pp. 1271-1279, Nov, 2005.J. F. Fuller, E. F. Fuchs, and K. J. Roesler, "Influence of harmonics on power distribution system protection," IEEE Trans. Power Delivery, vol. 3, pp. 549-557, Apr. 1988.

Effi

cien

cy (

%)

Fig. 11. Measured efficiency.

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