Xilinx Spartan Series High Performance, Low Cost FPGAs with on-chip SelectRAM Memory
Dec 26, 2015
Xilinx Spartan Series
High Performance, Low Cost FPGAs with on-chip SelectRAM Memory
Spartan FPGAs ?
Xilinx 4000 Heritage
Total Cost Management
Advanced ProcessTechnology
80 MHz PerformanceOn-chip SelectRAM
Software and cores
Smallest die size
Low packaging costLow test cost
Xilinx Spartan Families
Complete High Volume FPGA Solution SpartanXL: 3.3 Volt with up to 40K System Gates Gates-only solutions are no longer required
Process technology leap UltraDenseTM 0.35m for 3.3 Volt SpartanXL Family
Spartan Series delivers key ASIC requirements with all the FPGA advantages
Powerful software tools Most successful FPGA architecture
No compromises Performance, RAM, Cores, and Low Price
XCS##XL-3PC84C
XCS = Spartan XL = 3.3 Voltno XL = 5 Volt
## = System Gates
Spartan Naming
Spartan part name uses “System Gates” Includes both RAM and Logic
– High end of current published gate range Matches ASIC industry terminology Consistent with future FPGA families
Pe
rfo
rma
nc
e
5200 4000E Spartan/XL (5V/3.V)
E-1
E-2
S-4
S-3
-4
-3
Spartan Speed Grades
Higher speed grade = higher performance
Spartan Meets ASIC Requirements Low Price
Unit Cost
Development Cost
Unit Cost
Development Cost
NRE
LostOpportunity
Cost of Ownership
Per Unit ($)
FPGAASIC
FPGA Cost of Ownership Advantage No test vectors required Limited or no simulation Automatic Place and Route Re-spins in hours not months Faster Time-to-Market No NRE
1x
2x
10x
Total Cost Management
Leading edge process technology Smallest die size
Streamlined feature set Synchronous single/dual-port Select-RAM Popular serial configuration modes JTAG support
Optimized manufacturing test flow for low cost
Focused package offering Highest volume plastic PLCC, VQ, TQ, PQ, BGA packages
UltraDenseTM Process
ChipTransistor gates 0.5/0.35- allows 5V/3.3 V supply
All other features 0.35/0.25- small size- low capacitance- performance- low power
Combines 5V/3.3 V operation with 0.35/0.25 benefits
UltraDenseTM Process
Core
core-limited
I/O padsGate count determines
die size
Spartan Die Size for High I/O packageNearly Equivalent to Gate Arrays
pad-limited
Core
I/O pads
I/O countdetermines
die size
Advanced Process Technology eliminates the “RAM compromise”
Die Sizewithout RAM
1.0
Logicand RAM
I/O pads Die Sizewith RAM
1.0
Logic
Empty, wasted die
area
Technology advances have reduced die size faster than pad technology
Simple Packaging
Focus on popular, low-cost packages Highest-volume ASIC plastic packages
Only six packages: PC84 (05/10) VQ100 (05/10/20/30) TQ144 (10/20/30) PQ208 (20/30/40) PQ240 (30/40) BG256 (30/40)
Optimized PQ208 pinout Adds more I/O
Spartan-XL FPGAsSpartan-XL FPGAs
Marc Baker2-High_Volume-8am
Spartan-XL Global Buffers
8 BUFGLS buffers Similar to XC4000X Available in new SpartanXL library (M1.5)
BUFGP/BUFGS from a Spartan design get converted automatically
No BUFGE/BUFFCLK
Spartan-XL Fast Capture Latch
IOB fast capture latch supported in silicon and software
SpartanXL library includes ILFFX, etc.
Note that there is still only one type of clock buffer
Spartan-XL CLB Latch
CLB flip-flops can be used as latches
LD, etc. components in SpartanXL library
Simplifies use of HDL synthesis
Similar to XC4000X
Spartan-XL Interconnect
Carry only propagates upward Significantly higher speed
– Similar to XC4000X Standard long line can be used to continue at the
bottom of the next column
Datasheet figure shows upward carry only Text describes that it is bidirectional in the 5V Spartan
family
All other device routing is identical to 5V Spartan family
Any 5 V
device
SpartanXLFPGA
Advanced 0.353.3V Core3.3V I/O
5V
3.3V
5V
3.3V
Meets TTLLevels
Spartan-XL Family Voltage Compatibility
Spartan inputs accept 5V signals
Spartan outputs drive standard TTL
100% compatible in 5 volt environment
Optional 3.3V Clamp for PCI
Programmable global clamp to 3.3V for PCI No VTT pins required BITGEN option
– Default is “5V Tolerant I/Os” Similar to XC4000XLA
Spartan-XL Output Drive
Programmable 12 mA or 24 mA output drive Pin-by-pin option Default is 12 mA Similar to XC4000XLA
Spartan-XL Boundary Scan
M2 pin taken out of scan chain BSDL files are different than 5V Spartan
Added IDCODE Instruction Becomes default instruction
Simplified configuration via boundary scan No need to hold INIT Can abort and retry
Similar to XC4000XLA
Spartan-XL Power Down
Former M2 pin has a power-down function Active-low with default pull-up
Disables I/O and OSC, asserts GSR Can be asserted before configuration
After power down is removed, GSR and input disable are removed before outputs are enabled
Cannot lower VCC during power-down
Power down current not yet characterized
Spartan-XL Factory Test Input
Former M1 pin is still a “Don’t Connect”
Enables Express Mode configuration for factory testing
Default pull-up prevents Express mode
SpartanXL (3.3V) ProductionXCS05XL NowXCS10XL NowXCS20XL NowXCS30XL NowXCS40XL Now
Spartan-XL Family Available
Production volumes Now
Spartan-XL software support in 1.5
Spartan Series Footprint Compatibility
5 Volt XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
PC84 PC84
VQ100 VQ100 VQ100 VQ100
TQ144 TQ144 TQ144
PQ208 PQ208 PQ208
PQ240 PQ240
BG256 BG256
Highest volume ASIC plastic packages
Footprint compatible in common packages
Xilinx Spartan Series
5 Volt -> XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt -> XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K
Logic Cells 238 466 950 1368 1862
Max Logic Gates 3,000 5,000 10,000 13,000 20,000
Flip-Flops 360 616 1120 1536 2016
Max RAM bits 3,200 6,272 12,800 18,432 25,088
Max I/O 80 112 160 192 224
Performance 80MHz 80MHz 80MHz 80MHz 80MHz
No Compromises: Performance, RAM, Cores, and Low Price
Xilinx Solution for PC99 in PCs and Peripherals
Processor
Personal ComputerPersonal Computer
PeripheralsSpartanXLUSB interface/
FireWireinterface
Dev
ice
Bay
MemoryXC9500XLSDRAM
Controller
USB,FireWire
interfaces
USBUSBFireWireFireWire
FPGA Challenge (FireWire Example)
FireWire part of PC99 spec is used to demonstrate the benefits of Xilinx FPGAs
IEEE 1394 standard based on Apple’s original definition of FireWire
High speed serial bus 400 Mbits/s required for PC99; increasing to 3.2 Gbits/s
For emerging consumer electronics digital camcorders, DVD players, digital VCRs, HDTV,
set-top boxes, video conferencing
For traditional PC peripherals hard drives, printers, scanners, modems
PhysicalLayer
PhysicalLayer
400 MHz
FireWire
ReceiveReceive50 MHz
Link Layer Interface
FireWire Link Layer Interface Transmit Section
TransmitTransmit8
App
licat
ion
Inte
rfac
e
CRC
CycleStart Core
StateMachine
FIFOsRequest/
Data
PHYInterface
Physical layer operates at full 400 MHz data transfer rate serial-to-parallel conversion drops data rate to 50 MHz
for back-end link layer
Link Layer includes CRC generation and FIFOs
Challenges Facing the Design Engineer
Design complexity
Flexibility for an evolving standard
Design cycle time
HDL entry
Cost control
High performance FIFOs
Design time
Design tools Low power
Potential SolutionsDiscrete logic
not practical approach any longer few available 3.3V/2.5V devices available
Chip sets few available expensive
Custom ASIC long design cycle costly to rework
Programmable Logic
Spartan-XL Provide SolutionReprogrammable: instant updatesFlexibility and design complexity
— feature-rich programmable architecture
High performance: >100 MHz parallel logicDesign tools
— established, easy-to-use development tools— complete software support and extensive cores (IP)
Cost control— advanced process technology for small, low cost die— streamlined manufacturing provides total cost management
Reprogrammability
Fast time to market immediate design changes no cost penalty for mistakes and updates
Immediate production no conversion costs off-the-shelf no inventory risk
100% tested streamlined Xilinx testing reduces costs
High Performance FIFOsUsing SelectRAM Memory
Any logic block can be used as SelectRAM memory
Distributed RAM provides high performance solutions
Features synchronous write,
asynchronous read separate read port
in dual-port mode for FIFOs
All Xilinx FPGAs minimize power by using segmented interconnect
3.3V SpartanXL FPGAs consume less than half the power of 5V Spartan FPGAs
Power Down mode reduces quiescent current to 100 A
SpartanXL Low Power
Spartan Spartan XL PowerDown
Spartan-XL Implementation
Implement FIFO part of FireWire design as an example
50 MHz required
Spartan-XL Benefits
Fast time-to-market user programmable
Low cost
Features for complex logic high speed low power
Easy to use fully supported by Xilinx and third-party software
Solutions for Low-Cost,High-Volume Applications
Low cost programmable logic SpartanXL FPGAs available XC9500XL CPLDs available
High performanceSystem-level featuresEase of evaluation and design
WebFITTER, Foundation 1.5i software available