Xilinx Answer 65494 2.5G Example Design using Tri-Mode Ethernet MAC … · 2.5G Example Design using Tri-Mode Ethernet MAC and 2.5G PCS/PMA or SGMII IP in Vivado Important Note: This
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Xilinx Answer 65494 2.5G Example Design using Tri-Mode Ethernet MAC and 2.5G PCS/PMA
or SGMII IP in Vivado
Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability. It is important to note that Answer Records are Web-based content that are frequently updated as new information becomes available. You are reminded to visit the Xilinx Technical Support Website and review (Xilinx Answer 65494) for the latest version of this Answer.
Introduction
This example is to show how we can have AXI Tri‐Speed Ethernet MAC extended to use 2500BASE_X on 7 series devices. It includes detailed steps for generating the “Tri Mode Ethernet MAC” core and “1G/2.5G Ethernet PCS/PMA or SGMII” core in Vivado 2015.2 and connecting them together in the top level TEMAC example design. It also includes a simulation section on running “BIST” loopback, and a Hardware debug section on using ILA debug cores in a Vivado flow.
Design Architecture
The following is the block of TEMAC (Version 9.0) at 2.5G connected to 2500BASE_X (Version 15.0) core targeting Kintex7 in Vivado 2015.2 (See Figure 1) below.
Figure 1 : Block Diagram of Connected TEMAC and 2500BASE_X IPs
Design Interfaces
We have 3 main interfaces to focus on in this documentation. (See above Figure 1)
Interface 1 – Data Interface between 2500BASE_X core and Transceiver
Interface 2 – MAC and 2500BAXE_X Interface
Interface 3 - MAC AXI4 Stream Interface Here is a list of signals on each interface. We are going to analyze them in both simulation and hardware debug in this documentation.
8. Open the TEMAC example wrapper file and connect the 2500BASE_X core with MAC. Please compare
tri_mode_ethernet_mac_0_example_design.vhd and tri_mode_ethernet_mac_0_example_design_old.vhd for the detailed changes
Here are the steps required to connect the two cores.
Instantiate the gig_eth_pcs_pma _block and connect the GMII interface to the Tri-Mode Ethernet MAC.
Set the Configuration vector to disable AN, disable Isolate, Loopback and PowerDown.
Set the Mac_speed to 10. Top-level ports changes: *********************************************************************** -- clock from internal phy -- gtx_clk : in std_logic; -- clk_enable : in std_logic; -- speedis100 : out std_logic; -- speedis10100 : out std_logic; -- 200MHz clock input from board clk_in_p : in std_logic; clk_in_n : in std_logic; phy_resetn : out std_logic; --added 2500BASE_X serial data and reference clock ports gtrefclk_p : in std_logic; -- Differential +ve of reference clock for MGT: 125MHz, very high quality. gtrefclk_n : in std_logic; --Differential -ve of reference clock for MGT: 125MHz, very high quality. txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD. txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD. rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA. rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA. synchronization_done : out std_logic; linkup : out std_logic; -- GMII Interface ----------------- --gmii_txd : out std_logic_vector (7 downto 0); --gmii_tx_en : out std_logic; --gmii_tx_er : out std_logic; --gmii_rxd : in std_logic_vector (7 downto 0); --gmii_rx_dv : in std_logic; --gmii_rx_er : in std_logic; ***********************************************************************
Instantiate the PCM PMA block: *********************************************************************** COMPONENT gig_ethernet_pcs_pma_0 PORT ( gtrefclk_p : IN STD_LOGIC; gtrefclk_n : IN STD_LOGIC; gtrefclk_out : OUT STD_LOGIC; gtrefclk_bufg_out : OUT STD_LOGIC; txn : OUT STD_LOGIC; txp : OUT STD_LOGIC; rxn : IN STD_LOGIC; rxp : IN STD_LOGIC; independent_clock_bufg : IN STD_LOGIC; userclk_out : OUT STD_LOGIC; userclk2_out : OUT STD_LOGIC; rxuserclk_out : OUT STD_LOGIC;
rxuserclk2_out : OUT STD_LOGIC; resetdone : OUT STD_LOGIC; pma_reset_out : OUT STD_LOGIC; mmcm_locked_out : OUT STD_LOGIC; gmii_txd : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_tx_en : IN STD_LOGIC; gmii_tx_er : IN STD_LOGIC; gmii_rxd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gmii_rx_dv : OUT STD_LOGIC; gmii_rx_er : OUT STD_LOGIC; gmii_isolate : OUT STD_LOGIC; configuration_vector : IN STD_LOGIC_VECTOR(4 DOWNTO 0); status_vector : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); reset : IN STD_LOGIC; signal_detect : IN STD_LOGIC; gt0_qplloutclk_out : OUT STD_LOGIC; gt0_qplloutrefclk_out : OUT STD_LOGIC ); END COMPONENT; ***********************************************************************
Remove the reusable_clock module as gtx_clk is removed from the toplevel. *********************************************************************** -- example_clocks : tri_mode_ethernet_mac_0_example_design_clocks -- port map ( -- gtx_clk => gtx_clk, -- axi_lite_clk => axi_lite_clk, -- -- clock outputs -- gtx_clk_bufg => gtx_clk_bufg, -- s_axi_aclk => s_axi_aclk -- )
Add 200MHz clock input from the board and drive the axi_lite and Independent clocks: *********************************************************************** clkin_buf : IBUFGDS port map (O => clkin200, I => clk_in_p, IB => clk_in_n); clk200_bufg : BUFG port map (O => clk_200_bufg, I => clkin200); axi_lite_clk <= clkin200; mac_speed <= "10"; ***********************************************************************
Before running the simulation, we will need to modify the demo_tb testbench. Please check demo_tb for details. Instantiate the new DUT with the top level changes mode. Change the TB_MODE to BIST instead of DEMO: *********************************************************************** -- constant TB_MODE : string := "DEMO" constant TB_MODE : string := "BIST"; ***********************************************************************
In “BIST” mode, the built in pattern generators and pattern checkers are used with the data loopback in the PHY domain. ***********************************************************************
--Create the transceiver Reference clock (125 MHz) p_gtrefclk : process begin gtrefclk_p <= '0'; gtrefclk_n <= '1'; wait for 4000 ps; gtrefclk_p <= '1'; gtrefclk_n <= '0'; wait for 4000 ps; end process p_gtrefclk; -- drives clk200 at 200 MHz p_clk200 : process begin clk_in_p <= '0'; clk_in_n <= '1'; wait for 80 ns; loop wait for 2.5 ns; clk_in_p <= '1'; clk_in_n <= '0'; wait for 2.5 ns; clk_in_p <= '0'; clk_in_n <= '1'; end loop;
end process p_clk200; ***********************************************************************
Loop the serial transmit data to the receiver. ***********************************************************************
elsif gen_state = SET_DATA and byte_count = X"010" and tready = '1' then to elsif gen_state = SET_DATA and byte_count = X"002" and tready = '1' then ***********************************************************************
In Vivado Simulation settings, set the simulator to Vivado Simulator. And click on “Run Simulation”. (see Figure 15)
Figure 15 : Run Simulation
In XSIM, type “run all” in the Tcl Console. When the simulation comes up, you will see something similar to the following. Here is an overview of the simulation. (See Figure 16 ~ Figure 20)
We will zoom in on the first packet from the pattern generator and track it through the MAC AXI4 Stream TX interface to the MAC and 2500BASE_X interface; and then to the 2500BASE_X and GT interface and in the Rx loopback path. RX Transceiver to 2500BASE_X to MAC RX to MAC RX AXI stream Interface. Here is the first Ethernet packet appearing on the MAC AXI4 Stream TX interface. Here is a snapshot of the zoomed-in AXI4 Stream Interface(see Figure 21 ~ Figure 23)
Figure 21 : Zoomed in MAC AXI4 Stream TX Interface
Figure 22 : 1st Ethernet Packet Start on MAC AXI4 Stream TX Interface
Figure 23 : 1st Ethernet Packet End on MAC AXI4 Steam TX Interface
This is consistent with what we have in the pat_gen.vhd: *********************************************************************** entity tri_mode_ethernet_mac_0_basic_pat_gen is generic ( DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405"; SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
When zooming in the first packet on gmii_txd bus between MAC and 2500BASE_X interface, we have Figure 24 and Figure 25):
Figure 24 :1st Ethernet Packet Start between MAC and 2500BASE_X TX Interface
Figure 25 :1st Ethernet Packet End between MAC and 2500BASE_X TX Interface
The “55” is the preamble. “D5” is the start of the frame data. After “D5”, we can also see the Source Address (5A-01-02-03-04-05) followed by the Destination Address (DA-01-02-03-04-05). On the 2500BASE_X to Transceiver interface, “FB” indicates the start of a packet. “55” is the preamble. “D5” is the start of a frame; and “5A-01-02-03-04-05” is the Source Address, followed by the Destination Address “DA-01-02-03-04-05”. (see Figure 26 )
Figure 26 : 1st Ethernet Packet Start between 2500BASE_X and Transceiver Interface
We can also see “FD” at the end of txdata bus; which indicates the end of a packet. (see Figure 27)
Figure 27 :1st Ethernet Packet End between 2500BASE_X and Transceiver Interface
Now we will take a closer look on the RX interface from Transceiver -> 2500BASE_X -> TEMAC -> AXI4 Stream, as all of the data has been looped back. On the 2500BASE_X and Transceiver interface, “FB” shows the start of a packet. (see Figure 28)
Figure 28 : 1st Ethernet Packet start Looped Back between Transceiver and 2500BASE_X RX Interface
And “FD” is the end of a packet. (see Figure 29 )
Figure 29 : 1st Ethernet Packet End Looped Back between Transceiver and 2500BASE_X RX Interface
On the 2500BASE_X to MAC RX Interface, we can see the following (see Figure 30 ~ Figure 33)
Figure 30 : 1st Ethernet Packet start Looped Back between 2500BASE_X and MAC RX Interface
Figure 31 : 1st Ethernet Packet End Looped Back between 2500BASE_X and MAC RX Interface
Figure 32 : 1st Ethernet Packet start Looped Back on MAC AXI4 Stream RX Interface
Figure 33 : 1st Ethernet Packet End Looped Back on MAC AXI4 Stream RX Interface
If we take a closer look at the statistics vector we can see that when tx_statistics_valid is asserted, the tx_statistics_vector is 0x00000801 (see Figure 34 )
Figure 34 : MAC TX Statistics Vector
We can compare this with the bit definitions of the “Transmitter Statistics Vector” in the Production Guide (see Figure 35 ).
Figure 35 : Bit Definition for the Transmitter Statistics Vector
This means a “SUCCESSFUL FRAME”; with the frame count bit[11:5] = [1000000] = 64 bytes Below is the Receive statistics vector: If we take a closer look at the statistics vector we can see that when rx_statistics_valid is asserted, the rx_statistics_vector is 0x8000801 (see Figure 36)
Figure 36 : MAC TX Statistics Vector
We can compare this with the bit definitions of the “Receiver Statistics Vector” in the Production Guide (See Figure 37)
Then click the ”Run Synthesis” button to run the Synthesis (see Figure 38 )
Figure 38 : Run Synthesis from GUI
.
Setting Up the Debug Cores in Vivado
There are two ways to set up debug signals in ChipScope. One is to manually pull the signals that we would like to debug in Vivado. Alternatively, we can use the “mark_debug” attribute in the source code to mark the signals before running synthesis. This way, the signals that we “marked” to debug will be pulled directly to ChipScope. For this section, we are using the first method to add the signals to the ILA. After synthesis completes, click on “Open Synthesized Design” as shown below (see Figure 39):
Once you finish opening a connection to a hardware target, the “Hardware” window is populated with the hardware server, hardware target, and various hardware devices for the open target. (See Figure 50)
Figure 50 : Hardware View after Opening a Connection to the Hardware Target
After connecting to the hardware target and before you program the FPGA device, you need to associate the bitstream data programming file with the device. Select the hardware device in the Hardware window and make sure the Programming file property in the Properties window is set to the appropriate bitstream data (.bit) file. (See Figure 51 and Figure 52)
The Hardware window now shows the ILA and VIO cores that were detected when scanning the device. (see Figure 54)
Figure 54 : ILA Core is Present in Hardware Session
The ILA core(s) that you add to your design appear in the Hardware window under the target device. If you do not see the ILA core(s) appear, right-click on the device and select Refresh Hardware. This re-scans the FPGA device and refreshes the Hardware window. We should enable pattern generator and Pat check by setting the DIP switch. (See Figure 55) SW11 [3] = 1 and SW11[4]=1 When pattern generator is enabled, you will see the Activity info LED is flashing. Insert SFP+ module in the cage with optical fibre in loopback. Make sure the Jumper J4 is on to enable the SFP.
Use the Trigger Cond control in the ILA Cores tab in the Debug Probes window (or the Trigger Condition property in the ILA Core Properties window) to select between “AND” and “OR” settings. The “AND” setting causes a trigger event when all of the ILA probe comparisons are satisfied. The “OR” setting causes a trigger event when any of the ILA probe comparisons are satisfied. Here is the Debug Probe window. (see Figure 56)
To capture the 1st packet on the axi4 stream TX Interface, we can set up the following: *********************************************************************** tx_axis_mac_tdata = 16h’5A tx_axis_mac_tready = 2b’1 tx_axis_mac_tvalid = 2b’1
***********************************************************************\ Set the Trigger Position in Window to 512. (see Figure 57) Use the Trigger Pos control in the ILA Cores tab in the Debug Probes window (or the Trigger Position property in the ILA Core Properties window) to set the position of the trigger mark in the captured data buffer. You can set the trigger position to any sample number in the captured data buffer. For instance, in the case of a captured data buffer that is 1024 samples deep:
Sample number 0 corresponds to the first (left-most) sample in the captured data buffer.
Sample number 1023 corresponds to the last (right-most) sample in the captured data buffer.
Samples numbers 511 and 512 correspond to the two “centre” samples in the captured data buffer
When zooming in on a packet on the MAC AXI4 Stream TX interface, we can see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05”. Because the packet is too long, here we only capture the beginning of an Ethernet packet and the end of it. (See Figure 61 and Figure 62)
Figure 61 : Zoomed-in Data Packet Start on MAC AXI4 Stream TX Interface
Figure 62 : Zoomed-in Data Packet End on MAC AXI4 Stream TX Interface
On the MAC to 2500BASE_X TX Interface, we can see the following. (See Figure 63)
Figure 63 : MAC and 2500BASE_X TX Interface
When zooming in a packet on the MAC to 2500BASE_X interface, we can also see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05” (see Figure 64) and Zoomed packet end(See Figure 65).
Figure 64 : Zoomed-in Data Packet Start on MAC to 2500BASE_X TX Interface
Figure 65 : Zoomed-in Data Packet End on MAC to 2500BASE_X TX Interface
On the 2500BASE_X to Transceiver TX Interface, we can see the following. (see Figure 66)
Figure 66 : 2500BASE_X to Transceiver TX Interface
When zooming in a packet on the 2500BASE_X to Transceiver interface, we can see “FB” (See Figure 67) to indicate the start of a packet, and “FD” to indicate the end of a packet (See Figure 68). We can also see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05”.
Figure 67 : Zoomed-in Data Packet Start on 2500BASE_X to Transceiver TX Interface
Figure 68 : Zoomed-in Data Packet End on 2500BASE_X to Transceiver TX Interface
As this is an optical cable loopback we will trace the same packet of size 2e on the RX path. On the Transceiver RX to 2500BASE_X Interface, we can see the following. (See Figure 69 )
Figure 69 : Transceiver RX to 2500BASE_X Interface
When zooming in a packet on the 2500BASE_X to Transceiver interface, we can see “FB” (See Figure 70 ) to indicate the start of a packet, and “FD” to indicate the end of a packet(See Figure 71 ). We can also see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05”.
Figure 70 : Zoomed-in Data Packet Start on Transceiver RX to 2500BASE_X Interface
Figure 71 : Zoomed-in Data Packet End on Transceiver RX to 2500BASE_X Interface
On the 2500BASE_X to MAC RX Interface, we can see the following. (See Figure 72)
Figure 72 : 2500BASE_X to MAC RX Interface
When zooming in a packet on the MAC to 2500BASE_X interface, we can also see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05” (See Figure 73) and Zoomed packet end shown in Figure 74.
Figure 73 : Zoomed-in Data Packet Start on 2500BASE_X to MAC RX Interface
Figure 74 : Zoomed-in Data Packet End on 2500BASE_X to MAC RX Interface
Captures at the MAC AXI4 Stream RX interface. (See Figure 75)
Figure 75 : MAC AXI4 Stream RX Interface
When zooming in on a packet on the MAC AXI4 Stream RX interface, we can see “5A-01-02-03-04-05” which is the Source Address; followed by the Destination address “DA-01-02-03-04-05”. Because the packet is too long, here we only capture the beginning of an Ethernet packet and the end of it. (See Figure 76 and Figure 77)
Figure 76 : Zoomed-in Data Packet Start on MAC AXI4 Stream RX Interface
Figure 77 : Zoomed-in Data Packet End on MAC AXI4 Stream RX Interface
Transmit Statistics vector showing 00000801 when tx_statistics_valid asserted indicating SUCCESSFUL FRAME transfer of frame count bit[11:5] = [1000000] = 64 bytes(See Figure 78).
Figure 78 : Transmit statistics vector
Receiver Statistics vector showing 8000801 when tx_statistics_valid asserted indicating Good Frame receiver of frame count bit[11:5] = [1000000] = 64 bytes(See Figure 79).