Wrapper/TAM Optimization1 System-on-Chip (SoC) Testing SoC Wrapper/TAM Design.

Wrapper/TAM Optimization 1

System-on-Chip (SoC) Testing

SoC Wrapper/TAM Design


Scan Chain Architectures*

* J. Aerts and E. J. Marinissen, ITC 1998, pp. 448-457


Paper Summary

Given:# pins SoC available for external scan test# scan patterns of each core# scan FFs in each core

the paper explores the pros and cons of three possible scan-chain architectures for testing the SoC with external source and sink.


Three Basic Scan Architectures

1. Multiplexing: Whole TAM width available to each core, but one at a time.

2. Daisychain: Long chains across multiple cores simultaneously test multiple cores, bypassing those for which the testing is completed.

3. Distribution: Test many cores concurrently but by dividing the TAM lines among them.


Multiplexing Architecture - 1

Full TAM width available to each core exclusivelyDeMux/Mux at inputs and outputs are necessary to connect TAM lines to core pins.Each parallel scan chain requires two signals: scan-in and scan-out. Additionally, at least two global signals are necessary to control scan-enable and mux/demux


Multiplexing Architecture - 2

# scan chains available:

where, K = # pins available for scan testM = number of control pins (=

2)

Total test time, overlapping scan-in and scan-out:

2

K MN

max

where

: number of scan test patterns

: number of scan FFs

: number of scan-testable cores

i ii i

i Ci C

i

i

f fT p p

N N

p

f

C


Daisychain ArchitectureA 2-to-1 mux after each core selects either the core’s internal scan chain or the (buffered) bypassOne test Strategy: Use daisy chain to transport patterns to all cores at once, until a core runs out of patterns and is bypassed. Other test strategies are also possible


Distribution Architecture

Distribute the scan chains over the coresEach core gets assigned its own dedicated scan chainsThe number of scan chains must exceed the number of cores.


Hybrid Architectures

Test-Bus1: Combines multiplexing and distribution.TestRail2: Combines daisychain and distribution.

1. P. Varma and S. Bhatia, ITC98, pp. 294-302.

2. E. J. Marinissen et al., ITC98, pp. 284-293.


Test Wrapper and TAM Co-Optimization for SoC

V. Iyengar, K. Chakrabarty, and E. J. Marinissen, JETTA 18, March 2002, pp. 211-228


Paper Summary

Simultaneous design of wrapper and TAM to optimize the testing times for cores.Algorithm improves on earlier methods of wrapper design in reducing the TAM width required to achieve optimum test time.Another enumerative algorithm for TAM optimization for small number of TAMs.


Example SoCs - 1 (from ISCAS Benchmarks)


Example SoCs – 2(From Philips Research)


Unbalanced vs. Balanced Wrapper Chains

Unbalanced Balanced

Time to apply entire test set to a core:

(1 max{ , } min{ , }

where

: number of test patterns

: longest wrapper scan-in

: longest wrapper scan-out

i o i o

i

o

T s s p s s

p

s

s

The time is minimized for balancedcores.

14 clocks/scan 8 clocks/scan


Wrapper Design Example without and with Co-

optimization

Assume:

Available TAM Width: 4

4 inputs2 outputs4 scan chains: 32, 8, 8, 8long

Clearly, (b) utilizes TAM width better than (a)


Longest Wrapper Scan-in (Scan-out) vs. TAM Width

Problem: Given the following internal scan chain lengths, plot the longest wrapper scan length as a function of TAM width kfor k = 1, 2, 3, 4, 5, 6.

Given scan chain lengths: 8, 8, 8, 8, 8, 10, 10, 10.


Example of a Philips’ p93791 core

This core has:417 functional inputs324 functional outputs72 bidirectional I/Os46 scan chains of lengths:

7x500 bits30x520 bits9x521 bits

Example Pareto-optimal point


Two-Priority Wrapper Optimization Problem: Formal Statement

The paper provides an approximation algorithm based on theBest Fit Decreasing (BFD) heuristic to solve the problem.


Algorithm


Example Core and Result


Optimal Core Assignment to TAMs

Test Bus Model for TAM Design: Cores on each TAM are sequentially tested

Test Bus Model for TAM Design

Multiplexed Cores Cores with Bypass


Problem Definition

Minimize the system test time by assigning cores to TAMs when the TAM widths are known:

An integer linear programming (ILP) based algorithmis presented in the paper to solve small instances of the problem.


Results for SoC from ISCAS Benchmarks -1


Generalizations - 1

The paper goes on to solve the following generalizations of the problems discussed so far:

Optimal Partitioning of TAM Widths:


Generalizations - 2

Wrapper/TAM Co-Optimization


Results for SoC from ISCAS Benchmarks -2

Wrapper/TAM Optimization1 System-on-Chip (SoC) Testing SoC Wrapper/TAM Design.

Documents

scan patterns

scan testm

scan chains available

external scan test

parallel scan chain

cores internal scan

tam width available

available tam width