PART B- FEE(S) TRANSMITTAL form, together .applicable fee(s), to: Mail Mail Stop Iss&E C"' Commissioner for Patents ,. / (CL __ 6--.) P.O. Box 1450 3 'n\US 1.1:' 0 r- 0 Alexandria, Virginia 22313-1450 !:' or EilX (703) 746-4000 should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh appropn ' '/':, 1 furthe spondence including the Patent, advance orders and notification of maintenance fees will be mailed to the current lcorrespondence address indicated elow or directed otherwise in Block 1, by (a) specifying a new correspondence address; and/or (b) indicating a sep:trate "FEE ADDRESS" maintenance ee utiflcations. 24739 7590 OU04/2005 CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004 01/19/2005 KBETEKA2 00000017 10390194 01 FC:2501 02 FC:1504 700.00 OP 300.00 Note: A certificate of mailing can only be used for domestic mailings of Fee(s) TransmittaL This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmissiOn. Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for first class mail in an envel addressed to the Mail Stop ISSUE FEE address above, or being facsim transmitted to the USPTO 703 746-4000, on the date indicated below. na (Signat (D APPLICATION NO. FILING DATE FIRST NAMED INVENTOR CONFIRMATION NO. 10/390,194 03/1412003 Ajay Janami Daga Pl377 TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRATh.'T GENERATION IN IC DESIGN :t APPLN. TYPE SMALL ENTITY ISSUE FEE nonprovisional YES $700 EXAMINER ART UNIT LIN, SUN J 2825 I. Chanl!.e of correspondence address or indication of "Fee Address" (3 7 CFR Lf63). 0 Change of corresJlondence address (or Change of Correspondence Address form PTO/SB/122) attached. PUBLICATION FEE TOTAL FEE(S) DUE $300 CLASS-SUBCLASS 716-001000 2. For printing on the patent front page, list (I) the names of up to 3 registered patent attorneys or agents OR, alternatively, $1000 3209 DATE DUE 04/04/2005 ,, " 0 "Fee indication (or "Fee Address" Indication form • PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer (2) the name of a single fum (having as a member a registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is listed, no name will be printed. · - Number is required. \ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type) PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the doCument has been filed recordation as set forth in 37 CFR 3.1 L Completion of this form is NOT a substitute for filing an assignment. (A) NAME OF ASSIGNEE (B) RESIDENCE: (CITY and STATE OR COUNTRY) F/ shfa-,· I Des;1// D {{.. or other private group entity 0 Govemm Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual 4a The following fee(s) are enclosed: 4b. Payment ofFee(s): Fee 13-A: checiZ in the amount of the fee( s) is enclosed. Fee (No small entity discount permitted) 0 Payment by credit card. Form PT0-2038 is attached. 0 Advance Order- # of Copies ld-rhe' Director is hereby authorized b c Deposit Account Number , e the required fee(s), or credit any ovell'ayment (enclose an extra copy of this form). 5. Change in Entity Status (from status indicated above) 0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27. 0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR L27(g)(2). The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the applicant; a regtstered attorney or agent; or the assignee or other part interest as shown by the records of the ·ted States ent and rademark Office. Typed or printed name ___ _ This collection of information is required by 3 7 CFR 1.311. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to proc an appl\cation. Confidentiality_is governed by 35 U.S.C. 122_and 3? CFR 1.14. TIJ,is collection \s to take minutes to complete, includi_ng gathering,_preparmg, submitting the completed applicatiOn form to the USPTO. Time Will vary depending upon the mdivJdual case. Any co=ents on the amount of time you reg_urre to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Co=erce, 1> Box 1450, Alexandria, Virginia 22313-1'150. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 22313-1450. Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number. PTOL 85 (Rev 12/04) Approved for use through 04/30/2007 OMB 0651 0033 US Patent and Trademark Office; US DEPARTMENT OF COMMER
A software-based system for generating timing constraints for a proposed IC design has a first input as a synthesizable description of the proposed IC, a second input as a clock specification for the proposed IC, and a processing unit accepting the first and second inputs, and determining therefrom as an output, a set of timing constraints to guide implementation of the proposed IC design.
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Transcript
PART B- FEE(S) TRANSMITTAL
form, together .applicable fee(s), to: Mail Mail Stop Iss&E ·~ C"' Commissioner for Patents ,. / (CL __ 6--.) P.O. Box 1450
3 'n\US 1.1:' 0 r- 0 Alexandria, Virginia 22313-1450 !:' or EilX (703) 746-4000
should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh appropn ' '/':, 1 furthe spondence including the Patent, advance orders and notification of maintenance fees will be mailed to the current lcorrespondence address indicated ~~ elow or directed otherwise in Block 1, by (a) specifying a new correspondence address; and/or (b) indicating a sep:trate "FEE ADDRESS" maintenance ee utiflcations.
24739 7590 OU04/2005
CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004
01/19/2005 KBETEKA2 00000017 10390194
01 FC:2501 02 FC:1504 700.00 OP
300.00
Note: A certificate of mailing can only be used for domestic mailings of Fee(s) TransmittaL This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmissiOn.
Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for first class mail in an envel addressed to the Mail Stop ISSUE FEE address above, or being facsim transmitted to the USPTO 703 746-4000, on the date indicated below.
(DepOiiito~s na
(Signat
(D
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR CONFIRMATION NO.
10/390,194 03/1412003 Ajay Janami Daga Pl377
TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRATh.'T GENERATION IN IC DESIGN
:t APPLN. TYPE SMALL ENTITY ISSUE FEE
nonprovisional YES $700
EXAMINER ART UNIT
LIN, SUN J 2825
I. Chanl!.e of correspondence address or indication of "Fee Address" (3 7 CFR Lf63).
0 Change of corresJlondence address (or Change of Correspondence Address form PTO/SB/122) attached.
PUBLICATION FEE TOTAL FEE(S) DUE
$300
CLASS-SUBCLASS
716-001000
2. For printing on the patent front page, list (I) the names of up to 3 registered patent attorneys or agents OR, alternatively,
• PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer
(2) the name of a single fum (having as a member a registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is listed, no name will be printed. · - Number is required.
\ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)
PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the doCument has been filed recordation as set forth in 37 CFR 3.1 L Completion of this form is NOT a substitute for filing an assignment.
(A) NAME OF ASSIGNEE (B) RESIDENCE: (CITY and STATE OR COUNTRY)
F/ shfa-,· I Des;1// AIL.f~maf;~/} Irt~. J_~05v..>e.jD) D {{..
~oration or other private group entity 0 Govemm Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual
4a The following fee(s) are enclosed: 4b. Payment ofFee(s):
~ue Fee 13-A: checiZ in the amount of the fee( s) is enclosed.
~ication Fee (No small entity discount permitted) 0 Payment by credit card. Form PT0-2038 is attached.
0 Advance Order- # of Copies ld-rhe' Director is hereby authorized b c Deposit Account Number ,
e the required fee(s), or credit any ovell'ayment (enclose an extra copy of this form).
5. Change in Entity Status (from status indicated above)
0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27. 0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR L27(g)(2).
The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the applicant; a regtstered attorney or agent; or the assignee or other part interest as shown by the records of the ·ted States ent and rademark Office.
Typed or printed name __Jbo.a.a~rJL..!..!!t>-=...l...!od~_._R~-_"?:2~~0~'1q....5.L_ ___ _ This collection of information is required by 3 7 CFR 1.311. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to proc an appl\cation. Confidentiality_is governed by 35 U.S.C. 122_and 3? CFR 1.14. TIJ,is collection \s e~t\mated to take 1~ minutes to complete, includi_ng gathering,_preparmg, submitting the completed applicatiOn form to the USPTO. Time Will vary depending upon the mdivJdual case. Any co=ents on the amount of time you reg_urre to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Co=erce, 1> Box 1450, Alexandria, Virginia 22313-1'150. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 22313-1450. Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.
PTOL 85 (Rev 12/04) Approved for use through 04/30/2007 OMB 0651 0033 US Patent and Trademark Office; US DEPARTMENT OF COMMER
Certificate of Express Mailing
"Express Mail" Mailing Label Number: EV584080300US Date of Deposit: 01/13/2005 Ref: Case Docket No.: P1377 Application of: Ajay Janami Daga Serial Number: 10/390,194 Filing Date: 03/14/2003 Title of Case: Automated Approach to Constraint Generation in IC Design
I hereby certify that the attached papers are being deposited with the United States Postal Service "Express Mail Post Office to Addressee" service under 37 C.F.R. 1.10 on the date indicated above and addressed to the Commissioner for Patents, Alexandria, VA 22313-1450.
1. Part B of issue fee transmittal. 2. Check for fees in the amount of$1000.00 ($700/Issue fee and $300/Pub. fee).
C., 3. Certificate of express mailing. 4. Postcard listing contents.
Mark A. Boys
UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Offi(e Address: COMMISSIONER FOR PATENTS
P.O. Box 1450 Alexandria. Virginia 22313-1450 www.usptn.go\'
NOTICE OF ALLOWANCE AND FEE(S) DUE
24739 7590 Ol/0412005
CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004
EXAMINER
LIN,SUNJ
ART UNIT PAPER NUMBER
2825
DATE MAILED: 0 1/04/2005
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/390,194 03/14/2003 Ajay Janami Daga Pl377 3209
TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN
APPLN. TYPE SMALL ENTITY ISSUE FEE PUBLICATION FEE TOTAL FEE(S) DUE DATE DUE
nonprovisional YES $700 $300 $1000 04/04/2005
THE APPLICATION IDENTIFIED ABOVE HAS BEEN EXAMINED AND IS ALLOWED FOR ISSUANCE AS A PATEN PROSECUTION .QN IHE MERITS IS CLOSED. TIDS NOTICE OF ALLOWANCE IS NOT A GRANT OF PATENT RIGHT TIDS APPLICATION IS SUBJECT TO WITHDRAWAL FROM ISSUE AT THE INITIATIVE OF THE OFFICE OR UPO PETITION BY THE APPLICANT. SEE 37 CFR 1.313 AND MPEP 1308.
THE ISSUE FEE AND PUBLICATION FEE (IF REQUIRED) MUST BE PAID WITIDN THREE MONTHS FROM TH MAILING DATE OF TIDS NOTICE OR TIDS APPLICATION SHALL BE REGARDED AS ABANDONED. .IH._ STATUTORY PERIOD CANNOT BE EXTENDED. SEE 35 U.S.C. 151. THE ISSUE FEE DUE INDICATED ABOV REFLECTS A CREDIT FOR ANY PREVIOUSLY PAID ISSUE FEE APPLIED IN TIDS APPLICATION. THE PTOL-85B (0 AN EQUIVALENT) MUST BE RETURNED WITIDN TIDS PERIOD EVEN IF NO FEE IS DUE OR THE APPLICATION WIL BE REGARDED AS ABANDONED.
HOW TO REPLY TO TIDS NOTICE:
I. Review the SMALL ENTITY status shown above.
If the SMALL ENTITY is shown as YES, verify your current SMALL ENTITY status:
A. If the status is the same, pay the TOTAL FEE(S) DUE shown above.
B. If the status above is to be removed, check box 5b on Part B -Fee(s) Transmittal and pay the PUBLICATION FEE (if required} and twice the amount of the ISSUE FEE shown above, or
If the SMALL ENTITY is shown as NO:
A. Pay TOTAL FEE(S) DUE shown above, or
B. If applicant claimed SMALL ENTITY status before, or is n claiming SMALL ENTITY status, check box 5a on Part B- Fee Transmittal and pay the PUBLICATION FEE (if required) and I the ISSUE FEE shown above.
II. PART B- FEE(S) TRANSMITTAL should be completed and returned to the United States Patent and Trademark Office (USPTO) w your ISSUE FEE and PUBLICATION FEE (if required). Even if the fee(s) have already been paid, Part B - Fee(s) Transmittal should completed and returned. If you are charging the fee(s) to your deposit account, section "4b" of Part B - Fee(s) Transmittal should completed and an extra copy of the form should be submitted.
III. All communications regarding this application must give the application number. Please direct all communications prior to issuance Mail Stop ISSUE FEE unless advised to the contrary.
IMPORTANT REMINDER: Utility patents issuing on applications filed on or after Dec. 12, 1980 may require payment maintenance fees. It is patentee's responsibility to ensure timely payment of maintenance fees when due.
Page 1 of 3
PTOL 85 (Rev 12/04) Approved for use through 04/30/2007
PART B- FEE(S) TRANSMITTAL
Complete and send this form, together with applicable fee(s), to: Mail Mail Stop ISSUE FEE Commissioner for Patents P.O. Box 1450 Alexandria, Virginia 22313-1450
or fix (703) 746-4000 INSTRUCTIONS: This form should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh !IJlpropriate. All further corresponden~ including tb,e P!Uent. advance orders ll!ld. notification of maintenance fees will be maile_d (? tb,e current co~ondence addre~.s mdicated unless corrected below or directed otherwiSe m Block I, by (a) spec1fying a new correspondence address; and/or (b) mdicatmg a separate "FEE ADDRESS maintenance fee notifications.
l
CURRENT COAAESPONDENCE 1\DDRESS (Note: Use Block I for any ehange of ad~ .. )
24739 7590 OU0412005
CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004
APPLICATION NO. I FILING DATE I
Note: A certificate of mailing can only be used for domestic mailings of Fee(s) Transmittal. This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmission.
Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for firSt clilss mail in an envei addressed to the Mail S~ ISSUE FEn address above, or be~ facsim transmitted to the USPTO 03) 746-4000, on the date indicated OW.
(Dep06ito~• na
(Signal
CD
FIRST NAMED INVENTOR I ATTORNEY DOCKET NO. I CONFIRMATION NO.
10/390,194 03114/2003 Ajay Janami Daga PJ377 3209
TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN
APPLN.TYPE SMALL ENTITY ISSUE FEE
nonprovisional YES $700
EXAMINER ART UNIT
LIN, SUN 1 2825
I. Change of correspondence address or indication of "Fee Address" (37 CFR I.363).
PUBLICATION FEE TOTAL FEE(S) DUE
$300
CLASS-SUBCLASS
7I6-00IOOO
2. For printing on the patent front page, list
(I) the names of up to 3 registered patent attorneys or agents OR, alternatively,
$1000
DATE DUE
04/04/2005
0 Change of correspondence address (or Change of Correspondence Address form PTO/SB/I22) attached.
0 "Fee Address" indication (or "Fee Address" Indication form PTO/SB/4 7; Rev 03-02 or more recent) attached. Use of a Customer Number is required.
(2) the name of a single firm (having as a member a 2. ____________ _ registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is 3 listeQ, no name will be printed. -------------
3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)
PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the document has been filed recordation as set forth in 37 CFR 3.11. Completion of this form is NOT a substitute for filing an assignment.
(A) NAME OF ASSIGNEE (B) RESIDENCE: (CITY and STATE OR COUNTRY)
Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual 0 Corporation or other private group entity 0 Governm
4a The following fee(s) are enclosed: 4b. Payment ofFee(s):
0 Issue Fee 0 A check in the amount of the fee(s) is enclosed.
0 Publication Fee (No small entity discount permitted) 0 Payment by credit card. Form PT0-2038 is attached.
0 Advance Order- #of Copies 0 The Director is hereby authorized by charge the required fee(s), or credit any ovel'J?ayment Deposit Account Number (enclose an extra copy of this form).
5. Change in Entity Status (from status indicated above)
0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27. 0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR 1.27(g)(2).
The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the apphcant; a regrstered attorney or agent; or the assignee or other part interest as shown by the records of the United States Patent and Trademark Office.
Typed or printed name--------------------- Registration No.--------------
This collection of information is required by 3 7 CFR I.3II. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to l'roc an application. Confidentiality is governed by 35 U.S.C. I22 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering, preparmg, submrtting the completed applicatiOn form to the USPTO. Time will vary depending upon the individual case. Any co=ents on the amount of time you require to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department ofCo=erce, 1> Box I450, Alexandria, Virginia 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 223I3-1450.
Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.
PTOL 85 (Rev I2/04) Approved for use through 04/30/2007 OMB 065I 0033 US Patent and Trademark Office; US DEPARTMENT OF COMMER
UNITED STATES PATENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
10/390,194 03/14noo3
24739 7590 01/04/2005
CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004
FIRST NAMED INVENTOR
A jay Janami Daga
UNITED STATES DEPARTME.NT OF COMMERCE United States Patent and Trademark. Office Add=<: COMMISSIONER FOR PATENTS
Determination of Patent Term Adjustment under 35 U.S.C. 154 (b) (application filed on or after May 29, 2000)
The Patent Term Adjustment to date is 102 day(s). If the issue fee is paid on the date that is three months after t mailing date of this notice and the patent issues on the Tuesday before the date that is 28 weeks (six and a h months) after the mailing date of this notice, the Patent Term Adjustment will be 102 day(s).
If a Continued Prosecution Application (CPA) was filed in the above-identified application, the filing date th determines Patent Term Adjustment is the filing date ofthe most recent CPA.
Applicant will be able to obtain more detailed information by accessing the Patent Application Information Retriev (PAIR) WEB site (http://pair.uspto.gov).
Any questions regarding the Patent Term Extension or Adjustment determination should be directed to the Office Patent Legal Administration at (571) 272-7702. Questions relating to issue and publication fee payments should directed to the Customer Service Center ofthe Office ?! P~t~nt P_ubli_c~ti~n_ at (703) 30~-~283. _ _ __
Page 3 of 3
PTOL 85 (Rev 12/04) Approved for use through 04/30/2007
Application No. Applicant(s)
Notice of Allowability 10/390,194 DAGA, AJAY JANAMI Examiner Art Unit
Sun J Un 2825
-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address-All daims being allowable, PROSECUTION ON THE MERITS IS (OR REMAINS) CLOSED in this application. If not included herewith (or previously mailed), a Notice of Allowance (PTOL-85) or other appropriate communication will be mailed in due course. THIS NOTICE OF ALLOWABILITY IS NOT A GRANT OF PATENT RIGHTS. This application is subject to withdrawal from issue at the initiative of the Office or upon petition by the applicant. See 37 CFR 1.313 and MPEP 1308.
1. [gl This communication is responsive to Amendment & Remarks filed on 1111712004.
2. [gl The ·allowed claim(s) is/are 1.3-13 and 15-24. renumbered (37CFR 1.126!.
3. [gJ The drawings filed on 03/1412003 are accepted by the Examiner.
4. D Acknowledgment is made of a claim for foreign priority under 35 U.S. C.§ 119(a)-(d) or (f).
a) D All b) D Some* c) D None of the:
1. D Certified copies of the priority documents have been received.
2. D Certified copies of the priority documents have been received in Application No. __ .
3. D Copies of the certified copies of the priority documents have been received in this national stage application from the
International Bureau (PCT Rule 17.2(a)).
*Certified copies not received: __ .
Applicant has THREE MONTHS FROM THE "MAILING DATE" of this communication to file a reply complying with the requirements noted below. Failure to timely comply will result in ABANDONMENT of this application. THIS THREE-MONTH PERIOD IS NOT EXTENDABLE.
5. 0 A SUBSTITUTE OATH OR DECLARATION must be submitted. Note the attached EXAMINER'S AMENDMENT or NOTICE OF INFORMAL PATENT APPLICATION (PT0-152) which gives reason(s) why the oath or declaration is deficient.
6. D CORRECTED DRAWINGS ( as "replacement sheets") must be submitted.
(a) D including changes required by the Notice of Draftsperson's Patent Drawing Review ( PT0-948) attached
1) D hereto or 2) D to Paper No./Mail Date __ .
(b) D including changes required by the attached Examiner's Amendment I Comment or in the Office action of Paper No./Mail Date __ .
Identifying indicia such as the application number (see 37 CFR 1.84(c)) should be written on the drawings in the front (not the back) of -~AcJ!.sJ!e.!!:_~~lac..!!!!._ent sheet{&) should be labeled as such in the header according to 37 CFR 1.121(d). · - ----------~--- --...- - ---- - -----~ ........ ----------- ---- -- ---~--
7. 0 DEPOSIT OF and/or INFORMATION about the deposit of BIOLOGICAL MATERIAL must be submitted. Note the attached Examiner's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.
Attachment( s) 1. D Notice of References Cited (PT0-892)
2. D Notice of Draftperson's Patent Drawing Review (PT0-948)
3. D Information Disclosure Statements (PT0-1449 or PTO/SB/08), Paper No./Mail Date __
4. D Examiner's Comment Regarding Requirement for Deposit
of Biological Material
5. D Notice of Informal Patent Application (PT0-152)
6. D Interview Summary (PT0-413), Paper No./Mail Date __ .
7. D Examiner's AmendmenVComment
8. D Examiner's Statement of Reasons for Allowance
9. D Other
U.S. Patent ard Trademar1< Office
PTOL-37 (Rev. 1-04) Notice of Allowability Part of Paper No./Mail Date 1221200
iii r::: u:
1
Application No.
Issue Classification 10/390,194
II II II I Ill II~ Ill Examiner
Sun J Lin
in the same order as b~
~ 1
1
1
11 Ti II·] Hlllll iii 01 I :::, c (§ 1::::::. u:
Applicant(s)
DAGA, AJAY JANAMI Art Unit
2825
I DCPA ~~T\ .!: :§1 u. ....
0
D R1.47
iii c u:
a 9 1// 1 39 69 : 99 129 ·• · ··· 159 r : 189
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~! ~~ ~==:=:= ......... 1-----f-~i-'--l: :--+--=--=-~;E.=......t==•.==.... ~E ~E1 '~==:~~~~ 1s 11 47 n 1 < 101 137 167 _1 rr 16 18 48 78 I H 1 o8 1381 .. 168 ~ 17 19 49 79 I H 109 ,,,. · 139 IT 169 199
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U.S. Patent and Trademark Office Part of Paper No. 12212004
th"n 160 ~alma or 10 aotlons If more n~ · · staple add!tlonal·shoot n.ere
(LEFT INSIDE~
BEST AVAILABLE COPY
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£PDF] Focus: The Automatic Generation of Golden Timing Constraints Fih:.: Format: PDF/Adobe Acrobat- View as HTML ... ·collectively referred to as exceptions to single-cycle clocking .•.• Figure 4: Golden timing constraint file for example design •.. W\1\'W.saros.co.uk/focus/whitepaper.pdf- $.i.m\!~LP~9~§.
[PDFJ Designing the Low-Power M ·CORE Architecture File Fonnat PDF/Adobe Acrobat- View as HTML ... Architecture (ISA), the custom datapath design, and the clocking. methodology . ... single cycle find-first-one instruction (FF1), a hardware loop ..• www.ece.umd.edu/courses/enee759m.S2000i papers/scott1998-lowpower.pdf- .$l.mH~L!~~.9~.§.
[PDFJ XAPP640 "Timing Constraints for Virtex-11 Pro Designs" v1.1 (01/03) File Format: PDF/Adobe Acrobat- View as HTML ... processor is in single-cycle mode. Multi-cycle mode occurs when the ..• timing constraint used is the PERIOD constraint, the clocks are related back to .•. direct.xilinx.com/bvdocs/appnotes/xapp640.pdf- Si;ni!ar pages
TechXclusives- Timing Closure- 6.1 i ... Exception: Spartan-3. Can reduce multiplexer delays Omprove •.. synchronous elements driven by a single clock ... Based on these two facts, multi-cycle constraints can ... direct.xilinx.com/xlnx/xweb/xil_tx_display. jsp?sTechX_ID=r.v_tim_closure_61i&iLanguageiD=1 - 69k-
G.?..GI:!~~- - .$.!mi.!?..L!?.?..9.~~
FPGA FAQ comp.arch.fpga archives- messages from 73725 ... a slow clock and it would be best if I could put a timing constraint on the fast signals .... If you have a DCM available just for clocking in the data, ... W'<.vw.fpga-faq.corn/archives/73725.htrn! - 61 k- Cached - Sirnilar oaaes
FPGA FAQ comp.arch.fpga archives- messages from 52075 ... Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in I> 2.000000 ... sounds like the result of over-clocking a > systolic processor! .•• www.fpga-faq.com/archives/52075.html - 75k - G~.!.<.tl~Q - .S.i.r.nU5;1LP.~.9.~-~ __ ~- __________ _
Synopsys Design Compiler - Whitepaper ... By default, Design Compiler calculates single cycle timing for .•. allows designers to define multi-cycle paths, false .•. point-to-point timing exception commands are ... WW'N.synopsys.corn/products/!ogic/dc_wp97.htrnl- 39k- Cached- Simi!ar pages
[PDFJ Designing the Low-Power M • CORE Architecture Filt:.: Format: PDF/Adobe Acrobat -View as HTML ... shift (ASR), and rotate operations (ROTL), a single cycle find-first ••. to select either register file for exception pro- cessing with no cycle penalty [20 ..• davinci .sn u .a c. kr/courses/emb/2000/doc/34 .pdf - §i.mH~r..p~g~_;?
[PDFJ Microcontrollers File Fonnat PDF/Adobe Acrobat- View as HTML ... normal CPU operation provided that it can be completed in a single cycle .••• The BDM serial interface uses a clocking scheme in which the external host ••• vV\.V\"'.freescale.cornlfiles/microcontrollers/ doc/ref_rnanuaVS12BDMV4.pdf- .$.!m.i.!~.L~~-9-~§
[PDFJ Microcontrollers
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1 Fast and practical false-path elimination method for large SoC designs Chul Rim; Soo-Hyun Kim; Joo-Hyun Park; Myung-Soo lang; Jin-Yong Lee; KyuMyong Choi; Jeong-Taek Kong; SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , 17-20 Sept. 2003 Pages: 397 - 400
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2 A protocol for timed atomic commitment Davidson, 5.; Lee, I.; Wolfe, V.; Distributed Computing Systems, 1989., 9th International Conference on , 5-9 June 1989
[Abstract] [PDF Full-Text (664 KB)] IEEE CNF
3 A 4-GHz effective sample rate integrated test core for analog and mixedsignal circuits Hafed, M.M.; Abaskharoun, N.; Roberts, G. W.; Solid-State Circuits, IEEE Journal of, Volume: 37 , Issue: 4 , April 2002 Pages:499- 514
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Sir. Transmitted herewith is and an amendment in the abovc-idattifiro application, under 37 C.F.R. 1.312.
Ill No additional fee is required. 121 Applicant claims Small entity status under 37 CFR 1.27. 0 The fee has been calculated as sbown below.
•••• CLAIMS AS AMENDED **** ~
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Total 22 Minus .... 24 0
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Jndep 2 Minus "'"'"' 3 0 $ 44 $ 88 s o.oo Claims
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~ Please charge any additional fees or credit overpayment to Deposit Account 50-0534 . A duplicate of this sheet is enclosed.
~ Respectfully Submitted, Donald R. Boys R.,g, No. 35074
Donald R.. :Boys Central Coast Patent Agency, Inc. P.O. Box 187 Aromas, CA 95004 (831) 726-1457
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For An Automated Approach to Constraint Generation in IC Design
Sir; Transmitted herewith i$ and an amendment in the above-identified appHcation, undet 37 C.F.R. l.3ll.
0 No additional fee is required. G2l Applicant claims SmaU entity status under 37 CFR l.:l7. 0 The fee has been calculated as shown below.
**** CLAJMS AS AMENDED •••• ~
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£d/~f/Lr-Respectfully Submitted, DonAld R. Boys Reg. No. 35074
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COIP>Y P.O. Box 187 Aromas, CA 95004 (831) 726-1457
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11/17/~aa4 15:29 8317263475 CCPA
IN mE UNITED STATES PATENT AND TRADEMARK OFFICE
lnRe: Case: Serial No.: Filed:
Art Unit 2825 ExiUlliner: Lin, Sun J.
Ajay Janami Daga P1377 10/390,194 03/14/2003
RECE~ CENTRAL F. ~ 04 CENTER
NOV 1 7 2004
Subject: An Automated Approach to Constraint Generation in IC Design
To: The Commissioner of Patents and Trademarks Alexandria, VA 22313-1450
Dear Sir;
Response A
PAGE 4/W RCVD AT 11/1712004 5:25:48 PM ~astern Standard TlmeJ' SVR:USPTO.fFXRF·112' DNIS:8729306 a CSID:8317263475 a DURATION (mm-ss):02-38
:(
. .. · '·
11/17/2884 15:29 8317263475 CCPA
0 ••• •
-2-
Claims 1-24 are presented below for examination. Claims 1, 3, 5, 12, 13, 15, 17
and 24 are ~ended, and claims 2 and I 4 are canceled in this response.
1. (currently amended) A software-based system for generating timing constraints
for a proposed IC desi!W, comprising:
a first input as a synthesizable description of.the proposed IC dWgn;
a second input as a clock specification for the proposed IC design; and
a processing unit accepting the first and second inputs, apd determining
therefrom as an output a set of timing constraints to guide implementation ·of the
proposed IC design;,
wherein the processing unit. in detennining the timing constraints.
determines exceptions to single-cycle clocking for the proposed IC design.
2. (canceled)
3. (currently amended) The system of claim ~ .Lwherein the exceptions include
false paths and multi-cycle paths.
· 4. t original) The system of cla1m 1 wherein the output is provided in Synopsys
Design Constraint (SOC) format useable by one or more of virtual prototyping,
logic synthesis, place & route, and static timing tools in design implementation .
5. (currently amended) The system of claim 1 wherein the oroposed IC design is
one of an application-specific integrated circuit (A~IC) or a field-programmable
gate array (FPGA).
6. (original) The system of claim 1 wherein the first and second inputs and output
any time extensions needed beyond any extension specifically requested witJl this
amendment, such extension of time is hereby requested. If there are any fees due
beyond any fees paid with this amendment, authorization is given to deduct such fees
from deposit account 50-0534.
Donald R. Boys Central Coast Patent Agency P.O. Box 187 Aromas, CA 95004 (831) 72()..1457
by
Respectfully Submitted, Ajay Janami Daga
d.-.«6:!,~ • Donald R Boys
Reg. No. 35,074
PAGE 18
PAGE 10110 * RCVD AT 1111712004 5:25:48 PM ~astern Standard TIRle) ~ SVR:USPTO·EFXRF·112 3 DNIS:8729306- CSID:8317263475 *DURATION (rnm-ss):02·38
UNITED STATES PATENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
10/390,194 03/14/2003
24739 7590 08/2412004
CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004
FIRST NAMED INVENTOR
Ajay Janami Daga
UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS
P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov
I ATTORNEY DOCKET NO. I CONFIRMATION NO.
P1377 3209
EXAMINER
LIN, SUN J
ART UNIT PAPER NUMBER
2825
DATE MAILED: 08/24/2004
Please find below and/or attached an Office communication concerning this application or proceeding.
PT0-90C (Rev. 10/03)
Application No.
10/390,194
Office Action Summary Examiner
Sun J Lin
Applicant(s)
DAGA, AJAY JANAMI
Art Unit
2825
-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address --Period for Reply
A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE ;a MONTH(S) FROM THE MAILING DATE OF THIS COMMUNICATION. - Extensions oftime may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed
after SIX (6) MONTHS from the mailing date of this communication. - If the period for reply specified above is less than thirty (30) days, a reply within the statutory minimum of thirty (30) days will be considered timely. - If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication. - Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term adjustment. See 37 CFR 1.704(b).
Status
1)1:8l Responsive to communication(s) filed on 14 March 2003.
2a)0 This action is FINAL. 2b)C8] This action is non-final.
3)0 Since this application is in condition for allowance except for fonnal matters, prosecution as to the merits is
closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
Disposition of Claims
4)1:8l Claim(s) 1-24 is/are pending in the application.
4a) Of the above claim(s) __ is/are withdrawn from consideration.
5)0 Claim(s) __ is/are allowed.
6)C8] Claim(s) 1,4-9.12.13.16-21 and 24 is/are rejected.
7)1:8l Claim(s) 2.3.10. 11.14.15.22 and 23 is/are objected to.
8)0 Claim(s) __ are subject to restriction and/or election requirement.
Application Papers
9)0 The specification is objected to by the Examiner.
1 O)C8] The drawing(s) filed on 14 March 2003 is/are: a)C8] accepted or b)O objected to by the Examiner.
Applicant m~y not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
11 )0 The oath or declaration is objected to by the Examiner. Note the attached Office Action or fonn PT0-152.
Priority under 35 U.S.C. § 119
12)0 Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
a)O All b)O Some* c)O None of:
1.0 Certified copies of the priority documents have been received.
2.0 Certified copies of the priority documents have been received in Application No. __ .
3.0 Copies of the certified copies of the priority documents have been received in this National Stage
application from the International Bureau (PCT Rule 17.2(a)).
* See the attached detailed Office action for a list of the certified copies not received.
Attachment(s)
1) C8J Notice of References Cited (PT0-892)
2) 0 Notice of Draftsperson's Patent Drawing Review (PT0-948)
3) 1:8Jinformation Disclosure Statement(s) (PT0-1449 or PTO/SB/08) Paper No(s)/Mail Date 03/14/03.
U.S. Patent and Trademarl< Off1ce
4) 0 Interview Summary (PT0-413) Paper No(s)/Mail Date. __ .
PTOL-326 (Rev. 1-04) Office Action Summary Part of Paper No./Mall Date 08182004
Application/Control Number: 1 0/390,194
Art Unit: 2825
DETAILED ACTION
Page 2
1. This office action is in response to application 10/390,194 filed on 03/14/2003.
Claims 1 - 24 remain pending in the application.
Claim Objections
2. Claims listed below are objected to because of the following informalities:
Claim 1, line 3, after "IC" insert -design-.
Claim 1, line 4, after "IC" insert -design-.
Claim 5, line 1, change "IC" to -proposed IC design-.
Claim 12, line 3, in front of "design" insert -proposed I C-.
Claim 13, line 4, after "IC" insert -design-.
Claim 14, line 6, after "IC" insert -design-.
Claim 17, line 1, change "IC" to -proposed IC design-.
Claim 24, line 3, in front of "design" insert -proposed I C-.
Appropriate correction is required.
Claim Rejections - 35 USC§ 102(b)
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. §102(b) that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless-
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
4. Claims 1, 5-9, 12, 13, 17-21 and 24 are rejected under 35 U.S.C. §1 02(b) as
being unpatentable over U.S. Patent No. 5,896,299 to Ginetti eta/.
5. As to Claim 1, Ginetti eta/. teach the following subject matter:
• Method and svstem containing a computer implemented process (i.e.,
software-based svstem) for fixing timing constraints for a hierarchical design
of electronic circuit- [title; abstract; col. 1, line 66- col. 2, line 5]; Notice that
appropriate timing constraints are generated through fixing existing timing
Application/Control Number: 10/390,194
Art Unit: 2825
Page 3
constraints- [abstract]; A hierarchv design of circuit- [Fig. 14]; Notice that in
a hierarchv design, an electronic circuit under study may be a function block
in one hierarchical/eve/ (e.g., Fig. 3A) or a group of functional blocks
arranged in manvhierarchica//eve/s (e.g., Fig. 14); A proposed IC design is
any hierarchv design (one hierarchical/eve/ or many hierarchical levels) of
electronic circuit under study.
• synthesizing a RTL-HDL tvpe description of the circuit (i.e., proposed /C) -
[abstract]; Notice that RTL-HDL is a synthesizable description (called first
input);
• real clock timing (latency and skew). worst case conditions. best case
conditions- [abstract]; Notice that the real clock timing (latency and skew).
worst case conditions. best case conditions are constituents of a clock
specification (called second input) of the proposed IC design under study;
• Computer implemented process accepting the synthesizable description (first
input) and the clock specification (second input), and determining therefrom
as an output a set of timing constraints (upper-bond timing constraints, lower
bound timing constraints)- [abstract]; Notice that the set of timing constraints
could be utilized in guiding timing implementation of the hierarchical circuit
design {proposed IC design)- [col. 2, line 31 - 47; col. 5, line 1 - 60].
For reference purposes, the explanations given above in response to Claim 1 are
called [Response A] hereinafter.
6. As to claim 13, reasons are included in [Response A] given above.
7. As to Claims 5 and 17, Ginetti eta/. disclose one of his related publication on
"Using the ASIC synthesizer in DSP Designs"- [Other Publications]. Notice that the
ASIC is a synthesizable IC.
8. As to Claims 6 and 18, the explanations included in [Response A] could be applied
to any hierarchy circuit design, including a functional block (e.g., flip-flops) in an IC
design. Ginetti eta/. show and teach timing constraints (CK1, CK2) of a circuit
containing flip-flops 11. 13, which is a functional block- [Fig. 3A].
Application/Control Number: 10/390,194
Art Unit: 2825
Page4
9. As to Claims 7 and 19, in addition to reasons included in [Response A] given
above, Ginetti et a/. show and teach a circuit design 1 08 with two hierarchical parts
(subcells 110. 112), there are timing constraints for paths (data path, clock path)
between subce/1 110 and subce/1 112- [Fig. 14; col. 6, line 66- col. 7, line 27]. Notice
that subce/1 110 and subce/1 112 are functional blocks.
For reference purposes, the explanations given above in response to Claims 7
and 19 are called [Response B] hereinafter.
10. As to Claims 8 and 20, in addition to reasons included in [Response A] and
[Response B] given above, Ginetti eta/. teach subject matter on timing constrains in
hierarchical designs of electronic circuits- [abstract; col. 1, line 5-9]. Notice that
timing requirements is clock timing Oatencv and skew) specifications of hierarchical
parts- [abstract]. Block timing budgets are timing constraints of hierarchical parts. In a
hierarchical design, overall IC is partitioned in hierarchical manners.
11. As to Claims 9 and 21, as explained in [Response A] given above, Ginetti eta/.
teach that the svnthesizable description is provided as a HDL tvpe. Notice that a VHDL
format description is a HDL type description.
12. As to Claims 12 and 24, Ginetti eta/. teach that the clock description includes
clock period, (clock) waveform, skew and latency associated with each clock- [col. 5,
line 4- 6]. Notice that clock description is an input, therefore clock period, (clock)
waveform, skew and latencv are defined and inputted by users. Waveform, skew and
latencv of a clock define its phase shift relative to a reference clock. A clock is assigned
to each clock net. In designing a hierarchical electronic circuit, a user may need to
assign many clocks to different clock nets. Notice also that many users may have
different ideas in defining clocks, their periods, their phase shifts relative to a reference
clock to the clock nets in the proposed IC design.
Application/Control Number: 10/390,194
Art Unit: 2825
Claim Rejections - 35 USC § 103
Page 5
13. The following is a quotation of 35 U.S.C. 1 03(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 1 03(a) are summarized as follows:
(1 ). Determining the scope and contents of the prior art. (2). Ascertaining the differences between the prior art and the claims at issue. (3). Resolving the level of ordinary skill in the pertinent art. (4 ). Considering objective evidence present in the application indicating obviousness
or nonobviousness.
14. Claims 4 and 16 are rejected under 35 U.S.C. 1 03(a) as being unpatentable over
U.S. Patent No. 5,896,299 to Ginetti eta/. in view of U.S. Patent No. 6,658,628 81 to
Landv eta/.
15 As to Claim 4, Ginetti eta/. teach all subject matter recited in Claim 1, they do not
teach a method of providing the output in Svnopsvs Design Constraint (SOC) format
usable by one or more of virtual prototyping, logic synthesis, place & route and static
timing tools in design implementation. But Landv eta/. teach generating appropriate
time budget (or timing constraints) in Synopsvs Design Constraint (SOC) format file,
which is generated in a format or syntax corresponding to a .sdc suffix, for a particular
design- [col. 4, line 34- 38]. Landy eta/. also show and teach the following subject
matter:
• Timing file generator for hardmacro (e.g., AS/C)- [Fig. 1];
• Providing hardmac technology file and/or timing generation tool that may provide
transportable language or syntax that can be read and/or processed by other
synthesis/layout/analysis tools- [col. 1, line 38- 54]; Notice that synthesis tool
includes logic synthesis tool, layout tool includes place & rout tool, analysis tool
includes static timing tool.
Application/Control Number: 10/390,194
Art Unit: 2825
Page 6
Notice that the Synopsys Design Constraint (SOC) format file is a transportable
language or syntax. The timing constraints are generated in Synopsys Design
Constraint (SOC) format file in order to provide a capability of being read and/or
processed by logic synthesis, place & rout tool and static timing tools provided by other
vendors. Data generated in a transportable language or syntax is very helpful for a
design company utilizing a variety of logic synthesis, place & rout tool and/or static
timing tools, which are provided by different manufacturers.
Therefore, it would have been obvious at the time the invention was made to a
person having ordinary skill in the art to have applied the teachings of Landy eta/. in
generating timing constraints in Synopsys Design Constraint (SOC) format file in order
to provide a transportable capability of being read and/or processed by a variety of logic
synthesis, place & rout tool and static timing tools, which are provided by different
vendors.
For reference purposes, the explanations given above in response to Claim 4 are
called [Response C) hereinafter.
16. As to Claim 16, reasons are included in [Response C) given above.
Allowable Subject Matter
17. Claims 2, 3, 10, 11, 14, 15, 22 and 23 are objected to as being dependent upon a
rejected base claim, but they would be allowable if rewritten in independent form
including all of the limitations of the base claim and any intervening claims.
Those claims are allowed is because that the prior art does not teach or fairly
suggest the following subject matter:
• The processing unit, in determining the timing constraints, determines
exceptions to single-cycle clocking for the proposed IC design in combination
with other limitations as recited in Claim 2 and Claim 14, respectively;
• The first input is derived from a .lib model and converted into one of Veri log of
VHDL format in combination with other limitations as recited in Claim 10 and
Claim 22, respectively;
Application/Control Number: 1 0/390,194
Art Unit: 2825
Conclusion
Page 7
18. Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Sun J. Lin whose telephone number is (571) 272-1899.
The examiner can normally be reached on Monday-Friday (9:00AM-6:00PM).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Matthew Smith can be reached on (571) 272-1907. The fax phone numbers
for the organization where this application or proceeding is assigned are (703) 872-9318
for regular communications and (703) 872-9319 for After Final communications.
Any inquiry of a general nature or relating to the status of this application or
proceeding should be directed to the receptionist whose telephone number is (703) 308-
1782.
Sun James Lin Art Unit 2825 August23,2004
'
..
+
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INFORMATION DISCLOSURE Application Number NA Flllna Data 03/1412003
STATEMENT BY APPLICANT First Named Inventor Ajay Janami Daga Art Unit "i'+lr- "Z 11 'Z-5"'
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Application/Control No. Applicant(sYPatent Under Reexamination
10/390,194 DAGA, AJAY JANAMI Notice of References Cited
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B US-6,658,628 81 12-2003 Landy et al. 716/1
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An Automated Approach to Constraint Generation in IC Design
by inventor Ajay .Janami Daga
Field of the Invention
The present invention is in the technical area of integrated circuit (IC)
design, and pertains more specifically to Electronic Design Automation (EDA)
tools providing methods and apparatus for generating timing constraints in a
design project.
Cross Reference To Related Documents
The present non-provisional patent application claims priority to
provisional application serial number 60/365,749, filed on 03/18/2002. The
entire disclosure of provisional application 60/365,749 is incorporated herein
by reference.
Background of the Invention
The term integrated circuit (IC) is a very general term covering a very
broad range of electronic devices based on solid-state electronics, such as
microprocessors. It is now notoriously well-known that a vast array of
consumer products, especially those products in the area of
telecommunications and computerized devices (including personal computers),
-2-
are based on ICs, such as central processing units (CPUs), microprocessors,
and, of course, digital memory devices of many sorts.
In the art of IC design and manufacturing, ongoing research and
development in a highly competitive environment is conducted to produce new
and better devices, which are manufactured by usually well-know techniques
involving many ways of treating semiconductor materials (wafers), applying
thin-film materials, patterning, and selectively removing materials to create
highly concentrated matrices of interconnected semiconductor elements, such
as transistors, providing, in the end, minute, complex circuitry to perform
specific tasks of computation and logic with almost unbelievable rapidity and
reliability.
Also typically, in the manufacturing process, many ICs are formed on a
single wafer. After what is termed in the art the "front-end" processing, during
which the ICs are formed, the individual ICs are separated into discrete units
termed chips in the art, which may then be packaged and used in a wide variety
ofways for different products and purposes.
When developmental engineers conceive a new chip, it is of course
necessary to lay out all of the circuits that will accomplish the purposes, which
amounts to placing all transistors, resistors, and other devices, and plotting the
interconnections that complete the circuitry. In the very early days of chip
design this was a relatively straightforward process, at least a lot more
straightforward than it is today. The trend in design, however, has always
quite naturally been to faster and faster operation (clock speed), higher and
higher density (area needed for circuitry), and lower power consumption to
attain maximum computing or storage power in the least possible space. The
speed motivation is obvious. Part ofthe density motivation is dictated by
space and volume requirements in product design, and part by cost
considerations. More good chips per wafer drives the cost per part down.
-3-
As need for density and speed steadily increase, new challenges arise in
IC design. For example, specific manufacturing techniques, lithography for
example, are always limited to such as minimum spacing of elements on a
chip, line width in interconnects, and the like, and to achieve higher density it
is often necessary to invent new processing techniques or improvements in
older techniques. Likewise, even though higher density has a usually
beneficial effect on speed capability (devices are connected closer together),
allowing higher operating rate (clock speed), there are always limitations
associated with device structure, materials, and the like, to speed as welt, and
achieving higher and higher speed involves new inventions and discoveries in
materials, combinations of materials, structures of devices, and so on.
It therefore becomes apparent that a circuit diagram is only a starting
point in a new IC design, even though massive computing engines are needed
even for this seminal part of a design. Given stringent requirements for a new
design for speed, density, and power consumption, development engineers
have to pick very carefully among many alternatives for materials, processes,
film characteristics and thicknesses, interconnection alternatives, and much
more; and the selections one makes almost always influence other possible
selections and decisions, as all are intimately related.
Still, even in the face of the complexity ofthe task, small market
windows and short product lifecycles provide no room for error in the
execution of chip design projects - schedule slippage is measured not just in
terms of additional R&D costs, but in lost market opportunities that can be
fatal for a company. Integrated circuit designers are therefore under
tremendous pressure to design complex chips to meet design and marketing
requirements.
The design of complex multi-million-transistor chips requires the
pervasive use of electronic design automation (EDA) software tools. These
tools are used to take high-level descriptions of designs in languages that are
"!L !L!!
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very similar to programming languages and yield, through a series of
complicated steps, the final mask for a chip. This flow is referred to as RTL to
GDS-II (RTL is the initial design description in Verilog, VHDL and GDS-II is
the mask for chip manufacturing).
To counter the risk of designs not converging on requirements,
engineers use virtual prototyping tools, a type ofEDA tool, to estimate
downstream chip implementation characteristics (speed, area, power) from
early design descriptions. The intent is to get an early gauge of design
feasibility. Virtual prototyping tools have garnered significant interest in the
design community, and virtual prototyping is among the fastest growing of
EDA market segments.
Virtual prototyping tools arguably provide reasonable estimates of
delays along timing paths on a chip. The feasibility of a design, however,
hinges on whether these delays are actually within acceptable bounds. Without
good constraints on the permissible delays for the millions of timing paths on a
chip, virtual prototyping tools are insufficient to gauge actual design
feasibility. Absence of good timing constraints early in the design flow also
results in chip implementation tools (logic synthesis, place & route) being
asked to meet requirements that are both unnecessarily stringent and uncertain.
This severely impacts ability of such tools to generate low-cost, low-power
implementations that meet performance requirements without requiring design
iterations.
What is clearly needed is a tool that starts with the fundamental speed
performance requirements for an IC to be designed, i.e. its clock speed, and by
examining the intended functionality ofthe new chip in regard to how it will
be clocked is capable of precisely identifying and constraining acceptable
delays of timing paths on the new chip. Such a tool could generate golden
timing constraints that must be obeyed for the finished chip to operate at its
intended clock speed. Fundamental to the golden timing constraints for a chip
!!"'!!
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is that they describe not only the bounds on path delays that are established by
the clock requirements of a chip, but that they also identify paths on a chip
where clock requirements are relaxed. The relaxation of clock requirements is
referred to in the industry as "exceptions to single-cycle clocking". The
automatic identification ofthe exceptions to single-cycle clocking is
fundamental to the generation of the golden timing constraints for a chip.
The golden constraints, once determined, could then be used to drive
existing virtual prototyping tools, logic synthesis tools, and place & route
tools. The use of the golden constraints could, because of the automatically
generated exceptions to clock requirements, then empower chip design without
expensive and time consuming iterations, while also yielding chips that
consume less area, less power, or, if required, run faster than was thought
possible.
A unique and innovative software system, called Focus by the
inventors, for developing such golden timing constraints in IC design is taught
in enabling detail in the descriptions of preferred embodiments below.
Summary of the Invention
In a preferred embodiment ofthe present invention a software-based
system for generating timing constraints for a proposed IC design is provided,
comprising a first input as a synthesizable description of the proposed IC, a
second input as a clock specification for the proposed IC, and a processing unit
accepting the first and second inputs, and determining therefrom as an output a
set oftiming constraints to guide implementation ofthe proposed IC design.
In preferred embodiments, the processing unit, in determining the
timing constraints, determines exceptions to single-cycle clocking for the
proposed IC design. Further, in a preferred embodiment the exceptions include
-6-
false paths and multi-cycle paths. Output in a preferred embodiment is
provided in Synopsys Design Constraint (SDC) format useable by one or more
of virtual prototyping, logic synthesis, place & route, and static timing tools in
design implementation. The IC may be of any of many sorts, including
application-specific integrated circuits (ASIC) or field-programmable gate
arrays (FPGA).
In one aspect of the invention the first and second inputs and output
timing constraints may be for an individual functional block on an IC instead
of for the entire I C. In another aspect the first and second inputs and output
timing constraints may be for paths between functional blocks on an IC. In the
latter case the results may be used to partition overall IC timing requirements
into b Jock timing budgets.
In preferred embodiments the synthesizable description is provided as
one ofVerilog or VHDL format. In other embodiments the first input may be
derived from a Jib model, and converted into one ofVerilog or VHDL format.
In one embodiment a facility is provided for a user to manually refine an
automatically-generated model by adding functional detaiL In various
embodiments, as a part of clock specification, users may define the clocks,
their periods, their phase shifts relative to a reference clock, and the nets on the
design to which a clock is applied.
In another aspect of the invention a method for guiding an
implementation phase for a proposed IC design is provided, comprising the
steps of (a) providing to a processing unit as a first input a synthesizable
description ofthe proposed IC; (b) providing as a second input to the
processing unit clock specification for the proposed IC; and (c) using the first
and the second inputs by the processing unit to determine therefrom, as an
output, a set of timing constraints to guide implementation of the proposed IC
design.
- 7-
In preferred embodiments ofthe method, in step (c), the processing
unit, in determining the timing constraints, determines exceptions to single
cycle clocking for the proposed IC design. The exceptions may include false
paths and multi-cycle paths.
Also in preferred embodiments ofthe invention the output is provided
in Synopsys Design Constraint (SDC) format useable by one or more ofvirtual
prototyping, logic synthesis, place & route, and static timing tools in design
implementation. The method in preferred embodiments is applicable
application-specific integrated circuits (ASICs) or field-programmable gate
arrays (FPGAs), as well as to many other sorts ofiCs.
In some cases the first and second inputs and output timing constraints
may be for an individual functional block on an IC instead of for the entire IC.
Also in some cases the first and second inputs and output timing constraints are
for interaction paths between functional blocks on an IC, and may be used to
partition overall IC timing requirements into block timing budgets.
In preferred embodiments the synthesizable description is provided as
one ofVerilog or VHDL format. In other embodiments the first input may be
derived from a .lib model, and converted into one ofVerilog or VHDL format.
Further, there may be a facility provided for a user to manually refine an
automatically-generated model by adding functional detail.
In other embodiments of the present invention, as part of the clock
specification, users define the clocks, their periods, their phase shifts relative to
a reference clock, and the nets on the design to which a clock is applied.
The Focus system, as summarized above, provides significant
advantages in IC design, by providing:
• A reduction in the risk of design failures by providing engineers an
early understanding of the precise challenges they face in realizing a
design. By providing virtual-prototyping tools with golden timing
-8-
constraints, the Focus system empowers the tools to create more
DECLARATION AND PO\VER OF ATTORNEY FOR PATENT APPLICATION
A TIORNEY DOCKET NO. P1377
As a below named inventoT, I hereby declare that: My residence, post office address and citizenship are as stated be low nex.t to my name. I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first lllldjoint inventor (if plural names are listed below) of the subject matter which is claimed and for which a patent is sought on the invention entitled: Automated APProach to Constraint Generation in IC Design
the specification of which (check one) ~ is attached hereto. 0 was filed on: as patent aoolication serial number 0 and was amended on __
(If applicable) I hereby state that 1 have reviewed and understood the contents of the above-identified specification, including the
claims, as amended by any amendment referred to above. I acknowledge tbe duty to disclose information which is material to patentability in accordance with Title 37, Code of Federal Regulations sec. 1.56. In the case that the present application is a continuation-in-part application, J further acknowledge the duty to disclose material information as defined in Title 37, Code of Federal Re~ulations sec. 1.56. which became available between the filing date ofthe prior application and the filing date of the present application. I hereby claim foreign priority benefits under Title 35, United States Code sl19 of any foreign applications for patent or inventor's certificate listed below and have also identified below any foreign application for patent or inventor's certificate having a filing date before that ofthe application on which priority is claimed:
I hereby claim the benefit under Title 35, United States Codes, sec. 119 and sec. 120 of any United States application(s) listed below and, insofar as the subject matter of each of the claims of this application is not disclosed in the prior United States application in the manner provided by the tirst paragraph of Title 35, United States Code, sec. 112, I acknowledge the duty to disclose material mformation as defined in Title 37, Code of Federal Regulations, sec. 156(a) which occurred between the filing date of the prior application and the national or PCT international filing date of this application.
(Status):~ (Application Serial No.): 60/365.749 (Filing Date): 03/1 &/2002 (Application Serial No.): __ (Filing Date): __ (Status):---(Application Serial No.):__ (Filing Date): __ (Status}:---(Application Serial No.): __ (Filing Date): __ (Status):----{Application Serial No.):__ (Filing Date): __ (Status): ___ _
POWER OF AITORNEY: As a named inventor, I hereby appoint:
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ATTORNEY DOCKET ~0. P1377
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+140=
TOTAL ADOIT. FEE
ADDI-RATE TIONAL
FEE
X$9=
X42=
+140=
TOTAL ADDIT. FEE
ADD I-RATE TIONAL
FEE
X$9=
X42=
+140=
TOTAL
OTHER THAN OR SMALL ENTITY
OR X$18=
OR X84=
OR +280=
OR TOTAL
OTHER THAN OR SMALL ENTITY
ADD I-RATE TIONAL
OR X$18=
OR X84=.
OR +280=
ADD I-RATE TIONAL
OR X$18=
OR X84=
OR +280=
ADDI-RATE TIONAL
OR X$18=
OR X84=
OR .+280=
~If the "Highest Number Previously Paid For" IN'•T.HIS SPACE. is less than 3, enter "3." . The "Highest Number Previously Paid For" (Total or Independent) is the highest number found in the appropriate box in column 1.
ADDIT. FEE
FORM PTC>-875 (Rev. 1 2/02) OF COMMERCE
•. -
MUL nPLE DEPENDENT CLAJM FEE CALCULAnON SHEET
I 1 AFTEI\ 10 IV' I tiUNU A3 nLEP AMENDMENT AMfHOMEH1'
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Substitute for form 1449A/PTO Complet if Known
INFORMATION DISCLOSURE Application Number NA Flllna Date 03114/2003
STATEMENT BY APPUCAN'f First Named Inventor Ajay Janami Daga Art Unit NA
(use as many sheets as necessary) Examiner Name NA <"L t I 1 I ot I 1 Attorney Docket Number P1377
'EXAMINER: Initial if reference considered, whether or not citation is in conformance with MPEP 609. Draw line through citation if not in conformance and not considered. Include copy of this form with next communication to applicant. 1 Applicant's unique citation designation number (optional). 2 See Kinds Codes of USPTO Patent Documents at www.uspto.g!lV or MPEP 901.04. 3 Enter Office that issued the document, by the two-letter code (WIPO Standard ST.3). 4 For Japanese patent documents, the indication of the year of the reign of the Emperor must precede the serial number of the patent document. 5 Kind of document by the appropriate symbols as Indicated on the document under WIPO Standard ST. 16 if possible. 6 Applicant is to place a check mark here if English language Translation is attached. Burden Hour Statement: This form is estimated to take 2.0 hours to complete. Time will vary depending upon the needs of the individual case. Any comments on the amount of time you are required to complete this form should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Assistant Commissioner for Patents, Washington, DC 20231.