Wide band RF CMOS circuit design techniquesewh.ieee.org/r5/denver/sscs/Presentations/2010_05_Leenaerts.pdfWide band RF CMOS circuit design techniques SSCS DLP, Fort Collins ... WCDMA/HSPA/EGPRS+

Wide band RF CMOS circuit design techniques

SSCS DLP, Fort Collins

design techniques

Domine Leenaerts

Semiconductors, The Netherlands

Content

• Why wide band RF design?• How to make a wide band LNA?• What about the wide band Rx

architecture?architecture?• What about the technology?• Conclusions

History: SpeakEasy project (1992)

• Large scale military software defined radio

• motivated in large part by the communications interoperability problems that resulted from different branches of the military services having different branches of the military services having dissimilar (non-interoperable) radio systems

• ten different radio waveforms in software on a single platform operating in frequency bands between 2 and 2000 MHz

• Operated initially at the TMS320C40 processor

RJ Lackey and DW Upmal, "Speakeasy: The Military So ftware Radio," IEEE Communications Magazine, May 199 5

History: SpeakEasy project (1992)

LNA ADC

PA DAC

µPLNA ADC

PA DAC

µP

TM

S32

0C40

TM

S32

0C40

Final result in 1994:

several hunderd processors and the ‘radio’ filled the back of a truck

Today: 10 different standards?

There is a convergence of standards ongoing, but st ill…

Today: 10 different standards?

Frequency (GHz)

Today in industry

WCDMA/HSDPA/HSUPA/EGPRS, Skyworks

130nm cmos

ISSCC 2009

Today in industry

WCDMA/HSPA/EGPRS+ GPS and Rx diversity

WCDMA:4-LNA Primary Rx (2 SAW-less)

WCDMA:3-LNA diversity

Quad-Band GSM/EDGE (800-900-1800-1900)

0.18um CMOS ISSCC 2009

Quad-Band GSM/EDGE (800-900-1800-1900)

Qualcomm

Today in industry

HSUPA+BT+FM in 65nm CMOSSource: www.broadcom.com

Today in industry

• Industrial focus is on– Multi-band / multi-mode– Selectivity at RF

• Front-end module by means of antenna filters• Front-end module by means of antenna filters• Selective LNA’s• LO generation per mode or band

Software-defined radio (SDR)

• Based on signal processing– A/D requirements– Digital processing

LNA ADC

PA DAC

µPLNA ADC

PA DAC

µP

Use Reconfigurable radio instead

• Analog selectivity– A/D requirements more relaxed– Wide-band RF front-end– Digitally assisted radio / FE module– Digitally assisted radio / FE module

IQ-DAC

IQ-ADC

TX-filter

RX-filter

LO generation XO

radio

CAL

switc

h

FE module

BB

-MA

C p

roce

ssor

Dig

ital b

acke

ndIQ-DAC

IQ-ADC

TX-filter

RX-filter

LO generation XO

radio

CAL

switc

h

FE module

BB

-MA

C p

roce

ssor

Dig

ital b

acke

nd

Need of Wide-band RF front-ends

• First attempts were made by the development of UWB chipsets– 3 – 10 GHz– Started in 2003 with LNA design (see ISSCC – Started in 2003 with LNA design (see ISSCC

2004)

• Now focus on reconfigurable front-ends for 0 – 5 GHz operation– Started around 2005 (see ISSCC 2006)

Wide band LNA: What’s the problem?

Impedance match

Z

deliavsis PPZZ ,,* =⇒=

Z

Noise matchopts ZZ =

ZZiZs

Zi is mainly capacitive

Zopt

Im(Zopt ) is inductive in nature

How to obtain power match and noise match over wide bandwidth?

What is the problem?

Zs Zs

Wide band impedance match

Zs

Narrow band impedance match

Zs Zs

smRgF

142

αγ+≥

NF >> 3dB

s

s

QR

LF

ω3

21+≥

Zs

Ls

gss

gs

smin sC

sLC

LgZ

1++≈

Possible solution

Zs

filter

Wide band impedance match using filter as impedance converter

Zs

Ls

The first attempts

ISSCC2004: Ismail

Band-pass LC matching network

ISSCC2004: Bevilacqua

Band-pass LC matching network

Both are bulky due to # integrated inductorsand single-ended input/output

NF: 5.5dB (3-8GHz) NF: 4.5dB (2-10GHz)

Other possible solution

ZZs

min g

Z1≈

Zs

Ls

( )CGOQR

LF

s

s ++≥ ω3

21

Note: inherent single-to-differential conversion

min g

Z1≈

‘Second’ Generation

90nm CMOS

NF: 4.5dB (0.8-5GHz)

ISSCC 2006

decouple the noise and input impedance matchbut still bulky

Next generation: starting point

Simultaneous:• Single-to-Differential• Balanced Gain• Broadband input

vout+ -• Broadband input

match ( ~1/gmCG )• Noise Canceling• Distortion Canceling

[Blaakmeer et al. ESSCIRC `07]

RS

vsvin

+

-

CG CS

IBias

LNA: noise canceling

200Ω 50Ω

Noise canceled, signal amplified at differential output

vin

+

-Ibias

in

50Ω

20mS

80mS

vs

LNA: limited bandwidth

→ CLoad < 80 fF4 @ Ω200 ==

⋅=

CGV,

SCGV,CG

A

RAR

• Limited bandwidth at output CG-stage:

• Inductive peaking required– Contrasts aim: no on-chip inductors

Solution: don’t make voltage gain @ RF!

→ CLoad < 80 fF

GHz 10 2

1 =⋅⋅⋅

= π LoadCG3dB- CR

f

Solution: insert mixer

IF: Capacitanceno problem

Mixer: Low-Z input

Z4·Z

RS

vs

RF: no high-Z nodes

Mixer: Low-Z input

Low-Z

LO

gm

4·gm

IBias

Solution: insert mixer

WIF+ IF-

Z4·Z

R

3·R

3·C

C

gm·vrf4·gm·vrf

vs

RS

W4·WLO+ LO-

vrf+

-

‘CG’

‘CS’

Solution: noise cancellation @ IF

WIF+ IF-

Z4·Z

R

3·R

3·C

C

gm·vrf4·gm·vrf

vs

RS

W4·WLO+ LO-

vrf+

-

‘CG’

‘CS’

BLixer: IQ balanced

LO Q-

IF Q+ IF Q-

4·ZZ

LO I+ LO I- LO Q+

IF I-IF I+

I-Mixer Q-Mixer

LO Q-

IF Q+ IF Q-

4·ZZ

LO I+ LO I- LO Q+

IF I-IF I+

I-Mixer Q-Mixer

BalunLNAMixer →Blixer

4·i

LO Q+

vs

RS

IBias

i 4·i

LO Q+

vs

RS

IBias

i

BLixer: 50% duty cycle

LO Q-

IF Q+ IF Q-

4·ZZ

LO I+ LO I- LO Q+ LO Q-

IF Q+ IF Q-

4·ZZ


IF Q+ IF Q-

4·ZZ


4·i

LO I+ LO I- LO Q+

vs

RS

IBias

i

LO Q-

4·i

LO I+ LO I- LO Q+

vs

RS

IBias

i

LO Q-

4·i

LO I+ LO I- LO Q+

vs

RS

IBias

iLO Q+

LO I+

LO Q-

LO I-

BLixer: 25% duty cycle

LO Q-

IF Q+ IF Q-

4·ZZ


IF Q+ IF Q-

4·ZZ


IF Q+ IF Q-

4·ZZ


4·i

LO I+ LO I- LO Q+

vs

RS

IBias

i

LO Q-

4·i

LO I+ LO I- LO Q+

vs

RS

IBias

i

LO Q-

4·i

LO I+ LO I- LO Q+

vs

RS

IBias

iLO Q+

LO I+

LO Q-

LO I-

BLixer: silicon

Baseline65nm CMOS1.2V supply

OSC

IN IF OutLbias

OSC

IF I+LO gen + buf

1.4 mm

Active area< 0.02 mm2IN

IF I+IF I-

IF Q+IF Q-

Supply & Biasing

LO gen + buf

Core + IF-bufBiasing

1.4 mm

[Blaakmeer et al. ISSCC ‘08]

BLixer: measured results[d

B]

-20

-10

0

10

20GC

NF

20GC

Wide band behavior at RF

RX-frequency [GHz]1 10

-30

-20S11

fIF [MHz]10 100

[dB

]

0

5

10

15

500

GC

NF… and at IF/BB

BLixer: measured results

• Linearity:– IIP3 @ RF: -3 dBm ( 5.2 & 5.7GHz, fLO = 4.6 GHz )

– IIP2 @ RF: +20 dBm ( 2.4 & 5.7GHz, fLO = 3.2 GHz )

– IIP2 (Mix-leak.) >+40 dBm (5.7 & 5.8GHz, fLO:0.5 - 7 GHz)LO

• Quadrature accuracy:– Phase error < 3°– Gain error < 1dB

• LO leakage < -50 dBm

What about inverters?

Cesd

VSS

INV1X6RF

VBDVBD10

12

14

gain

, NF

, S11

[dB

]GaNFS11

VSS

VDD

outin

VBD

VBS

VSS

VDD

outin

VBD

VBS

-2

0

2

4

6

8

10

0 5 10 15 20 25

frequency [GHz]

gain

, NF

, S11

[dB

]


Add package:

HVQFN

2

4

6

8

10

12

14

gain

, NF

, S11

[dB

]

GaNFS11Ga_packageNF_packageS11_package

Cesd

VSS

INV1X6HVQFNRF LNA

-2

0

2

0 5 10 15 20 25

frequency [GHz]


2

4

6

8

10

12

14

gain

, NF

, S11

[dB

]

Ga_packageNF_packageS11_packageGA_PANF_PAS11_PA

Cesd

VSS

INV1X6HVQFNRF

INV

1X10

PA

LNA

-2

0

2

0 5 10 15 20 25

frequency [GHz]

‘Inverter-only’ LNA

INV

1X10

PA INV1X0.5

No inductors!

Add additional stage and feedback in LNA

Cesd

VSS

INV1X6HVQFNRF

LNA

INV1X4

‘Inverter-only’ LNA

5

10

15

20

gain

, NF

, S11

[dB

]

GA_PANF_PAS11_PAGA_FBNF_FBS11_FB

-20

-15

-10

-5

0

0 5 10 15 20 25

frequency [GHz]

gain

, NF

, S11

[dB

]

‘Inverter-only’ PA

INV

1X6

PALNA

No inductors!

Cesd

VSS

INV1X4 HVQFN

RFINV1X4 INV1X10

Add additional stages and feedback in PA

‘Inverter-only’ PA

5

10

15

20ga

in, S

22 [d

B]

GpS22

-20

-15

-10

-5

0

0 5 10 15 20 25

frequency [GHz]

gain

, S22

[dB

]

RF front-end only with inverters!RF I/O

Noi

se F

igur

e [d

B]

Measured NF of front-end in BG1


Noi

se F

igur

e [d

B]



radio65nm (LP) CMOS

Frequency [Hz]

Noi

se F

igur

e [d

B]

Simulated NF of LNA only

Measured NF of LNA only

Frequency [Hz]

Noi

se F

igur

e [d

B]

Simulated NF of LNA only

Measured NF of LNA only

[Leenaerts et al. ISSCC ‘09]

• We can make wide band LNA’s, but what about the receiver?

What about the RX architecture?

• Commodity is to use passive mixers– Inherently wide band nature as they act as

switch only– Can be made very linear– Can be made very linear

• Followed by analogue wide band BB filters– Tunable in filter order, bandwidth

‘Classical’ ZIF architecture

ISSCC 2009: IMEC, SDR in 45nm CMOS

... but how to handle interferers?

Nonlinear !!

Wide band at RF give rise to interference issuesISSCC 2009: Ru, SDR in 65nm CMOS


and ‘square-wave’ LO results in harmonic mixing


• One solution is to use band-pass filters– Need tunable BP, difficult at RF

• Other solution is to NOT make (too much) gain at RFgain at RF

ESSCIRC 2001: Leenaerts, 180nm CMOS

… but harmonic mixing remains

harmonic rejection mixer removes 3*LO and 5*LO

Amplitude weighting

Phase shifting

Emulate sine-wave LO

ISSCC 2001: Weldon

… but how to make accurate?2

ISSCC 2009: Ru

41=2x5 + 3x7 +2x529=3x5 + 2x7

41/29 = 1.4138 and = 1.4142, so error is 0.03%2

2-stage poly phase network

And the result …

65nm CMOS

… but what about other interferers?

• Harmonic mixing helps only for interferers which are at harmonics of the used LO frequency

• How do we improve robustness against • How do we improve robustness against other interferers?– Make notch at RF

Notch at RF by translational loop

Darabi, ISSCC 2007

Notch at RF by translational loop

Darabi, ISSCC 2007

Impact on NF of LNA is 3dB, so activate filter only in presence of interferer

Some conclusions

• Wide Band CMOS design is possible– Convergence towards a receiver comprising

wide band LNA, passive mixers and BB filteringfiltering

– Additional tricks added to cope with interference are still needed

• But which technology is favorable?

What about the technology?

Does CMOS scaling improves wide band behavior?

• Technology RF performance– 180nm, 90nm, 65nm, 45nm

• UWB CMOS circuits – 90nm, 65nm, 45nm (and SiGe BiCMOS)

• UWB receiver design– 65nm, 45nm

Used technology• All experiments have been done in a low

standby power process node, i.e. LP CMOS

CMOS 90nm 65nm 45nm

Lgate [um] 0.1 0.06 0.04

Vdd [V] 1.2 1.2 1.1

Iem,M1,minW [mA@110 C]

0.21 0.11 0.07

#metal 6 + ALU 7 + ALU 7 + ALU

Technology

distance

ArearoC εε=

Some definitions

• Cut-off frequency ft– unity gain current frequency for short-circuited output

gg

mT C

gf

π2~ input capacitance

• Voltage gain bandwidth fa– Frequency for 3-dB DC voltage gain drop, calculated

for a resistive load making the DC voltage gain 2x

dddc

mA CA

gf

π2~ output capacitance

Some definitions

• 1-dB minimum Noise Figure frequency (fNF1dB)– frequency for which this NF is still reached assuming

optimum NF matching

• Finger width Wf– Folded device finger width: Wf = W/FOLD – Folded device finger width: Wf = W/FOLD

Difference schematic - layout

• Schematic– MOS model takes into account naked device

behavior.

• Layout• Layout– parasitics due to metal connections,

especially CO-M1– metal layers to fulfill current reliability

Layout has major impact in deep sub-micron

Difference schematic - layout100

GH

z

80

60

50

no interconnect

• NMOS device• L = 0.18 um• W = 32 um• contact = 2• @ fold = 8

f T G

Hz

Folding factor

1 102 3 4 6 8 20 30

50

40

30

with interconnect–– fT =70 GHzfT =70 GHz–– fT =60 GHzfT =60 GHz

gate

p+ guard-ring

gate

S S S S SD D D D

Comparison of this effect

• For both devices: single finger, double gate contact– Purple: schematic (naked

device)– Blue: layout extraction

• Serious impact of metallization

90nm W/L = 0.12um/0.1um

0

10

20

30

40

50

60

70

80

90

ft [G

Hz]

• Serious impact of metallization– 90nm: 70%– 65nm: 55%

0

0.001 0.01 0.1 1

drain current [m A]

65nm W=0.12um L=0.06um

0

10

20

30

40

50

60

70

80

90

0.001 0.01 0.1 1

drain current [mA]

ft [G

Hz]

65/45nm: ft obtained after layout

65nm L=0.06um

60

80

100

120

ft [G

Hz] W=0.12um

W=1um

45nm L=0.04um

150

200

250

ft [G

Hz] W=2um

W=10um

(Wf = 0.5 um for 1 and 10 um)

0

20

40

0,001 0,01 0,1 1 10 100

drain current [mA]

ft [G

Hz]

W=10um

65nm LP: ft naked device: 160GHz

0

50

100

0.001 0.01 0.1 1 10 100

drain current [mA]

ft [G

Hz]

W=10um

(Wf = 0.5 um for 2 and 10 um)

45nm LP: ft naked device: 270 GHz

Comparison for ft: scaling helps

W=10um, FOLD=20

150

200

250

ft [G

Hz] 90nm

0

50

100

150

0.1 1 10 100

drain current [mA]

ft [G

Hz] 90nm

65nm45nm

65nm: influence of finger-width

65nm: W=10um, L=0.06um

200.0

250.0

300.0

350.0

freq

uenc

y [G

Hz] ft

fa_2

0.0

50.0

100.0

150.0

200.0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Wf = W/FOLD [um]

freq

uenc

y [G

Hz]

fa_2

fNF1dB

fmax

fcross

seems optimal layout includes only M1

RF performance incl. all layout effect

CMOS ft [GHz] fa [GHz fNF1dB [GHz] Wf opt.

180nm 41 39 10 ≈ 3

90nm 80 72 40 ≈ 1.790nm 80 72 40 ≈ 1.7

65nm 120 110 44 ≈ 1

45nm 200 130 53 ≈ 0.67

Wf/Lmin ≈ 16

How realistic is peak ft, fa?

• Peak values are normally reached for Vgs close to Vdd– happens for instance in cross-coupled diff pair

in most VCO topologiesin most VCO topologies

• But what happens in more realistic situations, e.g. Vgs = 1/2Vdd?– e.g. situation in frequency divider, LNA, …


90nm, W=1um, L=0.1um

60

70

80

90

freq

uenc

y [G

Hz]

38%

0

10

20

30

40

50

60

0.1 1 10

Vgs [V]

freq

uenc

y [G

Hz]

ft

faVgs=1.2V

Vgs=0.6V

38%


CMOS 90nm 65nm 45nm

Naked device

115 160 270

Vgs=Vdd 80 / 72 120 / 110 200 / 130

Vgs=1/2Vdd 49 / 38 51 / 41 47 / 28

x / y = ft / fa [GHz / GHz]

Scaling and wide band RF

• LNA performance• Frequency divider performance• Dual band receiver in 65nm• Dual band receiver in 45nm• Dual band receiver in 45nm

A CMOS wide band LNA

Vdd

OUT-VB

IN

0

OUT+Vss

Transformer:• Single-ended differential• Impedance matching• Voltage feedback

[ISSCC2007, Lee et al.]

Resistor:• Current feedback

A CMOS wide band LNA: 65nm

Gain: 11dB

3-dB BW: 7.5GHz

NF: 2.5dB

iIP2: +25dBm

[ISSCC2007]

A CMOS wide band LNA: 45nm

NF

Gv

S11

Gain: 8dB

3-dB BW: 11GHz

NF: 3dB

iIP2: +25dBm

S11

CMOS LNA: comparison

• Input device (for roughly same gm)– W/L 90nm: 200/0.1 um/um– W/L 65nm: 240/0.06 um/um– W/L 45nm: 200/0.04 um/um

x2

x1.25– W/L 45nm: 200/0.04 um/um

Vdd

OUT-VB

IN

OUT+Vss

0

CMOS LNA: comparison

LNA 90nm 65nm 45nm

Gv [dB] 9 11 10

BW [GHz] 7.5 7.5 11

NF [dB] 2.5 2.5 3

iIP2 [dBm] +15 +25 +25

iIP3 [dBm] 0 +12 +6

Pdiss [mW] 18 20 30

CMOS LNA versus BiCMOS

NF

S21

S11 (measured on PCB)

[dB]

S11(chip)

NF

S21

S11 (measured on PCB)

[dB]

S11(chip)

[ISSCC2005]

S12

[GHz]

S12

[GHz]

LNA 65nm SiGe 0.25um

Gv [dB] 11 20

BW [GHz] 7.5 12

NF [dB] 2.5 3

iIP2 [dBm] +25 +25

iIP3 [dBm] +12 +10

Pdiss [mW] 20 12

65nm and 45nm divider chainVDD

out0

out90

out180

out270

VDD

out0

out90

out180

out270

÷2in

out0out180

CLK

CLKb

Vbias

VSS

CLK

CLKb

Vbias

VSS

divider measurements

-10

0

10P

in [d

Bm

]

65nm

-50

-40

-30

-20

0 5 10 15 20 25

input frequency [GHz]

Pin

[dB

m]

65nm

45nm

divider measurements

CMOS 65nm 45nm

Self resonance 14GHz 18GHz

Max input freq. 18GHz 21GHz

Pin -14dBm -9dBm

Pdiss 18mW 24mW

UWB transceiver in 65nm

TIA

TIA

LNA

VtoI

VtoI

BG

1 /

BG

3 ÷2

mat

chin

g

BB

out

Ext

. LO

TIA

TIA

LNA

VtoI

VtoI

BG

1 /

BG

3 ÷2

mat

chin

gm

atch

ing

BB

out

Ext

. LO

A

select

VC

OV

CO

VC

O

BG

1 /

BG

3X

mat

chin

g

PA

BB

in

Ext

. LO

Bias &

Control

A

select

VC

OV

CO

VC

OV

CO

VC

OV

CO

BG

1 /

BG

3X

mat

chin

gm

atch

ing

PA

BB

in

Ext

. LO

Bias &

Control


At mixer output, 3.2 -- 7.7 GHz< 2 dBTx output flatness

At mixer output, w/o PA4 %Tx output EVM

Two-tone: fin1=1.8 GHz, fin2=2.4 GHz+6 dBmRx IIP3

IF-input to mixer output, w/o PA+52 dBTx gain

fin= 4 GHz / 7 GHz5.0 / 5.5 dB Rx noise figure

Receiver52 mWDissipation @ 1.2V


Voltage gain, RF input to IF-output20 dBRx Gain

CommentValueParameter

At mixer output, 3.2 -- 7.7 GHz< 2 dBTx output flatness

At mixer output, w/o PA4 %Tx output EVM


IF-input to mixer output, w/o PA+52 dBTx gain

fin= 4 GHz / 7 GHz5.0 / 5.5 dB Rx noise figure

Receiver52 mWDissipation @ 1.2V


Voltage gain, RF input to IF-output20 dBRx Gain

CommentValueParameter

LNA/PA

ReceiverTransmitterLO generation

52 mW48 mW63 mW

Dissipation @ 1.2V ReceiverTransmitterLO generation

52 mW48 mW63 mW

Dissipation @ 1.2V

BB

filte

rs

LO

1mm


S21

NF band1

dB

NF band9

dB

S21

NF band1

dB

NF band9

dB

S11

MHz

dB

MHz

dB

S11

MHz

dB

MHz

dB


2nd harm.spurs

Band Group #1 Band Group #3

LOleakageleakage

UWB receiver in 45nm

RF front-end

1mm

IF stage

LO stage

Bias

UWB receiver in 45nm

10

12

14

16G

ain,

Noi

se [d

B]

-10.00

-5.00

0.00

S11

[dB

]

0

2

4

6

8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

frequency [GHz]

Gai

n, N

oise

[dB

]

-25.00

-20.00

-15.00 S11

[dB

]

Comparison of 65nm-45nm RX

BB filter

65nm LP CMOS 45nm LP CMOS

Dies on scale : analog does not necessarily scale!

LNA

Comparison of 65nm-45nm RX

Rx performance

65nm 45nm

Gain [dB] 20 14

3-dB BW [GHz] 7 103-dB BW [GHz] 7 10

NF [dB] 5.5 7

iIP3 [dB] +5 0

iIP2 [dB] +25 +20

Pdiss [mW] 52 90

Where do we stand nowadays?

• Wide Band CMOS design is possible– Convergence towards a receiver comprising

wide band LNA, passive mixers and BB filtering– Additional tricks added to cope with interference – Additional tricks added to cope with interference

are still needed

• Impressive fT of naked device due to scaling does not tell the complete story– Layout influence becomes more and more

dominant

Hope you learned something

Wide band RF CMOS circuit design techniquesewh.ieee.org/r5/denver/sscs/Presentations/2010_05_Leenaerts.pdfWide band RF CMOS circuit design techniques SSCS DLP, Fort Collins ... WCDMA/HSPA/EGPRS+

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