Wafer Level CSP Overview Fillion 2011

SMTA Ohio Valley Chapter

Advanced Packaging Technologies: Chip Scale, Embedded Chip

and 3D Packaging

Ray Fillion

Fillion [email protected]

518-810-1519

mailto:[email protected]

©Ray Fillion 2011 2

Chip Scale Packaging, Embedded Chip Packaging and 3D Packaging

Presentation OutlinePackaging Introduction Chip Scale Packaging Wafer Level Chip Scale PackagingEmbedded Chip Packaging Embedded WLCSP Embedded Chip SiP/MCM Packaging3D PackagingSummary


Functions of a Package?• Signal Distribution: Minimize interconnect inductance, resistance, crosstalk & delays:

• Power Delivery: Minimize rail inductance, resistance, noise & ground bounce:

• Thermal Dissipation: Provide cooling paths:

• Mechanical Protection: from damaging stress, strain or shock:

• Environmental Protection: Provide a barrier to moisture, liquids:

• I/O Pitch Reconfiguration: Transformation from chip features to PCB compatible features:


Background: Thru-Hole

Ceramic DIPDual-in-Line Package

Plastic DIPDual-in-Line Package

The first packages were Dual-in-Line packages (DIPs) that had leads on a 100 mil (2.5 mm) pitch, that were inserted into holes in a circuit board and soldered in place. The circuit

board could be a simple single-sided or double-sided epoxy-glass (FR-4) or a complex multilayer board with 4 or more

layers. DIPs were limited to low I/O counts, typically 8 – 64 and the thru-holes limited PCB routing.


LCC- Leadless Chip Carrier

TSOP- Thin Small Outline Packager

LQFP (0.5 mm) Leaded Quad Flat Package

In the 1980’s, SMT was introduced with leaded and perimeter leadless surface mounted devices solder

attached onto the surface of the circuit board. Lead pitch shrunk to 50 mils (1.25 mm) and later down to 25 (0.625

mm) and even 20 mils (0.50 mm) and I/O count increased to about 250, a 4x increase over DIPs. High pin count SMTs

had fragile leads and low assembly yields.

Background: Surface Mount


In the 1990’s, Ball Grid Array (BGA) packages were introduced that utilized solder balls to connect an array pads on the

package bottom surface to the board. Chips could be wire bonded or flip chip attached to the BGA carrier. Solder pads were on 1.5 mm and 1.25 mm grid arrays. This increased I/O capability by a factor of 5x to 10x permitting packages with

1000 to 2000 I/Os and had very high assembly yields.

IBM Cavity Down BGA

Background: Ball Grid Array


Chip Scale Packaging:

A chip scale package is a packaged chip that is the same size as or no more than 40% larger

than the chip itself.*

• Near Flip Chip Densities without Flip Chips Issues• Packaged Part Robustness without the Size Penalties of a Packaged Part• Supports Standard Pad Configurations, Multi-Sourcing and Lower Costs

The Ultimate in Small Packages

* One of many different definitions for a CSP.


Chip Scale PackagingSize Comparisons

Key Driving Forces Behind CSP:• Footprint Area Reduction (10x)• Package Thickness Reduction (3x)• Package Costs (2x)

Source: OKI

100% 35% 10%

Leaded QFPBGA

CSP


Chip Scale Developments

• Chip scale packaging was developed as a means for assemblers to flip chip attach devices that were designed for wire bond assembly.

• Most off-the-shelf ICs (>>90%) are designed for wire bonding and not for flip chip solder bump attach.

• That means the I/O pads are distributed either on the perimeter of the chip or down the center of the chip.

• The pads are on tight pitches (50 to 100µm) and have Al metallurgy.

• Neither the pad pitch nor metallurgy support flip chip solder bump assembly.


Size & Cost Driven: High Feature Content Portable Electronics• Reduced device footprint: 40 – 80%

• Improved power/ground delivery

• Reduced interconnect losses: 20-40%

• Lower EMI and EMS (for mixed logic, RF, analog)

• Second source capability: CSPs from multiple suppliers are available with common pad-outs, permitting easy second sourcing.

• And most importantly, lower costs!

Driving Forces Behind CSPs


Chip Scale ApplicationsValue/

Complexity

Time LineChip Scale Packaging started out as a portable electronics packaging option for small, less complex chips and then

moved to more complex logic devices were targeted.

Source: T. Di Stefano


Wire Bonded Chip Scale Packages

Bare chips placed on an organic substrate, wire bonded and molded.

• Low investment costs: infrastructure, materials in place on PCB manufacturing lines.

• Low production costs: simple process, low cost material, large PCB panels.

• Small size: small footprint, low height.

• Good electrical performance: better than standard chip carriers


Wire bonded Chip Scale Packaging

Chip Wire Bonded to a Thin, Single-Sided Flex Substrate, Over Molded with

Backside BGA Solder Balls


Chip Scale PackagesWire Bonded on Laminate

Chip Wire Bonded onto a Double-Sided Laminate Substrate, Over Molded with

Back Side Solder BallsSource: ASE


Fine Pitch BGA CSP

Source: NEC

Chip Mounted onto a BT Resin Substrate, Wire Bonded and Molded.

Higher I/O Count Devices Required More Complex and Costly Substrates.

Via Hole

Chip

Wire Bond

Solder Mask

Solder Ball

Circuit TraceBT Resin

Molding Compound


• Wafer Level CSPs Are the Fastest Growing Chip Scale Package Market Segment.

• WLSCPs replace assembly level processing steps and structures with BEOL wafer processing steps and structures.

• There is less handling and less material used and the resulting devices have minimized footprints and thickness’.

Wafer Level Chip Scale Packaging:


Wafer Level CSPs ProcessesVerses Conventional Packages

Wafer Level CSP

Dicing

Wafer

Wafer Packaging

Dicing

QFP, BGA, Conventional CSP

Packaging


WLCSP & WLP Unit Volumes Forecasts

Source: Electronics.CA Publications

WLP MEMS

WLP CMOS Imagers

WLCSP Analog & RF

WLCSP Wireless


WLCSP Market Penetration

Source: Yole

WLCSP Penetration RateInto Overall IC Packaging (in % Units)

WLCSP is the fastest growing packaging technology in the packaging industry today.

2012 20132011201020092008

8.3%7.1%

6.3%6.1%5.4%

4.8%


WLCSP Array Ball Pitch Trends

Source: Yole

2008 2009 2010 2011 2012

0.3 mm0.4 mm

0.5 mm

• I/O pitch reductions require finer/more costly PCBs.• More costly PCB can be off-set by using smaller PCBs.• Finer pitch WLCSP driven by higher I/O chips.


• Bump-on-Pad (BOP) WLCSP processing keeps the pads where they are initially located and changes the pad metallurgy and the pad size to be compatible with solder bumps.

• Redistribution Layer (RDL) WLCSP processing at the BEOL wafer uses an interconnection layer to move the wire bond pads from their initial locations to an array of pads better suited to solder bumps.

Redistribution Layer (RDL) and Bump-on-Pad (BOP) WLCSP Technologies


• RDL and BOP use conventional BEOL wafer fabrication process steps.

• Both dielectric and metal processes, ie. deposition and patterning, are applied to the completed wafer.

• In most devices, the chip wire bond pads are redistributed to an area array of solder pads.

• UBM metallization is applied to the CSP I/O pads prior to the application of solder bumps.

Redistribution Layer (RDL) and Bump-on-Pad (BOP) WLCSP Technologies


• Solder ball attach requires the package I/O pads to have under bump metallization (UBM) such as Ni/Au to obtain a reliable solder joint.

• Solder ball pads must be large enough to support the solder ball, ~ 60% of the ball diameter.

• UBM is applied to expanded chip I/O pads on BOP approaches and on pads formed over the chip passivation on RDL approaches.

• On both BOP and RDL approaches, the chip surface is protected by at least one polymer coating.

Under Bump Metallurgy


• In most fine pitch wire bond devices, pads need to be spread out to increase pad pitch to support solder ball attach.

• Redistribution Layer (RDL) processing moves the chip I/Os from the peripheral (or center row) wire bond pads to an area array of pads.

• This redistribution technique improves chip reliability by providing for larger and more robust solder balls for next level assembly.

Redistribution Layer Processing


• A polymer dielectric such as polyimide or BCB, is applied over the wafer to passivate the surface.• Vias are formed to the chip I/O pads by laser ablation, wet etch or photo-definition.• A metallization layer, usually Cu, Au, or an alloy, is then deposited over this dielectric and onto the pads. • The metal is patterned to form routing traces and array solder pads.• A second dielectric layer is applied to passivate the non-pad metal (traces) and to form the solder mask. • UMB is applied to the array pads.• Additional metal/polymer layers can be added.

Redistribution Layer Processing


Typical Direct Bump or Bump-on-Pad• Bump pad lies directly over wire bond pad.

• Polymer applied to protect die surface.

• Opening made to die I/O pad.

• Metal applied to enlarged pad and provide UBM.

• Second polymer dielectric can be applied.

Solder Bump

Polymer #2Solder Mask

UMBPolymer #1

Passivation

Si WaferAl Pad

27

Deposit and pattern BCB Passivation

Sputter deposit UBM layers (Al/NiV/Cu)

Pattern UBM layers

UBM

WLCSP Bump-on-Pad Process

Single Metal Layer, Single Polymer Dielectric Layer

Attach pre-formed solder spheres

Attach solder sphere by reflow

Source: Flip Chip International ©Ray Fillion 2011


Typical Redistribution Layer Structure• Bump pad lies over chip passivation.• Polymer applied and opened to die I/O pad.• Metal applied and patterned to form redistribution.• Second polymer applied and opened over bump pad.• Second metal is applied and patterned to form bump pad with UBM.

Solder Bump

UMBRDLPolymer #1Passivation

Si WaferAl Pad

Polymer #2Solder Mask


Two Metal Layers, Two Polymer Dielectric Layers

Chip PassivationSiliconChip Wire Bond Pad

Coat, expose, pattern, cure first dielectric layer

Sputter and pattern etch redistribution layer (Ti/Al/Ti) to form routing traces

Coat, expose, pattern, cure second dielectric layer

Sputter deposit and pattern UBM layers (Al/NiV/Cu)

WLCSP Redistribution Process

Source : Flip Chip International


WLCSP Bump-on-Polymer Cross-Section

BGA Pad CuDielectric #1Dielectric #2

Redistribution Metal (Ti/Al/Ti)Chip Pad Chip Passivation

Solder Ball

Source: Flip Chip International

WLCSP Redistribution, Bump-on-Polymer


Redistribution from Perimeter Pads to Area Array Solder Pads

Redistribution Layer Routing Examples


Wafer Level CSP pad redistribution with up to four metal layers for complex, high I/O count chips

Source: Amkor



Cross sectional view of a re-distributed solder bump using three layer BCB/CU

RDL.

Cross sectional view of a re-distributed solder bump

using two layer BCB/CU RDL.

Source: MicroFab


34

64 M DRAM WSCSP68 bumps, 0.8mm pitch

Close-up of Center Pad WLCSP showing solder balls, RDLs and Vias to Center Row Chip Pads

Source: Micron ©Ray Fillion 2011

WLCSP Redistribution, Bump-on-PolymerCenter Pad to Array RDL


Source: Infineon

Source: Oki

Source: ASE

Redistribution WLCSP Examples

Advanced Packaging Technologies: Wafer Level Chip ScalePackagin g

Thank You!Ray Fillion

Fillion [email protected]

518-810-1519

mailto:[email protected]

Wafer Level CSP Overview Fillion 2011

Documents

cross sectional

chip scale

form routing

ball grid

layer bcbcu

chip wire

wire bond

redistribution