-
SSB UPCONVERSION OF QUADRATURE DDS SIGNALS TO THE
800-TO-2500-MHz BAND (page 46)Fundamentals of DSP-Based Control for
AC Machines (page 3)
Transducer/Sensor Excitation and Measurement Techniques (page
33)Complete contents on page 1
Volume 34, 2000
A forum for the exchange of circuits, systems, and software for
real-world signal processing
aPRINTED IN U.S.A.AD341662/01
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About Analog Dialogue
Analog Dialogue is the free technical magazine of Analog
Devices, Inc., published continuouslyfor thirty-four years,
starting in 1967. It discusses products, applications, technology,
andtechniques for analog, digital, and mixed-signal processing.
2000 and 2001 Analog Devices, Inc., all rights reserved
Volume 34, the current issue, incorporates all articles
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www.analog.com/analogdialogue. All recent issues,starting with
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andcan be accessed freely.
Analog Dialogues objectives have always been to inform
engineers, scientists, andelectronic technicians about new ADI
products and technologies, and to help themunderstand and
competently apply our products.
The frequent Web editions have at least three further
objectives:
Provide timely digests that alert readers to upcoming and newly
available products.
Provide a set of links to important and rapidly proliferating
sources of informationand activity fermenting within the ADI
website [www.analog.com].
Listen to reader suggestions and help find sources of aid to
answer their questions.
Thus, Analog Dialogue is more than a magazine: its links and
tendrils to allparts of our website (and some outside sites) make
its bookmark a favoritehigh-pass-filtered point of entry to the
analog.com sitethe virtual world ofAnalog Devices.
Our hope is that readers will think of ADI publications as Great
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Welcome! Read and enjoy!We encourage your feedback*!
Dan [email protected], Analog Dialogue
*Weve included a brief questionnaire in this issue (page 55);
wed be most grateful if youd answer thequestions and fax it back to
us at 781-329-1241.
-
IN THIS ISSUEAnalog Dialogue Volume 34, 2000
Page
Editors Notes: New Fellow, Authors . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Fundamentals of DSP-Based Control for AC Machines . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Embedded Modems Enable Appliances to Communicate with Distant
Hosts via the Internet . . . . . . . . . . 7
Adaptively Canceling Server Fan Noise . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Fan-Speed Control Techniques in PCs . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Finding the Needle in a HaystackMeasuring Small Voltages Amid
Large Common Mode . . . . . . . . . 21
Demystifying Auto-Zero AmplifiersPart 1 . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Demystifying Auto-Zero AmplifiersPart 2 . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Curing Comparator Instability with Hysteresis . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Transducer/Sensor Excitation and Measurement Techniques . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Advances in Video Encoders . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Selecting an Analog Front-End for Imaging Applications . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
True RMS-to-DC Measurements, from Low Frequencies to 2.5 GHz . .
. . . . . . . . . . . . . . . . . . . . . . 45
Single-Sideband Upconversion of Quadrature DDS Signals to the
800-to-2500-MHz Band . . . . . . . . 46
VDSL Technology IssuesAn Overview . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Authors (continued from page 2) . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
Feedback Questionnaire . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Cover: The cover illustration was designed and executed by
Kristine Chmiel-Lafleur, of Communications Services, Analog
Devices, Inc.
-
2 ISSN 01613626 Analog Dialogue Volume 34 Analog Devices, Inc.
2000
Editors NotesEditors NotesWe are pleased to note the
introduc-tion of Dr. David Smart as newFellow at our 2000 General
Techni-cal Conference. Fellow, at AnalogDevices, represents the
highest levelof achievement that a technicalcontributor can
achieve, on a parwith Vice President. The criteriafor promotion to
Fellow are verydemanding. Fellows will haveearned universal respect
and recognition from the technical com-munity for unusual talent
and identifiable innovation at the stateof the art. Their creative
technical contributions in product orprocess technology will have
led to commercial success with amajor impact on the companys net
revenues.
Attributes include roles as mentor, consultant,
entrepreneur,organizational bridge, teacher, and ambassador.
Fellows must alsobe effective leaders and members of teams and in
perceivingcustomer needs. Daves technical abilities,
accomplishments, andpersonal qualities well qualify him to join Bob
Adams (1999),Woody Beckford (1997), Derek Bowers (1991), Paul
Brokaw(1979), Lew Counts (1983), Barrie Gilbert (1979), Roy
Gosser(1998), Bill Hunt (1998), Jody Lapham (1988), Chris
Mangelsdorf(1998), Fred Mapplebeck (1989), Jack Memishian (1980),
DougMercer (1995), Frank Murden (1999), Mohammad Nasser (1993),Wyn
Palmer (1991), Carl Roberts (1992), Paul Ruggerio (1994),Brad
Scharf (1993), Jake Steigerwald (1999), Mike Timko (1982),Bob Tsang
(1988), Mike Tuthill (1988), Jim Wilson (1993), andScott Wurcer
(1996) as Fellow.
NEW FELLOWDave Smart is the chief technolo-gist behind ADICE,
our highlysuccessful analog and mixed-signalcircuit simulator,
which is widelyused by chip designers in AnalogDevices. Dave joined
ADI in 1988,assuming responsibility for ADICE.He made numerous
contributions tothe robustness, accuracy, and featuresof the
simulator, winning the praiseof Analog Devices demanding analog IC
designers. To meet thechallenges of designing large mixed-signal
chips in the 1990s, Daveled a small team in the development and
deployment of a com-pletely new version of ADICE with innovative
techniques for theeffective simulation of mixed-signal circuits
using mixed levels ofmodeling abstraction. He is currently working
on tools and meth-ods for the design of RF and high-speed ICs. The
work of Dave andhis team has been a key element of the design of
nearly every ana-log and mixed-signal product developed by Analog
Devices in thepast decade.
Dave developed an interest in analog circuits as a teenager
growingup in Skokie, Illinois. Before receiving any formal
education inelectronics, he and a friend designed and built an
audio mixingboard for their high school auditorium to be used in
theatricalproductions. While pursuing his study of circuits as an
undergraduateat the University of Illinois at Urbana-Champaign in
the early 1970s,he became aware of the power of digital computers
and imaginedtheir use to take some of the tedium and guesswork out
of circuit
design. Once he met Professor Tim Trick, who was active in
thefield of computer-aided design of circuits, Daves career
directionwas set. After receiving BS and MS degrees from the
University ofIllinois, he worked on circuit simulation at GTE
CommunicationSystems for seven years. He returned to the University
of Illinois,researching parallel algorithms for circuit simulation
with ProfessorTrick, and he obtained his PhD degree prior to
joining ADI in 1988.
THE AUTHORSRick Blessington (page 7) rejoinedADI as a Business
DevelopmentManager in April of 1999, after 15years in the sales and
marketing ofcommunication products for majorelectronics companies.
At present,he is involved in development ofinventive new products
under acontract collaboration betweenSierra Telecom (So. Lake
Tahoe) andAnalog Devices. Rick holds BA and MA degrees in
Technologyfrom California State University at Long Beach. In the
early yearsof his career, Rick taught electronics in Southern
California. Heand his family now live in Walpole, MA; his hobbies
include sailingand skiing.
Kevin Buckley (page 40) is a SeniorApplications Engineer in the
High-Speed Converter Division, inWilmington, MA, working on
analogfront ends for imaging applications.He joined Analog Devices
in 1990 asa technician for the MicroelectronicsDivision and
received a BSEE in1997 from Merrimack College,North Andover, MA. In
his sparetime he plays hockey and soccer, coaches his sons soccer
team, andenjoys chasing his baby daughter around the house.
Paschal Minogue (page 10) is theEngineering Manager of the
DigitalAudio Group in Limerick, Ireland.He graduated from
UniversityCollege Dublin, with a B.E.Electronic Engineering degree
(FirstClass Honors) and joined theDesign Department at
AnalogDevices in Limerick, Ireland, in1981. Since then, he has
worked onstandard converters, noise cancellation, communication
products,and most recently audio-band and voice-band products.
Reza Moghimi (page 28) is anApplications Engineer for
thePrecision Amplifier product line inSanta Clara, CA. He is
responsiblefor amplifiers, comparators,temperature sensors, and the
SSMaudio product line. He holds a BSfrom San Jose State University
andan MBA from National University(Sunnyvale, CA). His
leisureinterests include playing soccer andtraveling with his
family. [more authors on Page 53]
-
Fundamentals ofDSP-Based Controlfor AC Machinesby Finbarr
Moynihan,Embedded Control Systems Group
INTRODUCTIONHigh-performance servomotors are characterized by
the need forsmooth rotation down to stall, full control of torque
at stall, andfast accelerations and decelerations. In the past,
variable-speeddrives employed predominantly dc motors because of
theirexcellent controllability. However, modern
high-performancemotor drive systems are usually based on
three-phase ac motors,such as the ac induction motor (ACIM) or the
permanent-magnetsynchronous motor (PMSM). These machines have
supplantedthe dc motor as the machine of choice for demanding
servomotorapplications because of their simple robust construction,
lowinertia, high output-power-to-weight ratios, and good
performanceat high speeds of rotation.
The principles of vector control are now well established
forcontrolling these ac motors; and most modern
high-performancedrives now implement digital closed-loop current
control. In suchsystems, the achievable closed-loop bandwidths are
directly relatedto the rate at which the computationally intensive
vector-controlalgorithms and associated vector rotations can be
implemented inreal time. Because of this computational burden, many
high-performance drives now use digital signal processors (DSPs)
toimplement the embedded motor- and vector-control schemes.
Theinherent computational power of the DSP permits very fast
cycletimes and closed-loop current control bandwidths (between 2
and4 kHz) to be achieved.
The complete current control scheme for these machines
alsorequires a high-precision pulsewidth modulation (PWM)
voltage-generation scheme and high-resolution analog-to-digital
(A/D)conversion (ADC) for measurement of the motor currents. In
orderto maintain smooth control of torque down to zero speed,
rotorposition feedback is essential for modern vector
controllers.Therefore, many systems include rotor-position
transducers, suchas resolvers and incremental encoders. We describe
here thefundamental principles behind the implementation of
high-performance controllers (such as the ADMC401) for
three-phaseac motorscombining an integrated DSP controller, with
apowerful DSP core, flexible PWM generation, high-resolutionA/D
conversion, and an embedded encoder interface.
VARIABLE SPEED CONTROL OF AC MACHINESEfficient variable-speed
control of three-phase ac machines requiresthe generation of a
balanced three-phase set of variable voltageswith variable
frequency. The variable-frequency supply is typicallyproduced by
conversion from dc using power-semiconductordevices (typically
MOSFETs or IGBTs) as solid-state switches. Acommonly-used converter
configuration is shown in Figure 1a. It
is a two-stage circuit, in which the fixed-frequency 50- or
60-Hzac supply is first rectified to provide the dc link voltage,
VD, storedin the dc link capacitor. This voltage is then supplied
to an invertercircuit that generates the variable-frequency ac
power for the motor.The power switches in the inverter circuit
permit the motorterminals to be connected to either VD or ground.
This mode ofoperation gives high efficiency because, ideally, the
switch has zeroloss in both the open and closed positions.
By rapid sequential opening and closing of the six switches
(Figure1a), a three-phase ac voltage with an average sinusoidal
waveformcan be synthesized at the output terminals. The actual
outputvoltage waveform is a pulsewidth modulated (PWM)
high-frequency waveform, as shown in Figure 1b. In practical
invertercircuits using solid-state switches, high-speed switching
of about20 kHz is possible, and sophisticated PWM waveforms can
begenerated with all voltage harmonic components at very
highfrequencies; well above the desired fundamental
frequenciesnominally in the range of 0 Hz to 250 Hz.
The inductive reactance of the motor increases with frequency
sothat the higher-order harmonic currents are very small, and
near-sinusoidal currents flow in the stator windings. The
fundamentalvoltage and output frequency of the inverter, as
indicated in Figure1b, are adjusted by changing the PWM waveform
using anappropriate controller. When controlling the fundamental
outputvoltage, the PWM process inevitably modifies the harmonic
contentof the output voltage waveform. A proper choice of
modulationstrategy can minimize these harmonic voltages and their
associatedharmonic effects and high-frequency losses in the
motor.
MA B C
N
VD
RECTIFIER INVERTER
THREE-PHASE
60HzMAINS
a. Typical configuration of power converter used to drive
three-phase ac motors.
DESIRED FREQUENCY
DESIREDAMPLITUDE
FUNDAMENTALMOTORPHASE
VOLTAGE
VAB
VAN
VBN
b. Typical PWM waveforms in the generation of a
variable-voltage, variable-frequency supply for the motor.
Figure 1.
Analog Dialogue 34-6 (2000) 3
-
PULSEWIDTH MODULATION (PWM) GENERATIONIn typical ac
motor-controller design, both hardware and softwareconsiderations
are involved in the process of generating the PWMsignals that are
ultimately used to turn on or off the power devicesin the
three-phase inverter. In typical digital control environments,the
controller generates a regularly timed interrupt at the
PWMswitching frequency (nominally 10 kHz to 20 kHz). In the
interruptservice routine, the controller software computes new
duty-cyclevalues for the PWM signals used to drive each of the
three legs ofthe inverter. The computed duty cycles depend on both
themeasured state of the motor (torque and speed) and the
desiredoperating state. The duty cycles are adjusted on a
cycle-by-cyclebasis in order to make the actual operating state of
the motor followthe desired trajectory.
Once the desired duty cycle values have been computed by
theprocessor, a dedicated hardware PWM generator is needed toensure
that the PWM signals are produced over the next PWM-and-controller
cycle. The PWM generation unit typically consistsof an appropriate
number of timers and comparators that arecapable of producing very
accurately timed signals. Typically, 10-to-12 bit performance in
the generation of the PWM timingwaveforms is desirable. The PWM
generation unit of the ADMC401is capable of an edge resolution of
38.5 ns, corresponding toapproximately 11.3 bits of resolution at a
switching frequency of10 kHz. Typical PWM signals produced by the
dedicated PWMgeneration unit of the ADMC401 are shown in Figure 2,
forinverter leg A. In the figure, AH is the signal used to drive
thehigh-side power device of inverter leg A, and AL is used to
drivethe low-side power device. The duty cycle effectively adjusts
theaverage voltage applied to the motor on a cycle-by-cycle basis
toachieve the desired control objective.
In general, there is a small delay required between turning off
onepower device (say AL) and turning on the complementary
powerdevice (AH). This dead-time is required to ensure the device
beingturned off has sufficient time to regain its blocking
capability beforethe other device is turned on. Otherwise a short
circuit of the dcvoltage could result. The PWM generation unit of
the ADMC401contains the necessary hardware for automatic dead-time
insertioninto the PWM signals.
CONTROLLERINTERRUPTS
CONTROL PERIODN
TIMEs
AH
ALDUTY CYCLE, D1 DUTY CYCLE, D2 DUTY CYCLE, D3
50 100 150 200
CONTROL PERIODN+1
CONTROL PERIODN+2
Figure 2. Typical PWM waveforms for a single inverter leg.
General Structure of a Three-Phase AC Motor ControllerAccurate
control of any motor-drive process may ultimately bereduced to the
problem of accurate control of both the torque andspeed of the
motor. In general, motor speed is controlled directlyby measuring
the motors speed or position using appropriatetransducers, and
torque is controlled indirectly by suitable controlof the motor
phase currents. Figure 3 shows a block diagram of atypical
synchronous frame-current controller for a three-phase
motor. The figure also shows the proportioning of tasks
betweensoftware code modules and the dedicated
motor-controlperipherals of a motor controller such as the ADMC401.
Thecontroller consists of two
proportional-plus-integral-plus-differential (PID) current
regulators that are used to controlthe motor current vector in a
reference frame that rotatessynchronously with the measured rotor
position.
Sometimes it may be desirable to implement a decoupling
betweenvoltage and speed that removes the speed dependencies
andassociated axes cross coupling from the control loop. The
referencevoltage components are then synthesized on the inverter
using asuitable pulsewidth-modulation strategy, such as space
vectormodulation (SVM). It is also possible to incorporate
somecompensation schemes to overcome the distorting effects of
theinverter switching dead time, finite inverter device on-state
voltagesand dc-link voltage ripple.
The two components of the stator current vector are known as
thedirect-axis and quadrature-axis components. The direct-axis
currentcontrols the motor flux and is usually controlled to be zero
withpermanent-magnet machines. The motor torque may then
becontrolled directly by regulation of the quadrature axis
component.Fast, accurate torque control is essential for
high-performancedrives in order to ensure rapid acceleration and
decelerationand smooth rotation down to zero speed under all load
conditions.
The actual direct and quadrature current components are
obtainedby first measuring the motor phase currents with suitable
current-sensing transducers and converting them to digital, using
an on-chipADC system. It is usually sufficient to simultaneously
sample justtwo of the motor line currents: since the sum of the
three currentsis zero, the third current can, when necessary, be
deduced fromsimultaneous measurements of the other two
currents.
The controller software makes use of mathematical
vectortransformations, known as Park Transformations, that ensure
thatthe three-phase set of currents applied to the motor is
synchronizedto the actual rotation of the motor shaft, under all
operatingconditions. This synchronism ensures that the motor
alwaysproduces the optimal torque per ampere, i.e., operates at
optimalefficiency. The vector rotations require real-time
calculation of thesine and cosine of the measured rotor angle, plus
a number ofmultiply-and-accumulate operations. The overall
control-loopbandwidth depends on the speed of implementation of the
closed-loop control calculationsand the resulting computation of
newduty-cycle values. The inherent fast computational capability
ofthe 26-MIPS, 16-bit fixed-point DSP core makes it the
idealcomputational engine for these embedded
motor-controlapplications.
ANALOG-TO-DIGITAL CONVERSION REQUIREMENTSFor control of
high-performance ac servo-drives, fast, high-accuracy,
simultaneous-sampling A/D conversion of the measuredcurrent values
is required. Servo drives have a rated operationrangea certain
power level that they can sustain continuously,with an acceptable
temperature rise in the motor and powerconverter. Servo drives also
have a peak ratingthe ability to handlea current far in excess of
the rated current for short periods oftime. It is possible, for
example, to apply up to six times the rated
4 Analog Dialogue 34-6 (2000)
-
current for short bursts of time. This allows a large torque to
beapplied transiently, to accelerate or decelerate the drive very
quickly,then to revert to the continuous range for normal
operation. Thisalso means that in the normal operating mode of the
drive, only asmall percentage of the total input range is being
used.
At the other end of the scale, in order to achieve the smooth
andaccurate rotations desired in these machines, it is wise
tocompensate for small offsets and nonlinearities. In any
current-sensor electronics, the analog signal processing is often
subject togain and offset errors. Gain mismatches, for example, can
existbetween the current-measuring systems for different
windings.These effects combine to produce undesirable oscillations
in thetorque. To meet both of these conflicting resolution
requirements,modern servo drives use 12-to-14-bit A/D converters,
dependingon the cost/performance trade-off required by the
application.
The bandwidth of the system is essentially limited by the
amountof time it takes to input information and then perform
thecalculations. A/D converters that take many microseconds
toconvert can produce intolerable delays in the system. A delay in
aclosed-loop system will degrade the achievable bandwidth of
thesystem, and bandwidth is one of the most important figures
ofmerit in these high-performance drives. Therefore, fast
analog-to-digital conversion is a necessity for these
applications.
A third important characteristic of the A/D converter used in
theseapplications is timing. In addition to high resolution and
fastconversion, simultaneous sampling is needed. In any
three-phasemotor, its necessary to measure the currents in the
three windingsof the motor at exactly the same time in order to get
an instantaneoussnapshot of the torque in the machine. Any time
skew (timedelay between the measurements of the different currents)
is an
error factor thats artificially inserted by the means of
measurement.Such a non-ideality translates directly into a ripple
of the torquea very undesirable characteristic.
The ADC system that is integrated into the ADMC401 provides
afast (6-MSPS), high-resolution (12-bit) ADC core integrated
withdual sample-and-hold amplifiers so that two input signals may
besampled simultaneously. (As noted earlier, this allows
thesimultaneous value of the third current to be calculated.) The
ADCcore is a high-speed pipeline flash architecture. A total of
eightanalog input channels may be converted, accepting
additionalsystem or feedback signals for use as part of the control
algorithm.This level of integrated performance represents the
state-of-the-art in embedded DSP motor controllers for
high-performanceapplications.
POSITION SENSING AND ENCODER INTERFACE UNITSUsually the motor
position is measured through the use of anencoder mounted on the
rotor shaft. The incremental encoderproduces a pair of quadrature
outputs (A and B), each with alarge number of pulses per revolution
of the motor shaft. For atypical encoder with 1024 lines, both
signals produce 1024 pulsesper revolution. Using a dedicated
quadrature counter, it is possibleto count both the rising and
falling edges of both the A and Bsignals so that one revolution of
the rotor shaft may be dividedinto 4096 different values. In other
words, a 1024-line encoderallows the measurement of rotor position
to 12-bit resolution. Thedirection of rotation may also be inferred
from the relative phasingof quadrature signals A and B.
It is usual to have a dedicated encoder interface unit (EIU) on
themotor controller; it manages the conversion of the dual
quadrature
DSP SOFTWAREMOTOR CONTROL
PERIPHERALS
PWMOUTPUTS
MOTORCURRENTFEEDBACK
ENCODERFEEDBACKSIGNALS
FWMGENERATION
UNIT
ADCSYSTEM
ENCODERINTERFACE
UNIT
ROTORPOSITION, e
3>2TRANSFORM
PARK
NON-IDEALITY
CORRECTIONVOLTAGE
DECOUPLING
PID
PARK SVM
PID
jee
I*QS
I*DS
d
dt
+
+
jee
Figure 3. Configuration of typical control system for
three-phase ac motor.
Analog Dialogue 34-6 (2000) 5
-
encoder output signals to produce a parallel digital word
thatrepresents the actual rotor position at all times. In this way,
theDSP control software can simply read the actual rotor
positionwhenever it is needed by the algorithm.
This is all very well, but there is an increasing class of
cost-sensitiveservo-motor drive applications with lower performance
demandsthat can afford neither the cost nor the space requirements
of therotor position transducer. In these cases, the same motor
controlalgorithms can be implemented with estimated rather
thanmeasured rotor position.
The DSP core is quite capable of computing rotor position
usingsophisticated rotor-position estimation algorithms, such
asextended Kalman estimators that extract estimates of the
rotorposition from measurements of the motor voltages and
currents.These estimators rely on the real-time computation of a
sufficientlyaccurate model of the motor in the DSP. In general,
these sensor-less algorithms can be made to work as well as the
sensor-basedalgorithms at medium-to-high speeds of rotation. But as
the speedof the motor decreases, the extraction of reliable
speed-dependentinformation from voltage and current measurements
becomes moredifficult. In general, sensorless motor control is
applicable
principally to applications such as compressors, fans, and
pumps,where continuous operation at zero or low speeds is not
required.
ConclusionsModern DSP-based control of three-phase ac motors
continuesto flourish in the market place, both in established
industrialautomation markets and in newer emerging markets in the
homeappliance, office automation and automotive markets.
Efficientand cost-effective control of these machines requires an
appropriatebalance between hardware and software, so that
time-critical taskssuch as the generation of PWM signals or the
real-time interfaceto rotor position transducers are managed by
dedicated hardwareunits. On the other hand, the overall control
algorithm andcomputation of new voltage commands for the motor are
besthandled in software using the fast computational capability of
aDSP core. Implementing the control solution in software bringsall
the advantages of easy upgrading, repeatability,
andmaintainability, when compared with older hardware solutions.All
motor-control solutions also require the integration of a
suitableA/D conversion system for fast and accurate measurement of
thefeedback information from the motor. The resolution,
conversionspeed, and input sampling structure of the ADC system
need tobe strictly targeted to the requirements of specific
applications.
b
6 Analog Dialogue 34-6 (2000)
Mixed-Signal Motor Control Signal Chain
DSP CAREADSP-21xx
MEMORYBLOCK
PROGRAMMABLEI/O
ENCODERINTERFACE
PWM
VREF
ADC
OTHERPERIPHERALS
RESOLVER-TO-DIGITALCONVERTER
OSCILLATOR
INTERFACER5-232, R5-485
COMPUTERHOST
SPEED/DIRECTION/POSITIONCOMMAND
E R
MOTORPOWERSTAGE
MOTOR CURRENTFEEDBACK
ENCODER ORRESOLVERFEEDBACK
BUFFER
ADMC300/ADMC330 SINGLE CHIP MOTOR CONTROL IC
NOTE:SELECT THE BLUE SIGNAL CHAINSM BLOCKS OR THEBLUE TEXT TO
SEE A LISTING OF AVAILABLE PRODUCTS.
Using Mixed-Signal Motor Control ICs
-
Embedded ModemsEnable Appliancesto Communicate withDistant Hosts
via theInternetby Rick BlessingtonSoftware & Systems Technology
Division*
INTRODUCTIONTodays smart appliances do much more than shut off
the dryerwhen the clothes are dry or display a new photograph when
onehas been shot. For example: they provide status
informationindicating when a vending machine needs to be filled or
a dropbox emptied; they run remote diagnostics when needed,
andautomatically upgrade their settings and download
softwareupgrades to stay current; they schedule and request
maintenanceto avoid malfunctions; they add intelligence to the
appliances thatharbor them.
Any equipment that does not require an embedded PC, but relieson
data or fax to communicate with a remote host, is likely torequire
an embedded modem. Internet appliances designed solelyto provide
information via email or the Web need embeddedmodems to provide the
communications link to the Internet. Set-top boxes for interactive
cable and satellite television requireembedded modems to
communicate billing information,interactive programming,
pay-per-view, and home shopping orders.Appliances and handheld
computers (or PDAs) become muchmore useful when they can link to
remote hosts.
The Handspring Visor, for example, can maintain schedules
andcalendars, contact lists and telephone directories, expense logs
andtime sheets, stock portfolios, and sports team statistics. To
becompletely useful, however, the information must be both
currentand identical to the information in the users computer,
companydatabase, and administrative assistants office tools and
paper files.With its Springboard modem, from card access, which
uses anAnalog Devices embedded modem chipset, the Visor can
beconnected to a telephone line and automatically update both
itselfand its users host computer. In this way, the Visor becomes
theaccurate, timely, and functional information appliance its
usersneed. Its embedded modem makes all of these capabilities
possibleby linking it to a remote host without loading the PDA,
because ofthe Analog Devices DSP used in the embedded modem.
The Visor required its modem to have low power, small size,
highreliability, standalone form factor, and ease of Internet
interfacing.The resulting Springboard modem fits entirely inside
the Visorpackage, operates from the Visors existing batteries
withoutsignificantly shortening their life, and automatically
connects to
the Internet when connected to a telephone line. It makes
theVisor an extension of its users computer network.
Embedded Modem ComponentsEmbedded modems contain a data pump,
DAA (data accessarrangement), and modem code. They may or may not
include acontroller, Internet protocol stack, and SDRAM. The number
ofchips depends on the application requirements, including the
needfor any additional functions. They connect to telephone lines,
andinclude all the necessary hardware and software.
A data pump includes a processor (DSP) that translates data to
astandard protocol (fax or Internet), at a specific bit rate, such
asV.32, V.34, V.90, employing modem code. A DAA provides
thephysical and software interface to a POTS (plain old
telephoneservice) line. A silicon DAA performs this function
without externalcodecs, relays, optocouplers, and transformers. An
Internet protocol(IP) stack implements the Internet protocols (such
as PPP, TCP,HTTP, POP3, FTP, etc.) on the modems DSP. This permits
filedownloads, standard Web-page hosting, and email capability
forthe device to which the modem is connected without the use of a
PC,microcontroller, or other processor. Thus the DSP executes both
themodem code and the IP stack.
Modem Architecture Trade-OffsEmbedded modems may be either
controller-based (parallel) oroperate without a controller. In both
cases they need a fixed-pointDSP data pump and DAA. The modem code
can either run onthe DSP data pump, or on a Pentium or RISC
processor (forhost-based or software modems), or on a
multifunctionprogrammable DSP (such as an ADSP-218x). For
comparison,modem architectures may be divided into two host-based
classes(with and without on-board processing), and two standalone
classes(microcontroller- and DSP-based). Their characteristics
andadvantages/disadvantages are compared in Table I.
The controller-based designs work without hosts, so they dont
careabout operating systems or whether the host has crashed.
Thisstandalone approach assures greater redundancy, since the
modemoperates independently of the host computer and its
operatingsystem. Their downside is they need a microcontroller and
itsmemory, as well as DSP memory, to run the supervisory code.This
entails additional parts count, real estate and power,
andconsequently added cost and risk. Also, their modem software
isusually hard-coded and consequently not upgradeable.
MICRO-CONTROLLER DATA PUMP DAA
MEMORY SRAM
MODULATIONCODE
SUPERVISORYCODE
TELCODTE
Figure 1. Controller-based modem.
Analog Dialogue 34-7 (2000) 7
*For more details, contact [email protected]
[email protected].
-
Controllerless (software-controlled, or win-) modems, offer
lower cost,real estate, and power since the memory resides on the
PC and nomicrocontroller (nor memory for it) is needed. However,
theyrequire a PC to run the supervisory code, so these winmodemsare
heavily dependent on the PC operating system. Consequently,uptime
of the PC host is important to their operation, and theyare
affected by the typical PC install/support issues. Theirperformance
suffers when the host is heavily loaded with otherjobs. They still
require a data pump with memory. Code upgradesand diagnostics are
dependent on the reliability of the PC host,with no redundancy.
Software upgrades are limited by the modemsfixed amount of
memory.
PERSONALCOMPUTER DATA PUMP DAA
DRAM
SRAM
MODULATIONSUPERVISORY
TELCO
ISOLATION
Figure 2. Controllerless modem (ISA and PCI).
Software, host-based or soft-modems operate without a DSP
ormicrocontroller, since their supervisory and data pump code
runson the PC host. This approach has been promoted by PC
processormanufacturers to take advantage of the free unused MIPS
ofthe increasingly more powerful host processors, since the
modemsdo not significantly load the host, but at the same time they
helpjustify the need to upgrade to it. These modems are very low
costbecause they use the existing host. On the other hand, if the
costof upgrading to a sufficiently fast host to handle the
modemfunctions is taken into consideration, the result will far
surpassthe cost of either a controller-based or controllerless
design. Host-based modems are also heavily dependent on their hosts
reliability,as well as concurrency issues encountered when running
manyoperations simultaneously. In addition, this approach
typicallylimits the modem to communicating only Windows and
Pentiumapplications, limiting the free MIPS (millions of
instructionsper second) on the host to particular functions. The
power drain
and cost-per-MIPS for a Pentium is much higher than for a
DSP-based design, so the power used by the board must be taken
intoaccount, even if the cost is not. The cost of modem IP must
still bepaid, so the concept of free is not accurate.
A multifunction DSP-based embedded modem incorporates
aprogrammable DSP, such as an ADSP-218x. By integrating
thecontroller, memory, and data pump on a single chip, real
estate(board space), cost, and power are reduced. No
separatemicrocontroller or associated memory is required. A
software-basedUART is used, further reducing the hardware cost,
real estate,and power. The standalone design operates independently
of thehost and operating system, offering redundancy and
remotesoftware upgradeability via the included FLASH memory.
Thecodec adds international capabilities, accommodating
country-specific parameters. Three modulation speeds are possible,
eachusing the same components but a different Internet protocol
(IP):up to 14.4 kbps, up to 33.6 kbps and up to 56 kbps.
The Analog Devices programmable DSP-based embeddedmodems capture
the advantages of all the above approaches withfew of their
disadvantages. Even as PC prices fall while host PCperformance
increases, embedded DSP MIPS will always remainless expensive, more
reliable, and independent of host processing.
ADDST218x
SILICON DAA
SOFTWAREBY
TELINDUS
FLASH(OR SYSTEM)
MEMORY
RJ11TELCO
RS232/TTLSERIAL OR
IDMAPARALLEL
DIGITALISOLATION
SIDE
LINESIDE
PROGRAMSRAM
DATASRAM
Figure 3. Multifunction DSP-based modem.
All of the alternatives, except the host-based design, have
thedisadvantage of facing competition with continuing PC host
priceerosion. As the PC host price decreases relative to that of
the stand-alone modem, host-based modems become more cost
effective. Thetrade-off between redundancy and cost, however, will
continue.
Table I. Modem Architecture Overview
Type Controller-Based ControllerlessSerial
MultifunctionTrade-Offs (+ and ) Parallel (or Winmodem)
SoftwareHost-Based ProgrammableDSP-Based
Requires Host No Yes Yes No
Redundancy Best. Stays alive None. Relies on host. None. Relies
on host. Best. Stays alive when hostwhen host crashes. crashes.
Upgradeability None Depends on host. Least Best
Cost Most Moderate Lowest Moderate
Downside(s) Needs microcontroller Needs host to run Requires
more power. Ongoing price competitionwith memory to run supervisory
code. Data Limited to Pentium and with host-PC pricing
erosion.supervisory code. pump still needs memory. Windows
applications.
Uniqueness Operating-system Memory resides on Software only. No
host or operating systemneutral host. Supervisory code and
dependencies. Integrated
DSP runs on host. controller and data pump.
8 Analog Dialogue 34-7 (2000)
-
DAA ApproachesThe DAA (data access arrangement) supports
country-specificCall Progress and Caller ID, which must be
specified for eachcountry. Different DAA components are available
to supportworldwide operation of a subset of countries. The DAA
handlesTIP and RING telephone connectionsand includes a secondcodec
for nonpowered lines, such as leased lines and wireless.Multiple
DAAs can be supported by a single DSP for use in multi-line
applications.
The state-of-the-art international silicon DAA with integral
codeceliminates the cost and real estate of transformers,
optoisolators,relays, and hybrids. All of this is replaced with two
small TSSOPpackages that directly connect to the DSP, improving
reliabilityand manufacturing ease while decreasing real estate and
cost. Thedesign improves performance, since the signals are
digitallytransmitted over the isolation barrier. The silicon DAA
includesinternational support in a single design and supports both
U.S.and international caller ID without relays, via
softwareprogrammability, for different countries. No hardware
modificationis required. Advanced power management, caller ID, and
sleep modesave power and offer green compliance, enabling a smaller
powersupply and longer battery life. Monitor output and
microphoneinput support voice and handset applications.
Each modem design also supports legacy DAAs used for
unpoweredtelephone line applications, such as wireless and leased
lines.
Software DevelopmentAnalog Devices embedded modems include modem
codesupplied by Telindus. Product-specific software can be
obtainedfrom modem partners of Analog Devices. For example, one
canautomatically link the Handspring Visor to the Internet by
addinga Springboard modem from Card Access. One can enable aLavazza
e-espressopoint coffee machine to send and receiveemails (to
trigger maintenance checks and restocking visits, anddisplay
weather or traffic reports) by adding an Internet modemfrom Analog
Devices that executes a TCP/IP stack from eDevice.
Modem Reference DesignsThe Analog Devices embedded modem
development platformincludes an ADSP-218x programmable DSP and a
silicon DAA.It consumes under 200 mW maximum power at 3.3 V. No
customer
code is required. The development platform includes
modemsoftware from ISO 9001-certified Analog Devices
technologypartner Telindus. The board comes with connectors for
EZ-ICE,JTAG, and RS-232 I/O for modification and testing of the
ATcommand set and S registers.
Embedded Modem ApplicationsThe products that use embedded modems
for communicationinclude vending machines (which can communicate
levels ofinventory and when they need to be filled), kiosks, POS
terminals,security and surveillance systems, games, and drop boxes
that cancommunicate when they have shipments to be picked up. The
waysin which the basic product communicates via these
standalonemodems are established by programming in relevant web
contentand communication data. The results for designers are
productswith such characteristics as built-in investment
protection,appliances that know and communicate when they need to
beserviced, fixed, filled, emptied, updated, or picked up.
Productsthat use the Internet to provide customer information
andcommunications can be located wherever needed.
Industrialequipment can indicate when it needs to be serviced.
Refrigeratorscan display recipes containing only the ingredients on
their shelves.
Standalone embedded modems can reduce operating costs at thesame
time that they make possible new product categories withfeatures to
spur new sales. With new Internet-enabled power, theseproducts can
create new opportunities for e-commerce, e-service,and
e-information vendors.
Standalone embedded modems offer complete and flexible
designalternatives for worldwide communications in a variety
ofapproaches. Each approach can be configured on as few as
threechips, offers a choice of speeds, and can be
implementedinexpensively with low power and real estate
requirements.Embedded modems can bring the power of Internet
informationand communications to both new and installed devices and
can addautomatic software upgrades and remote diagnostics at the
same time.
For Further InformationFor additional help, contact
[email protected], orvisit Analog Devices Software &
Systems Technologies on the Web.Or contact Analog Devices modem
partners: Card Accessand eDevice. b
TOP VIEW
BOTTOM VIEW
ONLY1 INCH!
ONLY 2 1/2 INCHES!
RS-232TRANSCEIVER
FLASHTTL LED DRIVER
DSP
DAA
ISOLATION
Figure 4. V.90 standalone embedded modem reference design.
Analog Dialogue 34-7 (2000) 9
-
Adaptively CancelingServer Fan NoisePrinciples and Experiments
witha Short Duct and the AD73522dspConverterby Paschal Minogue,
Neil Rankin, Jim Ryan
INTRODUCTIONIn the past, when one thought of noise in the
workplace, heavyindustrial noise usually came to mind. Excessive
noise of that typecan be damaging to the health of the worker.
Today, at a muchlower level, though not as severe a health hazard
in ofceenvironments, noise from equipment such as personal
computers,workstations, servers, printers, fax machines, etc., can
bedistracting, impairing performance and productivity. In the
caseof personal computers, workstations and servers, the noise
usuallyemanates from the disk drive and the cooling fans.
This article is about the problem of noise from server cooling
fans,but the principles can be applied to other applications with
similarfeatures. Noise from server cooling fans can be annoying,
especiallywhen the server is located near the user. Usually,
greater servercomputing power means higher power dissipation,
calling forbigger/faster fans, which produce louder fan noise. With
effectivefan noise cancellation, bigger cooling fans could be used,
permittingmore power dissipation and a greater concentration of
computerpower in a given area.
DESCRIPTION OF PROBLEMTypically, server cooling-fan noise has
both a random and arepetitive component. A spectrum plot of the fan
noise of the DellPoweredge 2200 server illustrates this (Figure 1).
Also, the proleof the fan noise can change with time and
conditions; for example,an obstruction close to the fan will affect
its speed and thus thenoise that it generates.
0
700 10
AM
PLIT
UDE
dB
FREQUENCY kHz
Figure 1. Profile of server fan noise.
ONE SOLUTIONOne solution is to conne the propagation of much of
the fannoise to a duct, and then use active noise control (ANC) to
reducethe strength of the fan noise leaving the duct [1].
A block diagram of a basic ANC system as applied to
noisepropagating inside a duct is illustrated in Figure 2. The
noisepropagating down the duct is sampled by the upstream
referencemicrophone and adaptively altered in the electronic
feed-forwardpath to produce the antinoise to minimize the acoustic
energy atthe downstream error microphone. However, the antinoise
canalso propagate upstream and can disrupt the action of the
adaptivefeedforward path, especially if the speaker is near the
referencemicrophone (as is always the case in a short duct). To
counteractthis, electronic feedback is used to neutralize the
acoustic feedback.This neutralization path is normally determined
off-line, in theabsence of the primary disturbance, and then xed
when theprimary noise source is present. This is done because the
primarynoise is highly correlated with the antinoise.
There are many problems associated with short-duct
noisecancellation [2, 3, 4]. Acoustic feedback from antinoise
speaker toreference microphone is more pronounced; the number of
acousticmodes increases exponentially; duct resonances can
causeharmonic distortion; and the group delay through the
analog-to-digital converters, processing unit, and
digital-to-analog converterscan become signicant [5]. This paper
concentrates on the latterproblem in particular.
PROGRAMMABLEFIR
(FEEDFORWARD)
LMSUPDATE
ALGORITHM
FIXEDFIR
(FEEDBACK)
DUCT
ERRORMICROPHONE
REFERENCEMICROPHONE
ANTINOISESPEAKER
+
Figure 2. Basic duct ANC system.
THE IMPORTANCE OF GROUP DELAYTo provide an unobtrusive and
viable solution in terms of size andcost, the smaller the duct is
made the better; ideally, it should tinside the server boxwhich
would result in a very short acousticpath. To maintain causal
relationships, the delay through the entire(mostly electronic)
feedforward path has to be less than or equalto the delay in the
forward acoustic path if broadband primarynoise is to be
successfully cancelled.
ff ap (1)
where ff is the delay through the feedforward path and ap is
theprimary acoustic delay.
In cases where the secondary speaker is recessed into its own
shortduct, the feedforward path will also include the acoustic
delaythrough this secondary duct.
ff = e + as (2)
where e is the electronic part of the feedforward path and as
isthe acoustic delay in the secondary duct.
10 Analog Dialogue 34-2 (2000)
-
The electronic delay in the feedforward path consists of
groupdelay through the microphone, anti-aliasing lter and
A/Dconverter (ADC); processing delay (+ digital lter group delay)
inthe DSP; group delay through the D/A converter (DAC) and
anti-imaging lter; and nally the delay through the secondary
speaker.
e = mic + adc + dsp + dac + spkr (3)Therefore, from
causality:
mic + adc + dsp + dac + spkr + as ap (4)To minimize ap, and
thereby the length of the duct, ff (and all itsvarious components)
should be made as small as possible. Letsassume that delays through
the microphone, speaker and secondaryduct path have already been
minimized. Then, the remainingquantity to be minimized is adc + dsp
+ dac.adc can be minimized by using an oversampled ADC with
lowgroup-delay-decimation ltering; dsp can be minimized by usinga
DSP with sufciently high-MIPS and an efcient instructionset; dac
can be minimized by using an oversampled DAC withinterpolation
ltering having low group delay. The latter shouldbe capable of
being bypassed to further minimize the group delay.
Furthermore, the processor should use the most recent ADCsample
as soon as it becomes available, and the DAC should usethe latest
DSP output result as soon as it becomes available. Toachieve this,
it must be possible to advance the timing of the DACrelative to the
ADC in some fashion.
High-speed gain taps in parallel with the main processing
pathcan help to ease the situation, especially in the case of
practicalshort ducts where the noise can flank the acoustic path
via theduct hardware itself.
Although a feedforward cancellation technique with a very
lowgroup delay is required to cancel the random component whenusing
a relatively short duct, a feedback approach can be appliedto
cancel the repetitive component using an rpm sync signal asthe
reference input.
ANC ARCHITECTURELess group delay through the cancellation system
means that ashorter duct can be used, making the approach more
feasible andacceptable. To achieve very low group delay, a heavily
oversampledsigma-delta converter technique is employed at the
analog front-end (AFE) section of the system. Furthermore, both an
analoggain tap (AGT) and a digital gain tap (DGT) can be utilized
toprovide even lower group delay in the processing path.
With no high-speed gain taps, a 2-ADC/1-DAC conguration(Figure
3) can be used, as all the processing is done digitally andat a
relatively low rate. In Figure 3, each conversion channel isshown
with its sample-rate conversion in a separate block: a
decimator block in the case of the ADC channel and an
interpolatorblock for the DAC channel.
PROGRAMMABLEFIR
(FEEDFORWARD)
LMSUPDATE
ALGORITHM
FIXEDFIR
(FEEDBACK)
DUCT
ERRORMICROPHONE
REFERENCEMICROPHONE
ANTINOISESPEAKER
+
DECADC
INT
DACDECADC
Figure 3. A 2-ADC/1-DAC configuration with no high- speed gain
taps.
The introduction of gain taps is illustrated in Figure 4.
Filterswith gain taps can be thought of as just single-tap FIR
lters. Thefeedforward tap is programmable and adapted during
cancellation;the feedback tap is xed and determined off-line.
Note that the DGTs act on the high-rate output of the ADC
andtheir outputs are combined with the high-rate input to the
DAC.
FIXEDFIR
(FEEDBACK)
PROGRAMMABLEFIR
(FEEDFORWARD)
LMSUPDATE
ALGORITHM
DUCT
ERRORMICROPHONE
REFERENCEMICROPHONE
ANTINOISESPEAKER
+
DEC
ADC
INT DAC
PROGRAMMABLEGAIN TAP
(FEEDFORWARD)+
+
INTDAC DEC ADC
+
FIXED GAIN TAP(FEEDBACK)
DEC
ADC
Figure 4. ANC system with high-speed analog and digitalgain
taps.
Analog Dialogue 34-2 (2000) 11
-
ANC ALGORITHMThe standard ltered-x LMS (FXLMS) algorithm was
used toupdate the ANC coefcient for the feedforward
cancellation,
hk+1 = hk + 2 ek x'k (5)where x'k is ltered by the secondary
path model. Other adaptivealgorithms have been suggested for
improved performance onxed-point DSPs [6].
The modeling for the secondary path and feedback
neutralizationpath is done off-line; then xed versions are used in
the active-cancellation mode. In addition, each microphone input is
processedthrough an adaptive dc tap, and a leakage component is
optionallypart of the feedforward-path coefcient update
algorithm.
ANC HARDWARE AND SOFTWARE REQUIREMENTSThe short-duct ANC
hardware should include an AFE with atleast two ADC channels and
one DAC channel. The referencesignal ADC and the antinoise DAC need
to have inherently highsample rates and low group delay. The
sampling timing of theantinoise DAC should be capable of being
advanced relative tothe sample timing of the reference ADC. The AFE
should alsohave both high-speed analog and digital gain taps to
provide anultra-short delay path. The error-signal ADC also needs
to be lowin group delay, as its delay contributes to the delay
through thesecondary path as seen by the processor from the
antinoise speakerto the error microphone. As this secondary path
model has to berun by the processing block as well as the main
feedforward path,it should be as short as possible. The main
processing block shouldhave as high a MIPS rate as possible (with
an efcient instructionset) to reduce the delay, keeping within the
general requirementfor a low-cost solution. Finally, a
single-package embodiment ofthe main signal conversion and
processing functions should makethe ANC solution more flexible yet
cost-effective.
One such ANC solution with a single integrated circuit
packagecan be obtained using the AD73522 dspConverter.
AD73522 PRODUCT INFORMATIONThe AD73522 (Figure 5) is a
single-device dspConverterincorporating a dual analog front end
(AFE), a microcomputeroptimized for digital signal processing (DSP)
and a flash-basedboot memory for the DSP.
The AFE section features two 16-bit ADC channels and two16-bit
DAC channels. Each channel provides 77-dB signal-to-noiseratio over
a voiceband signal bandwidth with a maximum samplerate of 64 ksps.
It also features an input-to-output gain network inboth the analog
(AGT) and digital (DGT) domains. The lowgroup-delay characteristic
(typically 25 s per ADC channel and50 s per DAC channel) of the AFE
makes it suitable for single-or multi-channel active control
applications. The ADC and DACchannels feature programmable
input/output gains with ranges of38 dB and 21 dB respectively. An
on-chip reference voltage isincluded to allow single-supply
operation.
The AD73522s 52-MIPS DSP engine combines the ADSP-2100family
base architecture (three computational units, data
addressgenerators and a program sequencer) with two serial ports,
a16-bit internal DMA port, a byte DMA port, a programmabletimer,
flag I/O, extensive interrupt capabilities, and on-chipprogram- and
data memory.
The AD73522-80 integrates 80 Kbytes of on-chip memorycongured as
16K 24-bit words of program RAM and 16K 16-bitwords of data RAM.
The AD73522-40 integrates 40K bytes ofon-chip memory congured as 8K
words of 24-bit program RAMand 16-bit data RAM.
Both devices feature a Flash memory array of 64 Kbytes(512
Kbits) connected to the DSPs byte-wide DMA port(BDMA). This allows
nonvolatile storage of the DSPs boot codeand system data
parameters. The AD73522 runs from a 3.3-Vpower supply. Power-down
circuitry is inherent to meet the low-power needs of
battery-operated portable equipment.
ANALOG FRONT ENDSECTION
ADC1
DAC1
REF
SERIALPORT
SPORT 2ADC2
DAC2
DATA ADDRESSGENERATORS PROGRAM
SEQUENCERDAG 1 DAG 2
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASEARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
POWER-DOWNCONTROL
MEMORY
18K PM(OPTIONAL 8K)
18K DM(OPTIONAL 8K)
PROGRAMMABLEI/O
AND FLAGSFULL MEMORY
MODE
EXTERNALADDRESS
BUS
EXTERNALDATABUS
BYTE DMACONTROLLER
FLASHBYTE MEMORY
64K BYTES
Figure 5. AD73522 dspConverter.
12 Analog Dialogue 34-2 (2000)
-
SIGMA-DELTA ADC AND DAC ARCHITECTUREThe conversion technique
adopted in the AFE is of the sigma-delta type. An analog
sigma-delta modulator is used in the ADCchannel and a digital
sigma-delta modulator is employed in theDAC channel. A sigma-delta
modulator is a heavily oversampledsystem that uses a low-resolution
converter in a noise-shaping loop.The quantization noise of the
low-resolution, high-speed converteris inherently high-pass
filtered and shaped out of band. Theoutput of the modulator or
noise shaper is then low-pass filteredto reduce the sample rate and
remove the out-of-band noise.
The AFE conversion channels used in the AD73522 are shown
inFigure 6. The ADC section consists of an analog second-order,32
to 256 oversampling, 1-bit sigma-delta modulator, followedby a
digital sinc-cubed decimator (divide-by-32 to divide-by-256).The
DAC section contains a digital sinc-cubed interpolator, adigital,
second-order, 32 to 256 oversampling, 1-bit sigma-deltamodulator,
followed by an analog third-order switched-capacitorLPF and a
second-order continuous-time LPF.
The group delay through the ADC channel is dominated by thegroup
delay through the sinc-cubed decimator and is given by thefollowing
relationship:
dec dsOrder
M=
1
2(6)
where Order is the order of the decimator (= 3), M is the
decimationfactor (= 32 for 64-ksps output sample rate) and ds is
thedecimation sample interval (= 1/2.048E6 s)
= dec E3
32 12
12 048 6
.
(7)
dec = 22.7 sfor a 64-ksps output sample rate.
The group delay through the DAC channel is primarily
determinedby the group delay through the sinc-cubed interpolator
and thegroup delay through the third-order switched-capacitor LPF.
Theinherent group delay through the interpolator is identical to
thatthrough the decimator and equals 22.7 s for 64-ksps input
samplerate. However, the interpolator can be optionally bypassed
to
avoid this inherent group delay at the expense of reduced
out-of-band rejection.
The z-transform of both the sinc-cubed decimator and
interpolatoris given by:
1
1 1
3
z
z
M
(8)
The group delay through the analog section of the DAC
isapproximately 22.7 s.Notice that with sample rates of only 8 ksps
the inherent groupdelays through both the decimator and
interpolator increase to186.8 s. Therefore, it is very important to
run the converters atas high a rate as possible to reduce the
inherent group delay.
The AFE features high-speed analog and digital feedforward
pathsfrom ADC input to DAC output via the AGT and DGTrespectively.
The AGT is configured as a differential amplifier withgain
programmable from 1 to +1 in 32 steps and a separate mutecontrol.
The gain increment per step is 0.0625. The group delaythrough the
AGT feedforward path is only 0.5 s. The DGT is aprogrammable gain
block whose input is tapped off from the bit-stream output of the
ADCs analog sigma-delta modulator. Thissingle-bit input is used to
add or subtract the digital gain tap setting,a 16-bit programmable
value, to the output of the DACsinterpolator. The group delay
through the DGT feedforward pathis only 25 s.The loading of the DAC
is normally internally synchronized withthe unloading of the ADC
data in each sampling interval. However,this DAC load position can
be advanced in time by up to 15 s in0.5-s steps. This facility can
be used to further minimize thefeedforward delay from analog input
to analog output via the DSP.
AD73522 PACKAGINGThe three main processing elements (AFE, DSP
and Flashmemory) are combined in a single package to give a
cost-effective,self-contained solution. This single package is a
119-ball plasticball grid array (PBGA), as shown in Figure 7. It
measures 14 mm 22 mm 2.1 mm, and the solder balls are arranged in a
7 17array with a 1.27-mm (50 mil) pitch.
+6/15dBPGA
+ CONTINUOUSTIME
LOW-PASSFILTER
SWITCHEDCAPACITORLOW-PASS
FILTER
1-BITDAC
ANALOGSIGMA-DELTAMODULATOR
+
0/38dBPGA
INVERTSINGLE-ENDED
ENABLE
+
+
GAIN1
+
DECIMATOR
GAIN1
+
DIGITALSIGMA-DELTA
MODULATORINTERPOLATOR
VREF
VFBN1VINN1
VINP1VFBP1
VOUTP1
VOUTN1
Figure 6. Analog front-end subsection of the AD73522
dspConverter.
Analog Dialogue 34-2 (2000) 13
-
TOP VIEW
14 mm
22 mm
a.
BOTTOM VIEW
7 ROWS 17 COLUMNS OF SOLDER BALLS
b.Figure 7. AD73522 plastic ball grid array (PBGA)
packaging.
AD73522 EVALUATION BOARDThe AD73522 dspConverter evaluation
board (Figures 8 and 9)combines all of the front-end analog signal
conditioning with a
user-friendly programming platform that allows quick and
easydevelopment. The board, interfacing to the serial port of a
PC,comes with Windows 95-compatible interface software that
allowsthe transfer of data to and from all memory, including the
Flashsections. All of the dspConverter pins are available at the
outputconnectors. The board has an EZ-ICE connector for
advancedsoftware development. Other features include a microphone
withconditioning circuitry on one input channel and speaker
amplierson the output channels.
Figure 8. AD73522 dspConverter evaluation board.
EXPERIMENTAL SETUPThe experimental setup (Figure 10) consists of
a server box(containing just a fan and power supply), a plastic
duct (withreference and error microphones and secondary
loudspeaker), andthe AD73522 evaluation board. The server fan was 5
inches (about13 cm) in diameter. The T-shaped duct and the speaker
measured6 inches (about 15) cm in diameter. The duct length was
adjustabledown to a minimum of 12 inches (30.5 cm).
AD73422/AD73522
512k 8FLASH
RS-232DRIVER
POWERAMP
ADDRESS/DATA/CONTROL
FLAGS AND SPORTADDRESSA13A0D20D16
DATAD15D0
SPORT 0
PF4
FL0
PF3
OUTPUT(2)
OUTPUT(1)
8SPEAKEROUT
PCINTERFACE
EZ-ICE J1
J13
J12
J3
J2
J7
J5
J6
SWITCHES
LEDRESET
DATAD7D0
INTERRUPT
PF7
FL1LED
J10
J11
POWERCIRCUITRY
12V DC
5V DC
MIC
INPUT(1)
INPUT(2)
J9
J8
J4
dspCONVERTER EVALUATION BOARD
CH1 CH2 CH1 CH2
DVCC3.2V
AVCC3.2V
INPUTCONDITIONING
CIRCUITRY
OUTPUTCONDITIONING
CIRCUITRY
Figure 9. Block diagram of the AD73522 dspConverter evaluation
board.
Windows is a registered trademark of Microsoft
Corporation.EZ-ICE is a registered trademark of Analog Devices,
Inc.
14 Analog Dialogue 34-2 (2000)
-
During experimentation, the AD73522 evaluation board washooked
up to a PC for debug. Also, internal variables were writtenout to
unused DAC channels for monitoring. Initially, the systemwas set up
using a primary speaker instead of the actual server fanto allow
testing with programmable tones and broadband signals.
Figure 10. Server fan experimental setup.
RESULTSThe performance of the experimental setup with a
single-tonedisturbance from the primary speaker is shown in Figure
11. Themain tone is reduced by a factor of 30 dB. When the
primaryspeaker delivers a broadband disturbance, the reduction
factor isabout 20 dB, as illustrated in Figure 12.
0
800 1
AM
PLIT
UDE
dB
FREQUENCY kHz
NO ANC
ANC
a. 136-Hz performance, with and without ANC.
0
800 1
AM
PLIT
UDE
dB
FREQUENCY kHz
NO ANC
ANC
b. 510-Hz performance, with and without ANC.
Figure 11. Noise spectra with single-tone disturbance.
0
600.2 0.6
AM
PLIT
UDE
dB
FREQUENCY kHz
NO ANC
ANC
Figure 12. Performance with broadband disturbance.
CONCLUSIONSAn approach combining an analog gain tap (AGT) and
digitalgain tap (DGT) allows the use of sigma-delta techniques in
low-group-delay ANC applications. A single-package
embodimentcombining analog and digital functions, like the
AD73522dspConverter, should provide an ANC solution that is both
flexibleand cost-effective.
ACKNOWLEDGEMENTSDell Computer, Limerick, Ireland, for the
Poweredge 2200 serverbox used in the experimental setup.
Cork Institute of Technology, Cork, Ireland, for the
ductconstruction used in the experimental setup and a kick-start
inthe code development.
The Institute of Sound and Vibration Research (ISVR)
andDigisonix, Inc., for an excellent introduction to active noise
control.
REFERENCES1. S.M. Kuo & D.R. Morgan, Active Noise Control
Systems:
Algorithms and DSP Implementations (Wiley, New York, 1996)
2. A Primer on Active Sound and Vibration Control, L.J.Eriksson,
Digisonix brochure
3. Application of Active Noise Control for Small-Sized
ElectronicEquipments, T. Hoshino, K. Fujii, T. Ohashi, A.
Yamaguchi,H. Furuya, J. Ohga, Inter-noise 94, 1409-1412 (1994)
4. Study of Active Noise Control System for Duct with HighSpeed
Flow, T. Hoshino, T. Ohashi, J. Ohga, H. Furuya, A.Yamaguchi, K.
Fujii, Active95 (International Symposium onActive Control of Sound
and Vibration), 423-430 (1995)
5. Active Control of Fan Noise in a Personal Computer, M.OBrien,
P. Pratt, IEEE ISSC 99 Digest, pp. 385-392 (1999)
6. An Adaptive Algorithm for Active Noise Control System by
aFixed Point Processing Type DSP, K. Fujii, A. Yamaguchi, H.Furuya,
J. Ohga, Active97, 1163-1170 (1997)
7. Short Duct Server Fan Noise Cancellation, P. Minogue,
N.Rankin, J. Ryan, Active99, 539-550 (1999) b
Analog Dialogue 34-2 (2000) 15
-
Fan-Speed ControlTechniques in PCsby David Hanrahan
Analog Devices offers a comprehensive set of
hardware-monitoringproducts for use in desktop and notebook PCs and
servers.Intelligent systems-monitoring devices make possible
sophisticatedfan speed control techniques to provide adequate
cooling andmaintain optimal thermal performance in the system.
During thepast year a family of products has been developed,
including theADM1029 Dual PWM Fan Controller and Temperature
Monitor,the ADM1026, and ADM1030/ADM1031 Complete, ACPI-Compliant,
Dual-Channel 1C Remote Thermal Monitor withintegrated fan
controller for one or two independent fans. Theybuild on the core
technology used in the ADM102x PC SystemMonitor product portfolio
(see also Analog Dialogue 33-1 and 33-4). Providing fan speed
control based on the temperaturesmeasured within the system, these
new products offer morecomplete thermal-management solutions. We
discuss here the needfor this level of sophisticated control and
the issues inherent inproviding it.
BACKGROUNDAs the new millennium dawns, processors are achieving
speeds of1 GHz and more. Their impressive improvements in speed
andsystem performance are accompanied by the generation
ofincreasing amounts of heat within the machines that use them.The
need to safely dissipate this heat, along with moves in
thecomputing industry to develop Green PCs and
user-friendlymachines (as Internet appliances become mainstream),
has driventhe need for, and development of, more sophisticated
cooling andthermal management techniques.
PCs have also begun to become smaller and less conventional
insize and shapeas can be seen in any of the latest concept PCs
orslim-line notebooks on the market. Rigid power
dissipationspecifications such as Mobile Power Guidelines 99 (Ref.
1)stipulate how much heat may be safely dissipated through
anotebooks keyboard without causing user discomfort. Any excessheat
must be channeled out from the system by other means, suchas
convection along heat pipes and a heat-spreader plate, or theuse of
a fan to move air through the system. Clearly, what is neededis an
intelligent, effective approach to thermal management thatcan be
universally adopted. Various industry groups have assembledto
address these and other issues, and have developed standardssuch as
ACPI (advanced configuration and power interface) fornotebook PCs
and IPMI (intelligent platform management interface)for server
management.
INDUSTRY STANDARDSThe development of the new thermal
management/speed controlproducts was motivated by the ACPI and IPMI
standards.
The Advanced Configuration and Power InterfaceACPI (Ref 2)
wasdefined by Intel, Microsoft, and Toshiba primarily to define
andimplement power management within notebook PCs.
Power management (Ref. 2) is defined as Mechanisms inhardware
and software to minimize system power consumption,manage system
thermal limits, and maximize system battery life.Power management
involves trade-offs among system speed, noise,battery life,
processing speed, and ac power consumption.
Consider first a notebook-PC user who types trip reports
whileflying across oceans or continents. Which characteristic is
moreimportant, maximum CPU performance or increased battery life?In
such a simple word-processor application, where the timebetween a
users keystrokes is almost an eternity in CPU clockcycles, maximum
CPU performance is nowhere near as critical ascontinuous
availability of power. So CPU performance can betraded off against
increased battery life. On the other hand, considerthe user who
wants to watch the latest James Bond movie in full-motion,
full-screen, mind-numbing sound and brightness, ondigital versatile
disk (DVD). It is critical that the system operatesat a level of
performance to decode the software fast enough,without dropping
picture or audio frames. In this situation CPUperformance cannot be
compromised. Therefore, heat generationwill be at top levels, and
attention to thermal management will beof paramount importance to
obtain top performance withoutimpairing reliability. Enter
ACPI.
What then is ACPI? ACPI is a specification that describes the
inter-face between components and how they behave. It is not a
purelysoftware or hardware specification since it describes how the
BIOSsoftware, OS software, and system hardware should interact.
The ACPI specification outlines two distinct methods of
systemcooling: passive cooling and active cooling. Passive cooling
relies onthe operating-system (OS) and/or basic
input/output-system(BIOS) software to reduce CPU power consumption
in order toreduce the heat dissipation of the machine. How can this
beachieved? By making intelligent decisions such as entering
suspendmode if no keystroke or other user interaction has been
detectedafter a specified time. Or if the system is performing some
intensivecalculations, such as 3D processing, and is becoming
dangerouslyhot, the BIOS could decide to throttle (slow down) the
CPU clock.This would reduce the thermal output from the machine,
but atthe cost of overall system performance. What is the benefit
of thispassive-type cooling? Its distinct advantage is that the
system powerrequirement is lowered silently (fan operation is not
required) in orderto decrease the system temperature, but this does
limit performance.
So, what about active cooling? In an actively cooled system,
theOS or BIOS software takes a direct action, such as turning on
aCPU mounted fan, to cool down the processor. It has the
advantagethat the increased airflow over the CPUs metal slug or
heat-sinkallows the heat to be drawn out of the CPU relatively
quickly. In apassively cooled system, CPU throttling alone will
prevent furtherheating of the CPU, but the thermal resistance of
the heat sink tostill air can be quite large, meaning that the heat
sink woulddissipate the heat to the air quite slowly, delaying a
return to full-speed processing. Thus, a system employing active
cooling cancombine maximum CPU performance and faster heat
dissipation.However, operation of the fan introduces acoustic noise
into thesystems environment and draws more power. Which
coolingtechnique is better? In reality, it depends on the
application; a
All brand or product names mentioned are trademarks or
registeredtrademarks of their respective holders.
16 Analog Dialogue 34-4 (2000)
-
versatile machine will use both techniques to handle
differingcircumstances. ACPI outlines the cooling techniques in
terms oftwo different modes: performance mode and silent mode. The
twomodes are compared in Figures 1 and 2.
_CRT9085807560555045403530252015105
_PSV
_ACx
POLICYSCI EVENT
_CRT9085807560555045403530252015105
_PSV
_ACx
POLICYSCI EVENT
1 2
Figure 1. Performance preferred. Active mode (_ACx, fan on)is
entered at 50, passive mode (_PSV, throttle back) is en-tered at
60. Shutdown occurs at the critical temperature(_CRT) 90. Fan speed
may increase at levels above ACx.Figure 2. Silence and battery
economy preferred. Passive modeis first entered at 45, and fan is
not turned on until 60.
Figures 1 and 2 are examples of temperature scales that
illustratethe respective trade-offs between performance, fan
acoustic noise,and power consumption/dissipation. In order for a
system-management device to be ACPI-compliant, it should be
capableof signaling limit crossings at, say, 5C intervals, or SCI
(system-control interrupt) events, that a new out-of-limit
temperatureincrement has occurred. These events provide a mechanism
bywhich the OS can track the system temperature and make
informeddecisions as to whether to throttle the CPU clock,
increase/decreasethe speed of the cooling fan, or take more drastic
action. Once thetemperature exceeds the _CRT (critical temperature)
policy setting,the system will be shut down as a fail-safe to
protect the CPU. Theother two policy settings shown in Figures 1
and 2 are _PSV(passive cooling, or CPU clock throttling) and _ACx
(activecooling, when the fan switches on).
In Figure 1 (performance mode), the cooling fan is switched on
at50C. Should the temperature continue to rise beyond 60C,
clockthrottling is initiated. This behavior will maximize
systemperformance, since the system is only being slowed down at a
highertemperature. In Figure 2 (silent mode), the CPU clock is
firstthrottled at 45C. If the temperature continues to rise, a
coolingfan may be switched on at 60C. This reduced-performance
modewill also tend to increase battery life, since throttling back
theclock reduces power consumption.
Figure 3 shows how the limits of the temperature
measurementbands track the temperature measurement. Each limit
crossingproduces an interrupt.
HIGH LIMIT
LOW LIMIT
100C
90C
80C
70C
60C
50C
40C
INT
TEMP
ACPI CONTROLMETHODS
CLEAR EVENT
*ACPI DEFAULT CONTROL METHODSADJUST TEMPERATURE LIMIT VALUES
*
**
*
*
*
Figure 3. Tracking temperature changes by moving limits
andgenerating interrupts.
The intelligent platform management interface (IPMI)
specification(Ref. 3) brings similar thermal management features to
servers.IPMI is aimed at reducing the total cost of ownership (TCO)
of aserver by monitoring the critical heartbeat parameters of
thesystem: temperature, voltages, fan speeds, and PSUs
(power-supplyunits). Another motivation for IPMI is the need for
interoperabilitybetween servers, to facilitate communication
between baseboardsand chassis. IPMI is based on the use of a 5-V
I2C bus, withmessages sent in packet form. Further information on
IPMI isavailable from the Intel website at
All members of the Analog Devices Temperature and
Systems-Monitoring (TSM) family are ACPI- and IPMI-compliant.
TEMPERATURE MONITORINGThe prerequisite for intelligent fan-speed
control within PCs is theability to measure both system and
processor temperatureaccurately. The temperature monitoring
technique used has beenthe subject of many articles (for example,
see Analog Dialogue 33-4)and will only be briefly visited here. All
Analog Devices system-monitoring devices use a temperature
monitoring technique knownas thermal diode monitoring (TDM). The
technique makes use ofthe fact that the forward voltage of a
diode-connected transistor,operated at a constant current, exhibits
a negative temperaturecoefficient, about 2 mV/C. Since the absolute
value of VBEvaries from device to device, this feature by itself is
unsuitablefor use in mass-produced devices because each one would
requireindividual calibration. In the TDM technique, two
differentcurrents are successively passed through the transistor,
and thevoltage change is measured. The temperature is related to
thedifference in VBE by:
VBE = kT/q ln(N)
where: k = Boltzmanns constant
q = electron charge magnitude
T = absolute temperature in kelvins
N = ratio of the two currents
Analog Dialogue 34-4 (2000) 17
-
REMOTESENSING
TRANSISTOR
D+
D
VDD
BIASDIODE LOW-PASS FILTER
fc65kHz
VOUT+TO ADCVOUT
N11 VDAS
Figure 4. Basic TDM signal-conditioning circuit.
In any CPU, the most relevant temperature is that of the hotspot
on the die. All other temperatures in the system (includingthe
heat-sink temperature) will lag the rise in this temperature.For
this reason, practically every CPU manufactured since theearly
Intel Pentium II processors contains a strategically
locatedtransistor on its die for thermal monitoring. It gives a
true,essentially instantaneous, profile of die temperature. Figure
5 showstemperature profiles in a system repeatedly entering and
wakingup from suspend mode. It compares the temperatures measuredby
a thermistor attached to the CPUs heat sink and by the
substratethermal diode. In the short interval for the actual die
temperatureto change back and forth by about 13, the heat sink
thermistorcannot sense any change.
Figure 5. Comparison of temperatures measured by a heatsink
thermistor and by TDM during a series of entrances toand exits from
suspend mode.
TEMPERATURE TO FAN CONTROLWith an accurate temperature
monitoring method established,effective fan control can be
implemented! The technique, in general,is to use TDM to measure
temperature, with the sensing transistoreither integrated on-chip
or externally placed as near as possibleto a hot-spot, and setting
the fan speed at a level that will ensuresufficient heat transport
at that temperature. Various operatingparameters of the control
loop will be programmable, such asminimum speed, fan start-up
temperature, speed versustemperature slope, and turn on/off
hysteresis. The speed controlapproaches described will include
on-off, continuous (linear),and pulsewidth modulation (PWM).
Fan-control methods: Historically, the range of approaches
tofan-speed control in PCs is from simple on-off control to
closed-loop temperature-to-fan speed control.
Two-step control: This was the earliest form of fan-speed
controladopted in PCs. The BIOS would measure the system
temperature(originally using a thermistor in close proximity to the
CPU) anddecide whether to switch a cooling fan fully on or off.
Later, PCsused more accurate TDM-based temperature monitors
toimplement the same two-step fan control.
Three-step control: The BIOS or Operating System again
measuresthe temperature using a thermistor or thermal diode and,
basedon software settings, decides whether to turn the fan fully
on, fullyoff, or set it to run at half-speed.
Linear fan-speed control: This more recent method of
fan-speedcontrol is also known as voltage control. The BIOS or OS
reads thetemperature from the TDM measurement circuit and writes
backa byte to an on-chip DAC, to set the output voltage in order
tocontrol the speed of the fan. An example of an IC fan controller
ofthis type is the ADM1022, which has an 8-bit DAC on-chip withan
output voltage range of 0 V to 2.5 V. It works with an
externalbuffer amplifier having appropriate design ratings for the
chosenfan. The ADM1022 also contains default automatic hardware
trippoints that cause the fan to be driven at full-speed in the
eventthat its TDM circuit detects an over-temperature condition.
Thedebut of these types of devices signified the emergence of
automaticfan-speed control, where some of the decision-making is
moved fromOS software to system-monitoring hardware.
Pulsewidth-modulation fan-speed control: In ADIs
systems-monitoring product line, these PWM types are the most
recentfan control products. The BIOS or OS can read the
temperaturefrom the TDM device and control the speed of the cooling
fan byadjusting the PWM duty cycle applied to it.
It is worth noting that all of the above methods of fan-speed
controlrely on CPU or host intervention to read the temperature
fromthe TDM device over the 2-wire System Management Bus.
Thethermal management software executed by the CPU must thendecide
what the fan speed should be and write back a value to aregister on
the systems monitor IC to set the appropriate fan speed.
An obvious next step in the evolution of fan-speed control is
toimplement an automatic fan-speed control loop, which could
behaveindependently of software and run the fan at its optimum
speedfor a given chip temperature. There are many benefits to
suchclosed-loop speed control.
Once the systems monitoring device has been initialized
(byloading limit registers with required parameters), the control
loopis then completely independent of software, and the IC can
reactto temperature changes without host intervention. This feature
isespecially desirable when a catastrophic system failure occurs,
fromwhich the system is unable to recover. If the PC crashes, the
powermanagement software in the OS is no longer executing,
whichresults in loss of thermal management! If the PC cannot read
thetemperature being measured (since the PC has crashed), it
cannotbe expected to set the correct fan speed to provide the
requiredlevel of cooling.
The other tangible benefit of a closed-loop implementation is
thatit will operate the fan at the optimum speed for any
giventemperature. This means that both acoustic noise and
powerconsumption are reduced. Running a fan at full speed
maximizesboth power consumption and acoustic noise. If the fan
speed can
18 Analog Dialogue 34-4 (2000)
-
be managed effectively through loop optimization, running onlyas
fast as needed for a given temperature, power drain and audiblefan
noise are both reduced. This is an absolutely criticalrequirement
in battery-powered notebook PC applications whereevery milliampere
of current, or milliamp-second of charge, is aprecious
commodity.
AUTOMATIC FAN-SPEED CONTROL LOOPHeres how one might implement an
automatic fan-speed controlloop, which will measure temperature
using TDM techniques andset the fan speed appropriately as a
function of temperature.Programmable parameters allow more complete
control of the loop.The first register value to be programmed is
TMIN. This is thetemperature (corresponding to ACx) at which the
fan will firstswitch on, and where fan speed control will begin.
Speed ismomentarily set at maximum to get the fan going, then
returnedto the minimum speed setting (see Figure 6). The parameter
thatallows control of the slope of the temperature-to-fan speed
functionis the range from TMAX to TMIN, or TRANGE. The
programmedvalues for TMIN and TRANGE define the temperature at
which thefan will reach maximum speed, i.e., TMAX = TMIN +
TRANGE.Programmed temperature range is selectable: 5C, 10C,
20C,40C, and 80C. In order to avoid rapid cycling on and off in
thevicinity of TMIN, hysteresis is used to establish a temperature
belowTMIN, at which the fan is turned off. The amount of hysteresis
thatcan be programmed into the loop is 1C to 15C. This fan
controlloop can be supervised by OS software over the SMBus and
thePC can decide to override the control loop at any time.
FULLSPEED
FAN SPEED
MINSPEED
TEMPERATURE
SPIN UP FOR 2 SECONDS
HYSTERESIS
TMIN TMAX
Figure 6. Fan speed programmed as an automatic function
oftemperature.
PWM vs. LINEAR FAN-SPEED CONTROLOne might ask why pulsewidth
modulation is desirable if linearfan-speed control is already in
widespread use.
Consider a 12-V fan being driven using linear fan-speed
control.As the voltage applied to the fan is slowly increased from
0 V toabout 8 V, the fan will start to spin. As the voltage to the
fan is
further increased, the fan speed will increase until it runs
atmaximum speed when driven with 12 V. Thus the 12-V fan has
aneffective operating window between 8 V and 12 V, with a range
ofonly 4 V available for use in speed control.
The situation becomes even worse with the 5-V fan that would
beused with a notebook PC. The fan will not start until the
appliedvoltage is about 4 V. Above 4 V, the fan will tend to spin
near fullspeed, so there is little available speed control between
4 V and5 V. Thus, linear fan-speed control is unsuitable for
controllingmost types of 5 V fans.
With pulsewidth modulation, maximum voltage is applied
forcontrolled intervals (the duty cycle of a square wave, typically
at30 Hz to 100 Hz). As this duty cycle, or ratio of high time to
lowtime, is varied, the speed of the fan will change.
At these frequencies, clean tach (tachometer) pulses are
receivedfrom the fan, allowing reliable fan-speed measurement. As
drivefrequencies go higher, there are problems with insufficient
tachpulses for accurate measurement, then acoustic noise, and
finallyelectrical spikes corrupting the tach signal. Therefore,
most PWMapplications use low frequency excitation to drive the fan.
Theexternal PWM drive circuitry is quite simple. It can
beaccomplished with a single external transistor or MOSFET to
drivethe fan (Figure 7). The linear fan-speed-control equivalent,
drivenby an analog speed voltage, requires an op amp, a pass
transistor,and a pair of resistors to set the op amp gain.
PWM_OUT1
ADM1031TACH/AIN1
Q12N2219A
5VRB
5V
R239kR1
10k
R31k
FAN_SPD AD8519R4
1k
12V
Q1BD1362SA968
7A 7B
Figures 7A and 7B. PWM drive circuit compared with a lineardrive
circuit.
How is the fan speed measured? A 3-wire fan has a tach
outputthat usually outputs 1, 2, or 4 tach pulses per revolution,
dependingon the fan model. This digital tach signal is then
directly applied tothe tach input on the systems-monitoring device.
The tach pulsesare not countedbecause a fan runs relatively slowly,
and it wouldtake an appreciable amount of time to accumulate a
large numberof tach pulses for a reliable fan speed measurement.
Instead, thetach pulses are used to gate an on-chip oscillator
running at22.5 kHz through to a counter (see Figure 8). In effect,
the tachperiod is being measured to determine fan speed. A high
count inthe tach value register indicates a fan running at low
speed (andvice versa). A limit register is used to detect sticking
or stalled fans.
Analog Dialogue 34-4 (2000) 19
-
CLOCK
FAN 1MEASUREMENT
PERIOD
FAN 0MEASUREMENT
PERIODSTART OF
MONITORINGCYCLE
CONFIGREG. BIT 4
FAN 0INPUT
FAN 1INPUT
Figure 8. Fan-speed measurement.
What other issues are there with fan-speed control?
When controlling a fan using PWM, the minimum duty cycle
forreliable continuous fan operation is about 33%. However, a
fanwill not start up at 33% duty cycle because there is not
enoughpower available to overcome its inertia. As noted in the
discussionof Figure 6, the solution to this problem is to spin the
fan up fortwo seconds on start-up. If the fan needs to be run at
its minimumspeed, the PWM duty cycle may then be reduced to 33%
after thefan has spun up, and it is protected from stalling by the
hysteresis.
FAN STALLS AND FAN FAILURESNevertheless, the possibility can
arise that a fan may stall at sometime while used in a system.
Causes may include a fan operatingtoo slowly, or dust build-up
preventing it from spinning. For thisreason, the Analog Devices
systems monitors have an on-chipmechanism based on the fans tach
output to detect and restarta stalled fan. If no tach pulses are
being received, the value inthe Tach Value register will exceed the
limit in the Tach LimitRegister and an error flag will