VMF Detailed Design Version 3

VMF Detailed DesignVersion 3

by Yehuda Afek

Alexander Matveev04/22/23 VMF Dettailed Dezign ver2 1

Subjects Abstract Idea Transactional Memory:

Memory Model Transaction Illustration

Requirements: VMF Transactional Memory

Hardware Implementation: Overview VMF Prediction Table

Concept Algorithm

VMF Stripe Cache Concept Algorithm

VMF Call Invoke Trigger VMF Miss Prediction Handling VMF Call Invoke implementation TLB Modifications VMF Code Segment: VMF_Start and VMF_End Context Switch Handling

04/22/23 VMF Dettailed Dezign ver2 2

Abstract idea

• To automate the transactification process.• Drastically simplify the compiler.• The HW will automatically do the STM.• It is like HW assisted STM


TM Memory Model

• Virtual memory pages are divided to stripes• stripe can have an object inside or multiple objects.

Also the objects can be splitted between the stripes.• TM algorithm granularity will be stripe. Therefore,

the read-set and write-set entries are stripes.• TM algorithm is applied only for memory accesses to

the shared memory.• The user marks which memory pages are shared and

which are not-shared.


TM Transaction

• Transaction is a block of code annotated by – {TxBegin, … block of code … , TxEnd}.

• Inside the transaction:– shared memory accesses: must be preceded by a

TxLD or TxST function call.– non-shared memory accesses: proceed regularly

• TxLD or TxST: call will record the shared memory access (to read-set or write-set) and will perform the TM algorithm specific code.


.

.

Non-Shared Page

stripe

Virtual MemoryCODE

LD r, X1

ST Y, r

LD r, X1+1Transaction

TM Illustration

LD r, X2

Shared Page

Non-Shared Page

TxBegin

TxEnd

TxLD invoked

TxLD invoked

TxST invoked

no invokation

Non-Shared Page


• VMF Code Segment: block of code annotated as: – {VMF_Start, … block of code …, VMF_End)– VMF_Start and VMF_End are defined in next slides

• VMF Invocation Trigger: For VMF code segment, VMF Call is invoked for LD or ST instruction if all the following conditions are true:

1. memory access address page is marked as shared2. If LD: memory access address stripe was not accessed before for LD (After the

VMF_Start call)3. If ST: memory access address stripe was not accessed before for ST (After the

VMF_Start call)

• VMF Call Invoke: If LD/ST instruction invoked VMF then the order of execution is:1. VMF function (given the read/write memory address)2. The original LD/ST instruction

VMF - Requirements


• VMF Call = TxLD/TxST for LD/ST instruction• VMF Code Segment is:

– START = TxBegin– END = TxEnd

• TxBegin:1. Execute VMF_Start (Defined in next slides)2. Execute the TM_Start

• TxEnd:1. Execute the TM_Commit using the constructed READ-SET and

WRITE-SET.2. Execute VMF_End (Defined in next slides)

TM - Requirements


Hardware Implementation Overview

• VMF Call Invoke will be done once per read or write access to every stripe during the transaction. In order to support this the following changes will done to the pipeline:– Fetch Stage: VMF Prediction Table (VMF PT) will be used to predict VMF

Call Invoke based on previous results for current LD/ST instruction.– MEM Stage: VMF Stripe Cache (VMF SC) will be used to cache stripes

that have been already accessed.• New Registers: Upon VMF Call we want to store:

– VMF_ADDR_REG: The memory address accessed by the LD/ST instruction that invoked the VMF

– VMF_PC_REG: The PC of the current LD/ST instruction so we can return back

• New Instructions: – VMF_Start opcode– VMF_End opcode



TLB

PC RegPC RegAddr Reg

inst addr vmf F

Inst PCAccess Addr

VMF Ctrl

VMF PT

SC

• CONCEPT: We distinguish between three types of instruction occurrences which access shared data:• Multiple Invoke: Instruction that access a different stripe in each occurrence

of the instruction in a transaction.• Once Invoke: Instruction accessing the same stripe throughout a transaction.

• First Time:• Repeated: Instruction accessing the same stripe during the transaction AND it is accessing a

stripe that was accessed before by some LD/ST instruction during THE SAME transaction.– Table entry is:

• ( instruction address , flags ) can be squeezed into 32 bits. (The last 2 bits of 32 bit instruction address can be used).

– Flags (2 bit):• 0: Once invoke type (Not yet invoked)• 1: Once invoke type (Repeated)• 2: Multiple invoke type (Not invoked yet)• 3: Multiple invoke type (Already invoked)

VMF Prediction TableConcept


VMF Prediction TableAlgorithm

1. COMMON CASE: If instruction triggered VMF Call and VMF Call was predicted:

– If instruction’s entry flags == 0 (Once Invoke – Not invoked yet) then– Update the instruction’s entry flags to 1 (Once Invoke – Already invoked)

– Else if instruction’s entry flags == 2 (Multiple Invoke – Not invoked yet) then1. Update the instruction’s entry flags to 3 (Multiple Invoke – Already invoked)

– Else,– The instruction’s entry flags is 3 (Multiple Invoke – Already invoked). Do no changes to

the entry.

– STUDY CASE - Once Invoke: If instruction triggered VMF Call and VMF call was not predicted:– Create entry with ( current instruction address , flags = 1 )

• STUDY CASE – Multiple Invoke: If instruction triggered VMF Call and VMF call was not predicted because flags == 1 for the entry:

1. Set entry’s flags to 3 (Multiple Invoke – Already invoked )

– RESTUDY CASE – NOT COMMON: If instruction did not triggered VMF Call and VMF call was predicted:– Remove instruction’s entry


VMF Stripe Cache• CONCEPT: The purpose of the VMF Stripe Cache is to record the stripes

that were already accessed in the current transaction.• ALGORITHM:

– Every entry has:• ( stripe address , flags)

– Flags can be:• 0 – read access was performed• 1 – write access was performed

– If shared memory access triggers VMF Call Invoke and the VMF PT flags is not equal to 3 (Multiple Invoke – Already Called) then:• Entry is created in the table holding the stripe’s address and the

access type information (0 for LD, 1 for ST)


VMF Call Invoke Trigger

• VMF Call Invoke Trigger: VMF Call Invoke is triggered if all following conditions are met for current LD/ST instruction:1. Memory access address page is marked as shared2. Memory access address stripe entry = (stripe address,

flags = 0 for LD or 1 for ST) is not in VMF Stripe Cache• Updates Upon Trigger: If VMF Call Invoke Trigger is True

then:– VMF Stripe Cache is updated: new entry is added– VMF Prediction Table is updated: new entry is added, or

entry’s flags is switched from 0 to 1 or from 1 to 2 or from 2 to 3.


VMF Miss Prediction Handling

• If current LD/ST instruction triggers VMF Call Invoke and VMF PT did not predict it then:1. Store current LD/ST instruction:• Memory access address (to special register)• Instruction PC (to special register)

2. Flush the pipeline3. Restart execution at PC = VMF Call Base Address


VMF Call Invoke Hardware Implementation

• In order to invoke the VMF Call we need to pass parameters to it. The basic parameters are current instruction’s:• Memory access address• Instruction PC

– Therefore upon VMF Call Invoke Trigger:– Memory access address is forwarded to the

VMF_ADDR_REG– Instruction PC is forwarded to the VMF_PC_REG– Current LD/ST instruction is aborted– (If was VMF miss prediction then pipeline flush is

performed)– VMF Call Procedure is executed normally


• Every page has additional bit – 0 – not marked (not shared)– 1 – marked (shared)

page addr Option FlagsS Flag

TLB Modifications


• VMF_Start:– VMF PT:• If entry’s flag is 1 then reset it to 0• If entry’s flag is 3 then reset it to 2

– VMF SC (Stripe Cache): remove entries– Trigger VMF on

• VMF_End:– Trigger VMF off

VMF Code Segment


Context Switch

• Upon context switch:– Flush the VMF tables (to preserve correctness)

04/22/23 VMF Detailed Design ver3 19

VMF Detailed Design Version 3

Documents

vmf function

vmf prediction table

vmf detailed designversion

shared memory accesses

memory access address

block of code

memory access address

tm algorithm specific