Vlsi

VLSI TechnologyVLSI Technology

ScalingScaling Moore’s LawMoore’s Law 3D 3D VLSIVLSI

The beginningThe beginning

Microprocessors are essential to many of the Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, products we use every day such as TVs, cars, radios, home appliances and of course, computers. home appliances and of course, computers. Transistors are the main components of Transistors are the main components of microprocessors.microprocessors.

At their most basic level, transistors may seem At their most basic level, transistors may seem simple. But their development actually required simple. But their development actually required many years of painstaking research. Before many years of painstaking research. Before transistors, computers relied on slow, inefficient transistors, computers relied on slow, inefficient vacuum tubes and mechanical switches to process vacuum tubes and mechanical switches to process information. In 1958, engineersinformation. In 1958, engineers managed to put two managed to put two transistors onto a transistors onto a SiliconSilicon crystal and create the first crystal and create the first integrated circuit, whichintegrated circuit, which subsequently subsequently led to theled to the first first microprocessor.                                                 microprocessor.                                                 

Transistor Size ScalingTransistor Size Scaling

MOSFET performance improves as size is decreased:

shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.

Significant BreakthroughsSignificant BreakthroughsTransistor size: Intel’s research labs have recently shown the world’s smallest transistor, with a gate length of 15nm. We continue to build smaller and smaller transistors that are faster and faster. We've reduced the size from 70 nanometer to 30 nanometer to 20 nanometer, and now to 15 nanometer gates.

Manufacturing process: A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1,000 of these "wires" placed side-by-side to equal the width of a human hair. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds.

Wafer size: Wafers, which are round polished disks made of silicon, provide the base on which chips are manufactured. Use a bigger wafer and you can reduce manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size, up from the previous wafer size of 200mm (about 8 inches).

Major Design ChallengesMajor Design Challenges Microscopic issuesMicroscopic issues

– ultra-high speedsultra-high speeds

– power dissipation and power dissipation and supply rail dropsupply rail drop

– growing importance of growing importance of interconnectinterconnect

– noise, crosstalknoise, crosstalk

– reliability, reliability, manufacturabilitymanufacturability

– clock distributionclock distribution

Macroscopic issuesMacroscopic issues

– time-to-markettime-to-market

– design complexity design complexity (millions of gates)(millions of gates)

– high levels of high levels of abstractionsabstractions

– design for testdesign for test

– reuse and IP, portabilityreuse and IP, portability

– systems on a chip (SoC)systems on a chip (SoC)

– tool interoperabilitytool interoperabilityYearYear Tech.Tech. ComplexityComplexity FrequencyFrequency Staff SizeStaff Size Staff CostsStaff Costs

19971997 0.350.35 13 M Tr.13 M Tr. 400 MHz400 MHz 210210 $90 M$90 M

19981998 0.250.25 20 M Tr.20 M Tr. 500 MHz500 MHz 270270 $120 M$120 M

19991999 0.180.18 32 M Tr.32 M Tr. 600 MHz600 MHz 360360 $160 M$160 M

20022002 0.130.13 130 M Tr.130 M Tr. 800 MHz800 MHz 800800 $360 M$360 M

Integrated CircuitsIntegrated Circuits Digital logic is implemented using Digital logic is implemented using transistorstransistors in in integrated circuitsintegrated circuits

containing many gates.containing many gates.– small-scale integrated circuits (SSI) contain 10 gates or lesssmall-scale integrated circuits (SSI) contain 10 gates or less– medium-scale integrated circuits (MSI) contain 10-100 gatesmedium-scale integrated circuits (MSI) contain 10-100 gates– large-scale integrated circuits (LSI) contain up to 10large-scale integrated circuits (LSI) contain up to 1044 gates gates– very large-scale integrated circuits (VLSI) contain >10very large-scale integrated circuits (VLSI) contain >1044 gates gates

Improvements in manufacturing lead to ever smaller transistors Improvements in manufacturing lead to ever smaller transistors allowing more per chip.allowing more per chip.– >10>1077 gates/chip now possible; doubles every 18 months or so gates/chip now possible; doubles every 18 months or so

Variety of logic familiesVariety of logic families– TTL - transistor-transistor logicTTL - transistor-transistor logic– CMOS - complementary metal-oxide semiconductorCMOS - complementary metal-oxide semiconductor– ECL - emitter-coupled logicECL - emitter-coupled logic– GaAs - gallium arsenideGaAs - gallium arsenide

What are shown on previous diagrams cover only the so called front‑end What are shown on previous diagrams cover only the so called front‑end

processing ‑ fabrication steps that go towards forming the devices and processing ‑ fabrication steps that go towards forming the devices and

inter‑connections between these devices to produce the functioning IC's. The inter‑connections between these devices to produce the functioning IC's. The

end result are wafers each containing a regular array of the same IC chip or end result are wafers each containing a regular array of the same IC chip or

die. The wafer then has to be tested and the chips diced up and the good chips die. The wafer then has to be tested and the chips diced up and the good chips

mounted and wire‑bonded in different types of IC package and tested again mounted and wire‑bonded in different types of IC package and tested again

before being shipped out.before being shipped out.

From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall

Moore’sMoore’s Law Law Gordon E. Moore - Chairman Emeritus of Intel CorporationGordon E. Moore - Chairman Emeritus of Intel Corporation 1965 - observed trends in industry - 1965 - observed trends in industry - ## of transistors on ICs vs. release dates of transistors on ICs vs. release dates::

– Noticed number of transistors doubling with release of each new Noticed number of transistors doubling with release of each new IC generationIC generation

– release dates (separate generations) were all 18-24 months apartrelease dates (separate generations) were all 18-24 months apart Moore’s LawMoore’s Law::

– The number of transistors on an integrated circuit will double The number of transistors on an integrated circuit will double every 18 monthsevery 18 months

The level of integration of silicon technology as measured in terms of The level of integration of silicon technology as measured in terms of number of devices per number of devices per ICIC

This comes about in two ways – size reduction of the individual devices and This comes about in two ways – size reduction of the individual devices and increase in the chip or dice sizeincrease in the chip or dice size

As an indication of size reduction, it is interesting to note that feature size As an indication of size reduction, it is interesting to note that feature size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10whereas now all features are measured in mm’s (1 mm = 10-6-6 m or 10 m or 10-4-4 cm) cm)

Semiconductor industry has followed this prediction with surprising Semiconductor industry has followed this prediction with surprising accuracyaccuracy

• In 1965, Gordon Moore predicted that the number of transistors that can be In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 monthsintegrated on a die would double every 18 to 14 months

• i.e., grow exponentially with timei.e., grow exponentially with time

• Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.

– 2300 transistors, 1 MHz clock (Intel 4004) - 19712300 transistors, 1 MHz clock (Intel 4004) - 1971

– 42 Million, 2 GHz clock (Intel P4) - 200142 Million, 2 GHz clock (Intel P4) - 2001

– 140 Million transistor (HP PA-8500)140 Million transistor (HP PA-8500)

Moore’s LawMoore’s Law

Source: Intel web page (www.intel.com)

Moore’s LawMoore’s Law From Intel’s 4040 (2300 transistors) to Pentium II From Intel’s 4040 (2300 transistors) to Pentium II

(7,500,000 transistors) and beyond(7,500,000 transistors) and beyond

Relative sizes of ICs in graph

Ever since the invention of integrated circuit, the smallest feature size has been Ever since the invention of integrated circuit, the smallest feature size has been reducing every year. Currently (2002) the smallest feature size is about 0.13 reducing every year. Currently (2002) the smallest feature size is about 0.13 micron. At the same time the number transistors per chip is increasing due to micron. At the same time the number transistors per chip is increasing due to feature size reduction and increase in chip area. Classic example is the case of feature size reduction and increase in chip area. Classic example is the case of memory chips: Gordon Moore of Intel in early 1970s found that: “density” (bits per memory chips: Gordon Moore of Intel in early 1970s found that: “density” (bits per chip) growing at the rate of four times in 3 to 4 years - often referred to as Moore’s chip) growing at the rate of four times in 3 to 4 years - often referred to as Moore’s Law. In subsequent years, the pace slowed down a bit, Law. In subsequent years, the pace slowed down a bit, data density has doubled data density has doubled approximately every 18 months – current definition of Moore’s Lawapproximately every 18 months – current definition of Moore’s Law..

Limits of Moore’s Law?Limits of Moore’s Law?

Growth expected until 30 nm gate length (currently: 180 nm)Growth expected until 30 nm gate length (currently: 180 nm)

– size halved every 18 mos. - reached in size halved every 18 mos. - reached in 2001 + 1.5 log2((180/30)2) = 2009

– what then?what then? Paradigm shift needed in fabrication processParadigm shift needed in fabrication process

Technological Background of the Technological Background of the Moore’s LawMoore’s Law

To accommodate this change, the size of the silicon To accommodate this change, the size of the silicon wafers on which the integrated circuits are fabricated wafers on which the integrated circuits are fabricated have also increased by a very significant factor – from have also increased by a very significant factor – from the 2 and 3 in diameter wafers to the 8 inthe 2 and 3 in diameter wafers to the 8 in (200 mm) and (200 mm) and 12 in (300 mm) diameter wafers12 in (300 mm) diameter wafers

The latest catch phrase in semiconductor technology (as The latest catch phrase in semiconductor technology (as well as in other material science) is nanotechnology – well as in other material science) is nanotechnology – usually referring to GaAs devices based on quantum usually referring to GaAs devices based on quantum mechanical phenomenamechanical phenomena

These devices have feature size (such as film thickness, These devices have feature size (such as film thickness, line width etc) measured in nanometres or 10line width etc) measured in nanometres or 10-9 -9 metresmetres

Recurring CostsRecurring Costs cost of die + cost of die test + cost of packagingcost of die + cost of die test + cost of packagingvariable cost = variable cost = --------------------------------------------------------------------------------------------------------------------------------

final test yieldfinal test yield

cost of wafercost of wafercost of die = -----------------------------------cost of die = -----------------------------------

dies per waferdies per wafer ×× die yielddie yield

× (wafer diameter/2)× (wafer diameter/2)22 × wafer diameter× wafer diameterdies per waferdies per wafer = ---------------------------------- = ---------------------------------- ------------------------------------------------------ die area die area 2 2 × die area × die area

die yielddie yield = (1 + (defects per unit area = (1 + (defects per unit area ×× die area)/ die area)/))--

Yield ExampleYield Example Example

wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, = 3 (measure of manufacturing process complexity)

252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area proportional to the third or fourth power of the die area

Intel 4004 MicroprocessorIntel 4004 Microprocessor

Intel Pentium (IV) MicroprocessorIntel Pentium (IV) Microprocessor

Die Size GrowthDie Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010

Year

Die

siz

e (m

m)

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

Clock FrequencyClock FrequencyLead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years

P6

Pentium ® proc486

38628680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Fre

qu

ency

(M

hz)

2X every 2 years

Courtesy, Intel

Examples of Cost Metrics (1994)Examples of Cost Metrics (1994)

ChipChip Metal Metal layerslayers

Line Line widthwidth

Wafer Wafer costcost

Defects/Defects/cmcm22

Area Area (mm(mm22))

Dies/Dies/waferwafer

YieldYield Die Die costcost

386DX386DX 22 0.900.90 $900$900 1.01.0 4343 360360 71%71% $4$4

486DX2486DX2 33 0.800.80 $1200$1200 1.01.0 8181 181181 54%54% $12$12

PowerPC PowerPC 601601

44 0.800.80 $1700$1700 1.31.3 121121 115115 28%28% $53$53

HP PA HP PA 71007100

33 0.800.80 $1300$1300 1.01.0 196196 6666 27%27% $73$73

DEC DEC AlphaAlpha

33 0.700.70 $1500$1500 1.21.2 234234 5353 19%19% $149$149

Super Super SPARCSPARC

33 0.700.70 $1700$1700 1.61.6 256256 4848 13%13% $272$272

PentiumPentium 33 0.800.80 $1500$1500 1.51.5 296296 4040 9%9% $417$417

VLSIVLSI

Very Large Scale IntegrationVery Large Scale Integration– design/manufacturing of extremely small, complex circuitry design/manufacturing of extremely small, complex circuitry

using modified semiconductor materialusing modified semiconductor material

– integrated circuit (IC) may contain millions of transistors, integrated circuit (IC) may contain millions of transistors, each a few each a few m in sizem in size

– applications wide ranging: most electronic logic devicesapplications wide ranging: most electronic logic devices

Origins of VLSIOrigins of VLSI Much development motivated by WWII need for improved Much development motivated by WWII need for improved

electronics, especially for radarelectronics, especially for radar 1940 - Russell Ohl (Bell Laboratories) - first pn junction1940 - Russell Ohl (Bell Laboratories) - first pn junction 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) -

first transistorfirst transistor

– 1956 Nobel Physics Prize1956 Nobel Physics Prize Late 1950s - purification of Si advances to acceptable Late 1950s - purification of Si advances to acceptable

levels for use in electronicslevels for use in electronics 1958 - Seymour Cray (Control Data Corporation) - first 1958 - Seymour Cray (Control Data Corporation) - first

transistorized computer - CDC 1604transistorized computer - CDC 1604

Origins of VLSIOrigins of VLSI (Cont.) (Cont.)

1959 - Jack St. Claire Kilby (Texas Instruments) - first 1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mmintegrated circuit - 10 components on 9 mm22

1959 - Robert Norton Noyce (founder, Fairchild 1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuitSemiconductor) - improved integrated circuit

1968 - Noyce, Gordon E. Moore found Intel1968 - Noyce, Gordon E. Moore found Intel 1971 - Ted Hoff (Intel) - first microprocessor (4004) - 1971 - Ted Hoff (Intel) - first microprocessor (4004) -

2300 transistors on 9 mm2300 transistors on 9 mm22

Since then - continued improvement in technology has Since then - continued improvement in technology has allowed for increased performance as predicted by allowed for increased performance as predicted by Moore’s LawMoore’s Law

Three Dimensional VLSIThree Dimensional VLSI

The fabrication of a single integrated circuit whose functional The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensionsparts (transistors, etc) extend in three dimensions

The vertical orientation of several bare integrated circuits in a The vertical orientation of several bare integrated circuits in a single packagesingle package

Advantages of 3D VLSIAdvantages of 3D VLSI

Speed - the time required for a signal to travel between the functional circuit Speed - the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced.blocks in a system (delay) reduced.

– Delay depends on resistance/capacitance of interconnectionsDelay depends on resistance/capacitance of interconnections

– resistance proportional to interconnection lengthresistance proportional to interconnection length

Advantages of 3D VLSIAdvantages of 3D VLSI

Noise - unwanted disturbances on a useful signalNoise - unwanted disturbances on a useful signal

– reflection noise (varying impedance along interconnect)reflection noise (varying impedance along interconnect)

– crosstalk noise (interference between interconnects)crosstalk noise (interference between interconnects)

– electromagnetic interference (EMI) (caused by current in pins)electromagnetic interference (EMI) (caused by current in pins) 3D chips3D chips

– fewer, shorter interconnectsfewer, shorter interconnects

– fewer pinsfewer pins

Advantages of 3D VLSIAdvantages of 3D VLSI

Power consumptionPower consumption

– power used charging an interconnect capacitancepower used charging an interconnect capacitance

» P = fCV2

– power dissipated through resistive materialpower dissipated through resistive material

» P = V2/R

– capacitance/resistance proportional to lengthcapacitance/resistance proportional to length

– reduced interconnect lengths will reduce powerreduced interconnect lengths will reduce power

Advantages of 3D VLSIAdvantages of 3D VLSI

Interconnect capacity (connectivity)Interconnect capacity (connectivity)

– more connections between chipsmore connections between chips

– increased functionality, ease of designincreased functionality, ease of design

Advantages of 3D VLSIAdvantages of 3D VLSI

Printed circuit board size/weightPrinted circuit board size/weight

– planar size of PCB reduced with negligible IC height increaseplanar size of PCB reduced with negligible IC height increase

– weight reduction due to more circuitry per package/smaller PCBsweight reduction due to more circuitry per package/smaller PCBs

– estimated 40-50 times reduction in size/weightestimated 40-50 times reduction in size/weight

3D VLSI - Challenges and Solutions3D VLSI - Challenges and Solutions

Challenge: Thermal managementChallenge: Thermal management

– smaller packagessmaller packages

– increased circuit density increased circuit density

– increased power densityincreased power density Solutions:Solutions:

– circuit layout (design stage)circuit layout (design stage)» high power sections uniformly distributed

– advancement in cooling techniquesadvancement in cooling techniques (heat pipes) (heat pipes)

Influential Participants - IndustryInfluential Participants - Industry

Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others...Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others...

– high density memorieshigh density memories AT&TAT&T

– high density “multiprocessor”high density “multiprocessor” Many other applications/participantsMany other applications/participants

Three Dimensional VLSIThree Dimensional VLSI

Moore’s Law approaching physical limitMoore’s Law approaching physical limit Increased performance expected by marketIncreased performance expected by market Paradigm shift needed - 3D VLSIParadigm shift needed - 3D VLSI

– many advantages over 2D VLSImany advantages over 2D VLSI

– economic limitations of fabrication overhaul will be overcome by economic limitations of fabrication overhaul will be overcome by market demandmarket demand

Three Dimensional VLSI may be the savior of Moore’s LawThree Dimensional VLSI may be the savior of Moore’s Law