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Apr 10, 2015
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JBTech INDIAVLSI Design Solutions and Project TrainingGreater Noida (UP) - [email protected]
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JBTech INDIA is Greater
Noida Based VLSI Design
Solutions and Project
Training Company
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What is VLSIAs cmos process technology
improves transistors continue to
get smaller and ICs hold more and
more transistors.
" Larger the integration smaller is
the size“
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VLSI Offers
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The era of VLSI now offers 64- bit
microprocessors complete with
"cache memory" and "floating
point arithmetic units" Containing
well over a million Transistors on a
single piece of silicon
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How an IC is build1. Wafer Preparation
2. Design
3. Fabrication
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1. Wafer PreparationBefore the long process of creating an integrated circuit can begin, a wafer of semiconductor material must first be manufactured. Thisessential substrate is the ultimate foundation upon which all integrated circuits are created.
Basic Steps of Silicon Wafer Manufacturing and Preparation steps outlined below.
Thickness Sorting and Flatness CheckingLapping & Etching Processes
Crystal Growth and Wafer Slicing ProcessObtaining the sandPreparing the molten silicon bath Making the ingot Preparing the wafers
Polishing ProcessFinal Dimensional and Electrical Properties Qualification
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2. Digital Design flowSpecificationDesign EntryPre synthesis simulationSynthesisPost Synthesis SimulationDFT InsertionStatic Timing analysisFloor planningPlacement and RoutingLayout validationDeep sub micron validation
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Top down Design Flow
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Logic Description (Verilog , VHDL)
Logic synthesisTechnology independent optimizationTechnology mapping
Logic Circuit (cell level netlist)
Layoutcell placement , routing
Mask data for chip fabrication
Cell Library Nand, nor, xor ,inv , DFF
Design Constraints (delay , area…)
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Design Entry Simulation Synthesis
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Semiconductor device fabrication is the process used to create chips. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconductingmaterial. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors.
3. What is Fabrication
Mask 1 defines the areas in which the deep p-well diffusions are to take place on an n-type substrate .Mask 2 defines the thinox (or diffusion) regions, namely, those areas where the thick oxide is to be stripped and thin oxide grown to accommodate p and n-transistors and wiresMask 3 is used to pattern the polysilicon layer that is deposited after the thin oxide
Mask 4 is a p-plus mask used to define all areas where p diffusion is to take place.
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(cont…)Mask 5 is usually performed using the negative form of the p-plus mask and defines those areas where n-type diffusion is to take place.Mask 6 defines contact cuts .Mask 7 defines the metal layer patternMask 8 is an overall passivation layer that is required to define the openings for access to bonding pads .
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Si substrate
Si substrate
Si substrate
Si substrate
Si substrate
Si substrate
(a)
(b)
(c)
(d)
(e)
(f)
SiO2
SiO2
SiO2
thinox
SiO2
thinox
polysilicon
SiO2
thinox
polysilicon
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Wafer preparation and fabrication are not done in INDIA
except SCL
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VLSI Design
in
INDIA
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India was projected as a software super power, But it has now set its sights on becoming an all-round IT super source as India’s VLSI design engineers join hands with their software developer brethren.
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Presently there are more than 400 design Center in India, Forecasting need of large no VLSI Designer in future
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The growing dependence on Indian VLSI Design professionals promises a significant opportunity in this area
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Major Global VLSI MNCs in INDIA
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intel
ST Microelectronics
Texas Instruments
Motorola (Freescale)
Virage Logic
Qualcom
AMD
Altera
ARM
Cypress Semiconductor
Infineon
KPIT cummins
LSI Technology
Magma Design Automation
Mentor Graphics
Sasken
Synopsys
Cadence
NXP
Xilinx
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VLSI Design
in
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Services1. Industrial Project Training2. PG Diploma 3. Short term courses
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1. Industrial Project TrainingThis includes training in HDL coding , shell/perl scripting and then starting with spec. definition of project with our industry expert panel. Project is done in structured process (Spec. definition, Feasibility Analysis, Arch. Development, HDL Coding, Code Validation/Verification strategy, Synthesis, Project closure).
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2.1 Industrial Project Training flow
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2. Short Term CoursesVerilog, VHDL, Basics of MOS & Semiconductor Physics, Introduction to spice with MOS, Digital CMOS Designing With Spice + Layout, Analog Designing with Spice + Layout, ASIC Design Flow, Perl/Shell scripting , customized solutions…
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3. PG DiplomaThis will include most of the aspects of VLSI (Digital/Analog Design, HDL Coding, Synthesis, Simulations, DFT Concepts, Timing definitions and constraints, Layout, Spice Simulations, Tcl/Perl Programming). Along with this a INDUSTRY level project is done. Durations for 4-6 Month. We help for placement after this Module.
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3.1 PG Diploma flow
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FacilitiesModern EDA ToolsFPGA BoardWell Furnished Library Interaction with Industry Experts Live Projects