VERTAF: An Application VERTAF: An Application Framework for Design and Framework for Design and Verification of Embedded Verification of Embedded Real-Time Software Real-Time Software Pao-Ann Hsiung, Shang-Wei Lin, Chih- Pao-Ann Hsiung, Shang-Wei Lin, Chih- Hao Tseng, Trong-Yen Lee, Jih-Ming Fu Hao Tseng, Trong-Yen Lee, Jih-Ming Fu and Win-Bin See and Win-Bin See
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VERTAF: An Application Framework for Design and Verification of Embedded Real-Time Software Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee,
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VERTAF: An Application Framework for VERTAF: An Application Framework for Design and Verification of Embedded Design and Verification of Embedded
Real-Time Software Real-Time Software
Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu and Win-Bin SeeTrong-Yen Lee, Jih-Ming Fu and Win-Bin See
ContentsContents
IntroductionIntroduction
Design and Verification FlowDesign and Verification Flow
- Guarantees satisfaction of temporal & spatial - Guarantees satisfaction of temporal & spatial constraintsconstraints
Formal Verification:Formal Verification:
- checks if system satisfies user-given or system-defined - checks if system satisfies user-given or system-defined generic propertiesgeneric properties
Code Generation:Code Generation:
- produce efficient portable code- produce efficient portable code
Design and Verification FlowDesign and Verification Flow
Software synthesis has two phasesSoftware synthesis has two phases
Used for scheduling different tasks performed by Used for scheduling different tasks performed by objectsobjects
Show how a user should use the systemShow how a user should use the system Added state-markers:Added state-markers:
- They relate the sequence diagram to the corresponding - They relate the sequence diagram to the corresponding state in the timed state chartstate in the timed state chart
SchedulingScheduling
Generate Petri nets from UML diagramsGenerate Petri nets from UML diagrams
Algorithms usedAlgorithms used
- Without RTOS ( Quasi Dynamic Scheduling) - Without RTOS ( Quasi Dynamic Scheduling)
-- Single real-time kernel -- Single real-time kernel
- With RTOS (Extended Quasi Static Scheduling)- With RTOS (Extended Quasi Static Scheduling)
- OS with middleware layer- OS with middleware layer
- Scheduler- Scheduler
VERTAF ComponentsVERTAF Components
Experimental ResultsExperimental Results
Two Applications:Two Applications: - Avionics- Avionics
-- 24 tasks -- 24 tasks -- 45 objects were found-- 45 objects were found -AICC (Autonomous Intelligent Cruise Controller)-AICC (Autonomous Intelligent Cruise Controller) -- 12 tasks-- 12 tasks -- 21 objects were found-- 21 objects were found
Time taken to developTime taken to develop - Avionics - Avionics -- Without VERTAF : 5 weeks-- Without VERTAF : 5 weeks -- Using VERTAF : 1 week-- Using VERTAF : 1 week - AICC- AICC -- Without VERTAF : 20 days-- Without VERTAF : 20 days -- Using VERTAF : 5 days-- Using VERTAF : 5 days
AICC Call GraphAICC Call Graph
ConclusionsConclusions
VERTAF integrates 3 different technologiesVERTAF integrates 3 different technologies
New specification languages can be easily New specification languages can be easily integrated into it.integrated into it.
More advanced features like network delay, More advanced features like network delay, network protocols will be considered in future network protocols will be considered in future workwork