VCS MX/VCS MXi User Guide - inst.eecs.berkeley.edueecs151/sp18/files/vcsmx_ug.pdfG-2012.09 September 2012 ... AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS,

VCS MX/VCS MXi User GuideG-2012.09September 2012

Comments?E-mail your comments about this manual to:[email protected].

mailto:[email protected]

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Copyright Notice and Proprietary InformationCopyright 2012 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

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Contents

1. Getting Started

Simulator Support with Technologies . . . . . . . . . . . . . . . . . . . . . 1-2

Setting Up the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Verifying Your System Configuration . . . . . . . . . . . . . . . . . . . 1-4

Obtaining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Setting Up Your Environment. . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Setting Up Your C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Creating a synopsys_sim.setup File . . . . . . . . . . . . . . . . . . . 1-8

The Concept of a Library In VCS MX. . . . . . . . . . . . . . . . 1-10

Library Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Including Other Setup Files . . . . . . . . . . . . . . . . . . . . . . . 1-12

Using SYNOPSYS_SIM_SETUP Environment Variable . 1-12

Displaying Setup Information. . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Displaying Design Information Analyzed Into a Library . . . . . 1-14

Using the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Basic Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Default Time Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-18

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2. VCS MX Flow

Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Using vhdlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Commonly Used Analysis Options . . . . . . . . . . . . . . . . . . 2-3

Using vlogan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Commonly Used Analysis Options . . . . . . . . . . . . . . . . . . 2-6

Analyzing the Design to Different Libraries . . . . . . . . . . . . . . 2-13

Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Commonly Used Options . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Commonly Used Runtime Options. . . . . . . . . . . . . . . . . . . . . 2-19

3. Elaborating the Design

Compiling or Elaborating the Design in Debug Mode . . . . . . . . . 3-1

Compiling or Elaborating the Design in Optimized Mode . . . . . . 3-2

Key Elaboration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Initializing Verilog Memories and Registers . . . . . . . . . . . . . . 3-3

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Overriding Generics and Parameters . . . . . . . . . . . . . . . . . . 3-6

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Checking for X and Z Values In Conditional Expressions . . . 3-8

Enabling the Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Filtering Out False Negatives . . . . . . . . . . . . . . . . . . . . . . 3-10

v

Cross Module References (XMRs) . . . . . . . . . . . . . . . . . . . . 3-12

hdl_xmr Procedure and $hdl_xmr System Task. . . . . . . . 3-13

Data Types Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

VHDL Referencing Verilog using hdl_xmr procedure. . . . 3-14

Verilog Referencing VHDL objects using $hdl_xmr . . . . . 3-16

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

$hdl_xmr Support for VHDL Variables . . . . . . . . . . . . . . . 3-18

Datatype Support and Usage Examples . . . . . . . . . . . . . 3-19

VCS MX V2K Configurations and Libmaps . . . . . . . . . . . . . . 3-24

Library Mapping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

Using -liblist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

Evaluating the Active Events When Limiting the Exposure of Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

Lint Warning Message for Missing endcelldefine . . . . . . . . . 3-39

Error/Warning Message Control . . . . . . . . . . . . . . . . . . . . . . 3-43

Controlling Error Messages . . . . . . . . . . . . . . . . . . . . . . . 3-45

Controlling Warning Messages . . . . . . . . . . . . . . . . . . . . 3-45

Controlling Lint Messages . . . . . . . . . . . . . . . . . . . . . . . . 3-47

Suppressing Lint, Warning, and Error Messages. . . . . . . 3-48

Error Conditions and Messages That Cannot Be Disabled 3-48

Using Message Control Options Together . . . . . . . . . . . . 3-49

Message Control Examples . . . . . . . . . . . . . . . . . . . . . . . 3-49

Obsolete Compile-Time Options for Controlling Messages 3-59

4. Simulating the Design

Using DVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

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Using UCLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

ucli2Proc Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Options for Debugging Using DVE and UCLI . . . . . . . . . . . . . . . 4-6

Key Runtime Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Overriding Generics at Runtime. . . . . . . . . . . . . . . . . . . . . . . 4-8

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Passing Values from the Runtime Command Line . . . . . . . . 4-12

VCS MX Supports simv -f . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Specifying a Long Time Before Stopping The Simulation . . . 4-15

5. Diagnostics

Using Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Using diag Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Using Smartlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Compile-time Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Libconfig Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Timescale Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Runtime Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Diagnostics for VPI/VHPI PLI Applications . . . . . . . . . . . . . . 5-12

Keeping the UCLI/DVE Prompt Active After a Runtime Error 5-15

UCLI Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

DVE Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

UCLI Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

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Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

Diagnosing Quickthread Issues in SystemC . . . . . . . . . . . . . 5-21

Quickthread Overruns Its Allocated Stack . . . . . . . . . . . . 5-22

Simulation Runs Out of Memory Due to Quickthread Stacks 5-23

Reducing or Turning Off Redzones . . . . . . . . . . . . . . . . . 5-24

Post-processing Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

Using the vpdutil Utility to Generate Statistics . . . . . . . . . . . . 5-25

The vpdutil Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

6. VCS Multicore Technology Application Level Parallelism

VCS Multicore Technology Options. . . . . . . . . . . . . . . . . . . . . . . 6-30

Use Model for Assertion Simulation. . . . . . . . . . . . . . . . . . . . 6-32

Use Model for Toggle and Functional Coverage . . . . . . . . . . 6-32

Use Model for VPD Dumping. . . . . . . . . . . . . . . . . . . . . . . . . 6-32

Running VCS Multicore Simulation . . . . . . . . . . . . . . . . . . . . . . . 6-33

Assertion Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34

Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35

VPD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37

Parallel SAIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38

Customary SAIF System Function Entries. . . . . . . . . . . . . . . 6-38

Enabling Parallel SAIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

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7. VPD, VCD, and EVCD Utilities

Advantages of VPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Dumping a VPD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Using System Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Enable and Disable Dumping. . . . . . . . . . . . . . . . . . . . . . 7-4

Override the VPD Filename . . . . . . . . . . . . . . . . . . . . . . . 7-7

Dump Multi-dimensional Arrays and Memories . . . . . . . . 7-8

Using $vcdplusmemorydump . . . . . . . . . . . . . . . . . . . . . . 7-17

Capture Delta Cycle Information . . . . . . . . . . . . . . . . . . . 7-18

Dumping an EVCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Post-processing Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23

The vcdiff Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

The vcdiff Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

The vcat Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

The vcat Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Generating Source Files From VCD Files . . . . . . . . . . . . 7-36

Writing the Configuration File . . . . . . . . . . . . . . . . . . . . . . 7-38

The vcsplit Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

The vcsplit Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

The vcd2vpd Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46

Options for specifying EVCD options . . . . . . . . . . . . . . . . 7-47

The vpd2vcd Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48

The Command File Syntax. . . . . . . . . . . . . . . . . . . . . . . . 7-54

The vpdmerge Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57

The vpdutil Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61

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8. Performance Tuning

Compile-time Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Compile Once and Run Many Times . . . . . . . . . . . . . . . . . . . 8-4

Parallel Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Runtime Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Using Radiant Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Compiling With Radiant Technology. . . . . . . . . . . . . . . . . 8-6

Applying Radiant Technology to Parts of the Design . . . . 8-6

Improving Performance When Using PLIs. . . . . . . . . . . . . . . 8-15

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

Impact on Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

Obtaining VCS Consumption of CPU Resources . . . . . . . . . . . . 8-20

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

Compile time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

9. Gate-level Simulation

SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Using Unified SDF Feature . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Using $sdf_annotate System Task. . . . . . . . . . . . . . . . . . . . . 9-3

Using -xlrm Option for SDF Retain, Gate Pulse Propagation, and Gate Pulse Detection Warning . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Using Optimistic Mode in SDF . . . . . . . . . . . . . . . . . . . . . 9-6

Using Gate Pulse Propagation . . . . . . . . . . . . . . . . . . . . . 9-7

Generating Warnings During Gate Pulses . . . . . . . . . . . . 9-8

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Precompiling an SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

Creating the Precompiled Version of the SDF file . . . . . . 9-9

SDF Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Delay Objects and Constructs . . . . . . . . . . . . . . . . . . . . . 9-11

SDF Configuration File Commands . . . . . . . . . . . . . . . . . 9-12

approx_command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

mtm_command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

scale_command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

SDF Example with Configuration File. . . . . . . . . . . . . . . . 9-15

Delays and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

Transport and Inertial Delays. . . . . . . . . . . . . . . . . . . . . . . . . 9-18

Different Inertial Delay Implementations . . . . . . . . . . . . . 9-20

Enabling Transport Delays . . . . . . . . . . . . . . . . . . . . . . . . 9-22

Pulse Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23

Pulse Control with Transport Delays . . . . . . . . . . . . . . . . . . . 9-25

Pulse Control with Inertial Delays. . . . . . . . . . . . . . . . . . . 9-27

Specifying Pulse on Event or Detect Behavior . . . . . . . . . 9-32

Specifying the Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36

Using the Configuration File to Disable Timing . . . . . . . . . . . . . . 9-38

Using the timopt Timing Optimizer . . . . . . . . . . . . . . . . . . . . . . . 9-38

Editing the timopt.cfg File . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41

Editing Potential Sequential Device Entries . . . . . . . . . . . 9-41

Editing Clock Signal Entries . . . . . . . . . . . . . . . . . . . . . . . 9-42

Using Scan Simulation Optimizer . . . . . . . . . . . . . . . . . . . . . . . 9-43

ScanOpt Config File Format . . . . . . . . . . . . . . . . . . . . . . . . . 9-44

ScanOpt Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45

xi

Negative Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46

The Need for Negative Value Timing Checks . . . . . . . . . . . . 9-47

The $setuphold Timing Check Extended Syntax . . . . . . . 9-52

Negative Timing Checks for Asynchronous Controls . . . . 9-55

The $recrem Timing Check Syntax . . . . . . . . . . . . . . . . . 9-56

Enabling Negative Timing Checks . . . . . . . . . . . . . . . . . . . . . 9-58

Other Timing Checks Using the Delayed Signals . . . . . . . . . 9-59

Checking Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-63

Toggling the Notifier Register. . . . . . . . . . . . . . . . . . . . . . . . . 9-64

SDF Back-annotation to Negative Timing Checks. . . . . . . . . 9-65

How VCS MX Calculates Delays . . . . . . . . . . . . . . . . . . . . . . 9-66

Using Multiple Non-overlapping Violation Windows. . . . . . . . 9-68

Using VITAL Models and Netlists . . . . . . . . . . . . . . . . . . . . . . . . 9-73

Validating and Optimizing a VITAL Model . . . . . . . . . . . . . . . 9-73

Validating the Model for VITAL Conformance . . . . . . . . . 9-74

Verifying the Model for Functionality . . . . . . . . . . . . . . . . 9-74

Optimizing the Model for Performance and Capacity. . . . 9-75

Re-Verifying the Model for Functionality. . . . . . . . . . . . . . 9-76

Understanding Error and Warning Messages . . . . . . . . . 9-76

Distributing a VITAL Model. . . . . . . . . . . . . . . . . . . . . . . . 9-77

Simulating a VITAL Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-78

Applying Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-78

Overriding Generic Parameter Values . . . . . . . . . . . . . . . 9-78

Understanding VCS MX Error Messages. . . . . . . . . . . . . 9-80

Viewing VITAL Subprograms . . . . . . . . . . . . . . . . . . . . . . 9-81

Timing Back-annotation . . . . . . . . . . . . . . . . . . . . . . . . . . 9-81

VCS MX Naming Styles . . . . . . . . . . . . . . . . . . . . . . . . . . 9-81

Negative Constraints Calculation (NCC) . . . . . . . . . . . . . 9-82

xii

Simulating in Functional Mode . . . . . . . . . . . . . . . . . . . . . 9-83

Understanding VITAL Timing Delays and Error Messages . . 9-85

Negative Constraint Calculation (NCC) . . . . . . . . . . . . . . 9-85

Conformance Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-85

Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-88

10.Coverage

Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

Options For Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

11. Using SystemVerilog

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Using UVM With VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

Update on UVM-1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Update on UVM-EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Natively Compiling and Elaborating UVM-1.0 . . . . . . . . . . . . 11-5

Natively Compiling and Elaborating UVM-1.1a . . . . . . . . . . . 11-5

Compiling the External UVM Library . . . . . . . . . . . . . . . . . . . 11-6

Using the -ntb_opts uvm Option. . . . . . . . . . . . . . . . . . . . 11-7

Explicitly Specifying UVM Files and Arguments . . . . . . . . 11-7

Accessing HDL Registers Through UVM Backdoor. . . . . . . . 11-8

Generating UVM Register Abstraction Layer Code . . . . . . . . 11-9

Recording UVM Transactions . . . . . . . . . . . . . . . . . . . . . . . . 11-10

UVM Template Generator (uvmgen) . . . . . . . . . . . . . . . . . . . 11-11

Using Mixed VMM/UVM Libraries . . . . . . . . . . . . . . . . . . . . . 11-12

xiii

Migrating from OVM to UVM . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

Where to Find UVM Examples. . . . . . . . . . . . . . . . . . . . . . . . 11-14

Where to Find UVM Documentation . . . . . . . . . . . . . . . . . . . 11-14

UVM-1.1a Documentation . . . . . . . . . . . . . . . . . . . . . . . . 11-14

UVM-1.0 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

UVM-VMM Interop Documentation . . . . . . . . . . . . . . . . . 11-15

Using VMM with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

Using OVM with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16

Native Compilation and Elaboration of OVM 2.1.2 . . . . . . . . 11-16

Compiling the External OVM Library . . . . . . . . . . . . . . . . . . . 11-18

Using the -ntb_opts ovm Option. . . . . . . . . . . . . . . . . . . . 11-18

Explicitly Specifying OVM Files and Arguments. . . . . . . . 11-18

Recording OVM Transactions . . . . . . . . . . . . . . . . . . . . . . . . 11-19

Running Native OVM Code in Partition Compile Flow. . . . . . 11-21

Debugging SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . 11-23

Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23

Newly implemented SystemVerilog Constructs . . . . . . . . . . . . . . 11-25

Support for Aggregate Methods in Constraints Using the withConstruct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25

Debugging During Initialization SystemVerilog Static Functions and Tasks in Module Definitions . . . . . . . . . . . . . . . . . . . . . . . 11-26

Explicit External Constraint Blocks . . . . . . . . . . . . . . . . . . . . 11-30

Generate Constructs in Program Blocks . . . . . . . . . . . . . . . . 11-33

Error Condition for Using a Genvar Outside of its Generate Block11-35

Randomizing Unpacked Structs. . . . . . . . . . . . . . . . . . . . . . . 11-36

xiv

Using the Scope Randomize Method std::randomize() . . 11-37

Using the Class Randomize Method randomize() . 11-41

Disabling and Re-enabling Randomization . . . . . . . . . . . 11-44

Using In-line Random Variable Control . . . . . . . . . . . . . . 11-48

Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52

Making wait fork Statements Compliant with the SV LRM. . . 11-52

Making disable fork Statements Compliant with the SV LRM 11-55

Recently Implemented SystemVerilog Constructs. . . . . . . . . . . . 11-56

The std::randomize() Function . . . . . . . . . . . . . . . . . . . . . . . . 11-57

SystemVerilog Bounded Queues. . . . . . . . . . . . . . . . . . . . . . 11-60

wait() Statement with a Static Class Member Variable. . . . . . 11-61

Parameters and Localparams in Classes . . . . . . . . . . . . . . . 11-62

SystemVerilog Math Functions . . . . . . . . . . . . . . . . . . . . . . . 11-62

Streaming Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63

Packing (Used on RHS) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63

Unpacking (Used on LHS) . . . . . . . . . . . . . . . . . . . . . . . . 11-64

Packing and Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . 11-64

Propagation and force Statement. . . . . . . . . . . . . . . . . . . 11-64

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65

Structures with Streaming Operators . . . . . . . . . . . . . . . . 11-65

Extensions to SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65

Unique/Priority Case/IF Final Semantic Enhancements . . . . 11-66

Using Unique/Priority Case/If with Always Block or Continuous Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67

Using Unique/Priority Inside a Function . . . . . . . . . . . . . . 11-70

System Tasks to Control Warning Messages. . . . . . . . . . 11-73

Single-Sized Packed Dimension Extension. . . . . . . . . . . . . . 11-74

xv

Covariant Virtual Function Return Types . . . . . . . . . . . . . . . . 11-77

Self Instance of a Virtual Interface . . . . . . . . . . . . . . . . . . . . . 11-78

UVM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-80

Error Condition for Using a Genvar Outside of its Generate Block 11-81

Exporting a SystemVerilog Package . . . . . . . . . . . . . . . . . . . . . . 11-82

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-83

Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-85

Using a Package in a SystemVerilog Module, Program, and Interface Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-87

12.Using OpenVera Native Testbench

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

Importing VHDL Procedures . . . . . . . . . . . . . . . . . . . . . . 12-6

Exporting OpenVera Tasks. . . . . . . . . . . . . . . . . . . . . . . . 12-8

Using Template Generator . . . . . . . . . . . . . . . . . . . . . . . 12-9

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22

Multiple Program Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22

Configuration File Model . . . . . . . . . . . . . . . . . . . . . . . . . 12-23

Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23

Usage Model for Multiple Programs. . . . . . . . . . . . . . . . . 12-24

NTB Options and the Configuration File. . . . . . . . . . . . . . 12-25

Separate Compilation of Testbench Files . . . . . . . . . . . . . . . 12-27

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29

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Class Dependency Source File Reordering. . . . . . . . . . . . . . 12-29

Circular Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31

Dependency-based Ordering in Encrypted Files . . . . . . . 12-32

Using Encrypted Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32

Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33

Using Reference Verification Methodology . . . . . . . . . . . . . . 12-33

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35

13.Aspect Oriented Extensions

Aspect-Oriented Extensions in SV. . . . . . . . . . . . . . . . . . . . . 13-3

Processing of AOE as a Precompilation Expansion . . . . . . . 13-5

Weaving advice into the target method . . . . . . . . . . . . . . 13-10

Pre-compilation Expansion details. . . . . . . . . . . . . . . . . . . . . 13-15

Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

14.Using Constraints

Inconsistent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Constraint Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

Randomize Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Solver Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Constraint Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

Test Case Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

Using multiple +ntb_solver_debug arguments . . . . . . . . . . . 14-15

Summary for +ntb_solver_debug. . . . . . . . . . . . . . . . . . . . . . 14-15

+ntb_solver_debug=serial . . . . . . . . . . . . . . . . . . . . . . . . 14-15

+ntb_solver_debug=trace. . . . . . . . . . . . . . . . . . . . . . . . . 14-16

xvii

+ntb_solver_debug=profile. . . . . . . . . . . . . . . . . . . . . . . . 14-16

+ntb_solver_debug=extract . . . . . . . . . . . . . . . . . . . . . . . 14-16

Constraint Debug Using DVE . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

Constraint Guard Error Suppression . . . . . . . . . . . . . . . . . . . . . . 14-17

Error Message Suppression Limitations . . . . . . . . . . . . . . . . 14-18

Flattening Nested Guard Expressions . . . . . . . . . . . . . . . 14-18

Pushing Guard Expressions into Foreach Loops . . . . . . . 14-19

Array and XMR Support in std::randomize() . . . . . . . . . . . . . . . . 14-20

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

XMR Support in Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

XMR Function Calls in Constraints . . . . . . . . . . . . . . . . . . . . 14-24

State Variable Index in Constraints . . . . . . . . . . . . . . . . . . . . . . . 14-25

Runtime Check for State Versus Random Variables . . . . . . . 14-25

Array Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

Using Soft Constraints in SystemVerilog . . . . . . . . . . . . . . . . . . . 14-26

Using Soft Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27

Soft Constraint Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

Within a Single Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

Soft Constraints Defined in Classes Instantiated as rand Members in Another Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29

Soft Constraints Inheritance Between Classes . . . . . . . . . . . 14-31

Soft Constraints in AOP Extensions to a Class . . . . . . . . . . . 14-32

Soft Constraints in View Constraints Blocks . . . . . . . . . . . . . 14-34

Discarding Lower-Priority Soft Constraints . . . . . . . . . . . . . . 14-34

Using DPI Function Calls in Constraints . . . . . . . . . . . . . . . . . . . 14-36

xviii

Invoking Non-pure DPI Functions from Constraints. . . . . . . . 14-37

Using Foreach Loops Over Packed Dimensions in Constraints . 14-41

Memories with Packed Dimensions. . . . . . . . . . . . . . . . . . . . 14-42

Single Packed Dimension . . . . . . . . . . . . . . . . . . . . . . . . 14-42

Multiple Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . 14-42

MDAs with Packed Dimensions. . . . . . . . . . . . . . . . . . . . . . . 14-43

Single Packed Dimension . . . . . . . . . . . . . . . . . . . . . . . . 14-43

Multiple Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . 14-43

Just Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 14-43

The foreach Iterative Constraint for Packed Arrays. . . . . . . . 14-44

Randomized Objects in a Structure. . . . . . . . . . . . . . . . . . . . . . . 14-46

15.Extensions for SystemVerilog Coverage

Support for Reference Arguments in get_coverage() . . . . . . . . . 15-49

get_inst_coverage() method . . . . . . . . . . . . . . . . . . . . . . . . . 15-50

get_coverage() method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50

Functional Coverage Methodology Using the SystemVerilog C/C++ Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51

SystemVerilog Functional Coverage Flow . . . . . . . . . . . . . . . 15-52

Covergroup Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54

SystemVerilog (Covergroup for C/C++): covg.sv . . . . . . . 15-55

C Testbench: test.c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55

Approach #1: Passing Arguments by Reference . . . . . . . 15-56

Approach #2: Passing Arguments by Value . . . . . . . . . . . 15-56

Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-56

Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-57

C/C++ Functional Coverage API Specification . . . . . . . . . . . 15-57

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16.OpenVera-SystemVerilog Testbench Interoperability

Scope of Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

Importing OpenVera types into SystemVerilog . . . . . . . . . . . . . . 16-3

Data Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Mailboxes and Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . 16-7

Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

Enumerated Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

Integers and Bit-Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Structs and Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

Connecting to the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

Mapping Modports to Virtual Ports. . . . . . . . . . . . . . . . . . . . . 16-15

Virtual Modports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

Importing Clocking Block Members into a Modport . . . . . 16-16

Semantic Issues with Samples, Drives, and Expects . . . . . . 16-21

Notes to Remember . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22

Blocking Functions in OpenVera . . . . . . . . . . . . . . . . . . . 16-22

Constraints and Randomization . . . . . . . . . . . . . . . . . . . 16-22

Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25

17.Using SystemVerilog Assertions

Using SVAs in the HDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

xx

Using Standard Checker Library . . . . . . . . . . . . . . . . . . . . . . 17-2

Instantiating SVA Checkers in Verilog . . . . . . . . . . . . . . . 17-3

Instantiating SVA Checkers in VHDL . . . . . . . . . . . . . . . . 17-4

Inlining SVAs in the Verilog Design . . . . . . . . . . . . . . . . . . . . 17-6

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

Inlining SVA in the VHDL design . . . . . . . . . . . . . . . . . . . . . . 17-8

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9

Controlling SystemVerilog Assertions . . . . . . . . . . . . . . . . . . . . . 17-10

Elaboration and Runtime Options . . . . . . . . . . . . . . . . . . . . . 17-10

Assertion Monitoring System Tasks. . . . . . . . . . . . . . . . . . . . 17-13

Using Assertion Categories . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

Using System Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

Using Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19

Stopping and Restarting Assertions By Category . . . . . . 17-21

Viewing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

Using a Report File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

Enhanced Reporting for SystemVerilog Assertions in Functions 17-32

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34

Name Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34

Checker and Generate Blocks. . . . . . . . . . . . . . . . . . . . . . . . 17-34

Controlling Assertion Failure Messages . . . . . . . . . . . . . . . . . . . 17-35

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35

Options for Controlling Default Assertion Failure Messages . 17-36

Options to Control Termination of Simulation. . . . . . . . . . . . . 17-37

Option to Enable Compilation of OVA Case Pragmas . . . . . . 17-40

xxi

Enabling IEEE Std. 1800-2009 Compliant Features . . . . . . . . . . 17-41

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41

18.Using Property Specification Language

Including PSL in the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

PSL Assertions Inside VHDL Block Statements in Vunit . . . . . . . 18-5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

PSL Macro Support in VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

Using the %for Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

Using the %if Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

Using Expressions with %if and %for Constructs . . . . . . . . . 18-12

PSL Macro Support Limitations . . . . . . . . . . . . . . . . . . . . . . . 18-13

Using SVA Options, SVA System Tasks, and OV Classes . . . . . 18-14

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

19.Using SystemC

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

Verilog Design Containing Verilog/VHDL Modules and SystemC Leaf Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

xxii

Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9

Generating Verilog/VHDL Wrappers for SystemC Modules 19-10

Supported Port Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15

Compiling Interface Models with acc_user.h and vhpi_user.h 19-18

Controlling Time Scale and Resolution in a SystemC . . . . . . 19-19

Automatic adjustment of the time resolution . . . . . . . . . . 19-20

Setting time scale/resolution of Verilog or VHDL kernel. . 19-20

Setting time scale/resolution of SystemC kernel . . . . . . . 19-21

Adding a Main Routine for Verilog-On-Top Designs . . . . . . . 19-22

SNPS_REGISTER_SC_MAIN . . . . . . . . . . . . . . . . . . . . . 19-23

SystemC Designs Containing Verilog and VHDL Modules . . . . . 19-24

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25

Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

Generating a SystemC Wrapper for Verilog Modules . . . 19-27

Generating A SystemC Wrapper for VHDL Design . . . . . 19-28

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31

Elaboration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34

SNPS_REGISTER_SC_MODULE . . . . . . . . . . 19-37

VHDL Design Containing Verilog/VHDL Modules and SystemC Leaf Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38

Input Files Required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39

Generating a Verilog/VHDL Wrapper for SystemC Modules 19-40

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-43

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-45

SystemC Only Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-45

xxiii

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-47

Supported and Unsupported UCLI/DVE and CBug Features 19-48

Controlling TimeScale Resolution . . . . . . . . . . . . . . . . . . . . . . . . 19-49

Setting Timescale of SystemC Kernel . . . . . . . . . . . . . . . . . . 19-49

Automatic Adjustment of Time Resolution . . . . . . . . . . . . 19-50

Considerations for Export DPI Tasks. . . . . . . . . . . . . . . . . . . . . . 19-51

Use syscan -export_DPI [function-name]. . . . . . . . . . . . . 19-51

Use syscan -export_DPI [Verilog-file]. . . . . . . . . . . . . . . . 19-52

Use a Stubs File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-54

Using options -Mlib and -Mdir . . . . . . . . . . . . . . . . . . . . . . . . 19-54

Specifying Runtime Options to the SystemC Simulation. . . . . . . 19-55

Using a Port Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-56

Automatic Creation of Portmap File . . . . . . . . . . . . . . . . . . . . 19-58

Using a Data Type Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . 19-59

Combining SystemC with Verilog Configurations . . . . . . . . . . . . 19-61

Verilog-on-top, SystemC and/or VHDL down. . . . . . . . . . . . . 19-61

Compiling a Verilog/SystemC design . . . . . . . . . . . . . . . . 19-62

Compiling a Verilog/SystemC+VHDL design . . . . . . . . . . 19-63

SystemC-on-top, Verilog and/or VHDL down. . . . . . . . . . . . . 19-64

Compiling a SystemC/Verilog design . . . . . . . . . . . . . . . . 19-66

Compiling a SystemC/Verilog+VHDL design . . . . . . . . . 19-67

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-67

Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-68

Parameters in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-68

xxiv

Parameters in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-69

Parameters in SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-69

Verilog-on-Top, SystemC-down . . . . . . . . . . . . . . . . . . . . . . . 19-70

VHDL-on-Top, SystemC-down. . . . . . . . . . . . . . . . . . . . . . . . 19-71

SystemC-on-Top, Verilog or VHDL down. . . . . . . . . . . . . . . . 19-72

Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-73

Parameter specification as vcs elaboration arguments . . . . 19-73

Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-74

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-74

Debugging Mixed Simulations Using DVE or UCLI. . . . . . . . . . . 19-75

Improved CBug Debugging Capabilities . . . . . . . . . . . . . . . . . . . 19-76

Viewing sc_signal of User-defined struct in Waveform Window 19-76

Driver/Load Support for SystemC Designs in Post Processing 19-77

Transaction Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-78

Interface Definition File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-79

Generation of the TLI Adapters . . . . . . . . . . . . . . . . . . . . . . . 19-83

Transaction Debug Output. . . . . . . . . . . . . . . . . . . . . . . . . . . 19-84

Instantiation and Binding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-85

Supported Data Types of Formal Arguments. . . . . . . . . . . . . 19-88

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-89

Delta-cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-89

Using a Customized SystemC Installation. . . . . . . . . . . . . . . . . . 19-90

Compatibility with OSCI SystemC . . . . . . . . . . . . . . . . . . . . . 19-93

Compiling Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-93

Using Posix threads or quickthreads. . . . . . . . . . . . . . . . . . . . . . 19-93

xxv

VCS Extensions to SystemC Library. . . . . . . . . . . . . . . . . . . . . . 19-94

Installing VG GNU Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-100

Static and Dynamic Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-100

Static Linking in VCS MX . . . . . . . . . . . . . . . . . . . . . . . . . 19-100

Dynamic Linking in VCS MX (For C/C++ Files) . . . . . . . . 19-101

Dynamic Linking in VCS MX (For SystemC Files) . . . . . . 19-102

LD_LIBRARY_PATH Environment Variable . . . . . . . . . . 19-103

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-103

Verilog wrapper needed for pure VHDL-top-SystemC down19-104

Incremental Compile of SystemC Source Files . . . . . . . . . . . . . . 19-105

Full Build from Scratch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-106

Full Incremental Build . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-107

Partial Build with Object Files . . . . . . . . . . . . . . . . . . . . . . . . 19-108

Partial Build with Shared Libraries . . . . . . . . . . . . . . . . . . . . . 19-109

Updating the Shared Library . . . . . . . . . . . . . . . . . . . . . . 19-110

Using Different Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . 19-110

Partial Build Invoked with vcs. . . . . . . . . . . . . . . . . . . . . . 19-111

Partial Build if Just One Shared Library is Updated . . . . . 19-111

Adding or Deleting SC Source Files in Shared Library . . 19-112

Changing From a Shared Library Back to Object Files . . 19-112

Suppressing Automatic Dependency Checking. . . . . . . . . . . 19-112

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-113

TLI Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-113

Accessing SystemC Members from SystemVerilog. . . . . . . . 19-114

TLI Adaptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-114

Instantiating the TLI adaptor in SV . . . . . . . . . . . . . . . . . . 19-114

xxvi

Direct Variable Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-115

Calling SystemC Member Function . . . . . . . . . . . . . . . . . 19-115

Arguments of Type char* used in Blocking Member Functions19-117

Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-117

SC_FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-120

Non-SystemC Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-121

Sub-classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-122

Name Clashes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-123

Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-125

Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-125

Syntax of TLI File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-126

Debug Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-129

Accessing Struct or Class Members of a SystemC Module from SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-130

Enhancements to TLI for Providing Access to SystemC/C++ Class Members from SystemVerilog. . . . . . . . . . . . . . . . . . . 19-131

Accessing Struct or Class Members of a SystemC Module Object from SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . 19-131

Accessing Generic C++ Struct or Class . . . . . . . . . . . . . . 19-135

Extensions of TLI Input File . . . . . . . . . . . . . . . . . . . . . . . 19-139

Invoking Pack or Unpack Adaptor Code Generation . . . . 19-140

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-141

Accessing Verilog Variables from SystemC. . . . . . . . . . . . . . 19-141

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-141

Access Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-142

Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-143

Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-144

Type Conversion Mechanism. . . . . . . . . . . . . . . . . . . . . . 19-145

xxvii

Accessing SystemVerilog Functions and Tasks from SystemC19-147

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-148

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-148

Function Declaration Hierarchy . . . . . . . . . . . . . . . . . . . . 19-149

Passing Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-151

Supported Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-152

Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-152

Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-154

Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-155

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-156

Accessing SystemC Members from SystemVerilog Using the tli_get_ or tli_set_ Functions. . . . . . . . . . . . 19-157

Using the tli_get_ and tli_set_ Functions . . 19-157

Prototypes of tli_get_ and tli_set_ Functions 19-158

Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-159

Member Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-162

Type Conversion Mechanism. . . . . . . . . . . . . . . . . . . . . . 19-164

Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-166

Generating C++ Struct Definition from SystemVerilog Class Definition19-168

Use Model for Generating C++ Struct from SystemVerilog Class19-169

Data Type Conversion from SystemVerilog to C++ . . . . . 19-170

Example for Generating C++ Struct from SystemVerilog Class19-171

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-172

Supporting Designs with Donut Topologies. . . . . . . . . . . . . . . . . 19-173

xx-

Exchanging Data Between SystemVerilog and SystemC Using Byte Pack/Unpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-175

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-176

Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-177

Unsupported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 19-177

Mapping of SystemC/C++ and SystemVerilog/VMM Data Types19-178

Usage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-183

Using the Pack Operator . . . . . . . . . . . . . . . . . . . . . . . . . 19-183

Using Unpack Operator . . . . . . . . . . . . . . . . . . . . . . . . . . 19-184

Using Pack and Unpack Functions . . . . . . . . . . . . . . . . . . . . 19-184

Using Code Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-187

Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-188

Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-188

Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-190

Supported Data types for Automatic Code Generation . . 19-191

Correcting the Generated Files . . . . . . . . . . . . . . . . . . . . 19-192

Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-193

Usage Example for Code Generator . . . . . . . . . . . . . . . . 19-194

Using Direct Program Interface Based Communication . . . . . . . 19-204

Limitations of Using DPI-based Communication Between Verilog and SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-205

Improving VCS-SystemC Compilation Speed Using Precompiled C++ Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-205

Introduction to Precompiled Header Files . . . . . . . . . . . . . . . 19-206

Using Precompiled Header Files . . . . . . . . . . . . . . . . . . . . . . 19-206

Example to Use the Precompiled Header Files . . . . . . . . . . . 19-208

Invoking the Creation of Precompiled Header Files. . . . . . . . 19-209

xxix

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-210

Limitations of syscan -prec . . . . . . . . . 19-210

Limitations of using -prec with path . . . . . . . . . . . . . . . . 19-212

Limitations of Sharing Precompiled Header Files . . . . . . 19-212

Increasing Stack and Stack Guard Size . . . . . . . . . . . . . . . . . . . 19-213

Increasing the Stack Size . . . . . . . . . . . . . . . . . . . . . . . . . 19-214

Increasing the Stack Guard Size . . . . . . . . . . . . . . . . . . . 19-214

Guidelines to Diagnose Stack Overrun . . . . . . . . . . . . . . 19-215

Debugging SystemC Runtime Errors . . . . . . . . . . . . . . . . . . . . . 19-216

Debugging SystemC Kernel Errors . . . . . . . . . . . . . . . . . . . . 19-216

Troubleshooting Your Elaboration Errors . . . . . . . . . . . . . 19-217

Troubleshooting Your Runtime Errors . . . . . . . . . . . . . . . 19-220

Function cbug_stop_here() . . . . . . . . . . . . . . . . . . . . . . . 19-222

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-224

Diagnosing Quickthread Issues . . . . . . . . . . . . . . . . . . . . . . . 19-224

Using HDL and SystemC Sync Loops. . . . . . . . . . . . . . . . . . . . . 19-225

The Coarse-Grained Sync Loop (blocksync) . . . . . . . . . . . . . 19-225

The Fine-Grained Sync Loop (deltasync) . . . . . . . . . . . . . . . 19-226

Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-226

Alignment of Delta Cycles . . . . . . . . . . . . . . . . . . . . . . . . 19-226

Example Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-227

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-227

Restrictions That No Longer Apply. . . . . . . . . . . . . . . . . . 19-228

Newsync is Now Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-228

Controlling Simulation Run From sc_main . . . . . . . . . . . . . . . . . 19-229

Effect on end_of_simulation Callbacks . . . . . . . . . . . . . . . . . 19-231

xxx

UCLI Save Restore Support for SystemC-on-top and Pure-SystemC19-232

SystemC with UCLI Save and Restore Use Model . . . . . . . . 19-233

SystemC with UCLI Save and Restore Coding Guidelines . . 19-233

Saving and Restoring Files During Save and Restore. . . . . . 19-235

Restoring the Saved Files from the Previous Saved Session 19-236

Limitations of UCLI Save Restore Support . . . . . . . . . . . . . . 19-236

Enabling Unified Hierarchy for VCS and SystemC . . . . . . . . . . . 19-237

Using Unified Hierarchy Elaboration . . . . . . . . . . . . . . . . . . . 19-237

Value Added by Option sysc=unihier . . . . . . . . . . . . . . . 19-240

Using the sysc=show_sc_main Switch . . . . . . . . . . . . . . . . 19-241

SystemC Unified Hierarchy Flow Limitations . . . . . . . . . . . . . 19-242

Aligning VMM and SystemC Messages . . . . . . . . . . . . . . . . . . . 19-242

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-243

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-243

Changing Message Alignment Settings. . . . . . . . . . . . . . . . . 19-244

Mapping SystemC to VMM Severities . . . . . . . . . . . . . . . . . . 19-246

Filtering Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-246

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-249

UVM Message Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-250

Enabling UVM Message Alignment . . . . . . . . . . . . . . . . . . . . 19-250

Accessing UVM Report Object of SystemC Instance . . . . . . 19-254

Introducing TLI Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-257

TLI Adapter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-257

SystemC Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-258

Global Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-258

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User Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-260

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-264

VMM Channel Interface (vmm_tlm_generic_payload) . . . 19-264

VMM TLM Interface (vmm_tlm_generic_payload) . . . . . . 19-267

VMM Channel/TLM Interface (Other data type) . . . . . . . . 19-270

SV Interface Other Than vmm_channel/vmm_tlm . . . . . . 19-270

VMM Channel Interface Details. . . . . . . . . . . . . . . . . . . . 19-271

VMM TLM Interface Details . . . . . . . . . . . . . . . . . . . . . . . 19-274

E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xamples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-278

Example-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-279

Example-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-283

Example-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-286

Example-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-288

Example-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-290

Example-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-294

Example-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-297

Example-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-299

Example-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-301

Example-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-304

Using VCS UVM TLI Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . 19-308

Using the UVM TLI Adapters . . . . . . . . . . . . . . . . . . . . . . . . . 19-308

UVM TLM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-308

UVM Analysis Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 19-310

Handling Multiple Subscribers . . . . . . . . . . . . . . . . . . . . . 19-312

UVM TLM Communication Examples . . . . . . . . . . . . . . . . . . 19-312

uvm_tlm_blocking Example . . . . . . . . . . . . . . . . . . . . . . . 19-312

uvm_tlm_nonblocking Example . . . . . . . . . . . . . . . . . . . . 19-314

uvm_tlm_analysis Example . . . . . . . . . . . . . . . . . . . . . . . 19-316

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Modeling SystemC Designs with SCV . . . . . . . . . . . . . . . . . . . . 19-318

SCV Library in VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-319

Use model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-319

msglog Extensions for Transaction Recording with SCV in VCS19-320

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-320

Viewing SystemC sc_report_handler Messages from Log File19-321

20.C Language Interface

Using PLI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

Writing a PLI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

Functions in a PLI Application . . . . . . . . . . . . . . . . . . . . . . . . 20-4

Header Files for PLI Applications. . . . . . . . . . . . . . . . . . . . . . 20-5

PLI Table File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

Using the PLI Table File . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19

Enabling ACC Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

Globally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

Using the Configuration File . . . . . . . . . . . . . . . . . . . . . . . 20-21

Selected ACC Capabilities . . . . . . . . . . . . . . . . . . . . . . . . 20-24

PLI Access to Ports of Celldefine and Library Modules . . . . . 20-28

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29

Visualization in DVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31

Using VPI Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32

Support for VPI Callbacks for Reasons cbForce and cbRelease20-32

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Support for the vpi_register_systf Routine. . . . . . . . . . . . . . . 20-33

Integrating a VPI Application With VCS MX. . . . . . . . . . . . . . 20-34

PLI Table File for VPI Routines . . . . . . . . . . . . . . . . . . . . . . . 20-36

Virtual Interface Debug Support. . . . . . . . . . . . . . . . . . . . . . . 20-36

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-40

Unimplemented VPI Routines . . . . . . . . . . . . . . . . . . . . . . . . 20-40

Using VHPI Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42

Diagnostics for VPI/VHPI PLI Applications . . . . . . . . . . . . . . . . . 20-42

Using DirectC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42

Using Direct C/C++ Function Calls . . . . . . . . . . . . . . . . . . . . 20-44

How C/C++ Functions Work in a Verilog Environment. . . 20-46

Declaring the C/C++ Function . . . . . . . . . . . . . . . . . . . . . 20-47

Calling the C/C++ Function . . . . . . . . . . . . . . . . . . . . . . . 20-54

Storing Vector Values in Machine Memory. . . . . . . . . . . . 20-55

Converting Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-58

Avoiding a Naming Problem. . . . . . . . . . . . . . . . . . . . . . . 20-61

Using Pass by Reference. . . . . . . . . . . . . . . . . . . . . . . . . 20-61

Using Direct Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

Using the vc_hdrs.h File. . . . . . . . . . . . . . . . . . . . . . . . . . 20-69

Access Routines for Multi-Dimensional Arrays . . . . . . . . 20-70

Using Abstract Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-72

Using vc_handle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-72

Using Access Routines . . . . . . . . . . . . . . . . . . . . . . . . . . 20-74

Summary of Access Routines . . . . . . . . . . . . . . . . . . . . . 20-118

Enabling C/C++ Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . 20-123

Mixing Direct And Abstract Access . . . . . . . . . . . . . . . . . 20-125

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Specifying the DirectC.h File . . . . . . . . . . . . . . . . . . . . . . 20-125

Extended BNF for External Function Declarations . . . . . . . . 20-126

21.SAIF Support

Using SAIF Files with VCS MX . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

SAIF System Tasks for Verilog or Verilog-Top Designs. . . . . . . . 21-2

The Flows to Generate a Backward SAIF File . . . . . . . . . . . . . . 21-5

Generating an SDPD Backward SAIF File. . . . . . . . . . . . . . . 21-6

Generating a Non-SPDP Backward SAIF File . . . . . . . . . . . . 21-7

SAIF Calls That Can Be Used on VHDL or VHDL-Top Designs . 21-7

SAIF Support for Two-Dimensional Memories in v2k Designs . . 21-9

UCLI SAIF Dumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

Criteria for Choosing Signals for SAIF Dumping . . . . . . . . . . . . . 21-10

22.Encrypting Source Files

128-bit Advanced Encryption Standard . . . . . . . . . . . . . . . . . . . . 22-1

Using Compiler Directives or Pragmas . . . . . . . . . . . . . . . . . 22-2

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

Using Automatic Protection Options . . . . . . . . . . . . . . . . . . . 22-5

gen_vcs_ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6

Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

Analysis Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

Exporting The IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

IP Vendor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

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IP Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10

IP User . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10

Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10

23. Integrating VCS MX with Vera

Setting Up Vera and VCS MX . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

Using Vera with VCS MX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

24.Using HSIM-VCS MX DKI Mixed-Signal Simulation

Environment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

25. Integrating VCS MX with NanoSim

Environment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

26. Integrating VCS MX with XA

Introduction to VCS MX-XA . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

Analyzing a Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

Elaborating a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

Setting up the Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4

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Analyzing Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4

Elaborating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

27. Integrating VCS MX with Specman

Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2

Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

Setting Up The Environment . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

Specman e code accessing VHDL only. . . . . . . . . . . . . . . . . 27-5

Specman e Code Accessing Verilog Only . . . . . . . . . . . . . . . 27-7

e code accessing both VHDL and Verilog . . . . . . . . . . . . . . . 27-9

Guidelines for Specifying HDL Path or Tick Access with VCS MX-Specman Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12

Using specrun and specview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

Adding Specman Objects To DVE. . . . . . . . . . . . . . . . . . . . . . . . 27-15

Version Checker for Specman. . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17

28. Integrating VCS MX with Denali

Setting Up Denali Environment for VCS MX . . . . . . . . . . . . . . . . 28-1

Integrating Denali with VCS MX . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

Usage Model for VHDL Memory Models . . . . . . . . . . . . . . . . 28-3

Usage Model for Verilog Memory Models . . . . . . . . . . . . . . . 28-4

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Execute Denali Commands at UCLI Prompt . . . . . . . . . . . . . 28-5

29. Integrating VCS MX with Debussy

Using the Current Version of VCS MX with Novas 2010.07 Version 29-1

Setting Up Debussy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

Usage Model to Dump fsdb File. . . . . . . . . . . . . . . . . . . . . . . 29-2

Using VHDL Procedures or Verilog System Tasks. . . . . . 29-4

Using UCLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

30. Integrating VCS with MVSIM Native Mode

Introduction to MVSIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1

MVSIM Native Mode in VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3

31.Migrating to VCS MX

Step 1: Setting Up The Environment . . . . . . . . . . . . . . . . . . . . . . 31-3

Step 2: Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5

Step 3: Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6

Step 4: Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7

Simulation Executable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

User Interface Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9

Coding Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10

LRM Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11

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Appendix A. VCS MX Environment Variables

Setup Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Analysis Setup Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Compilation/Elaboration Setup Variables. . . . . . . . . . . . . . . . A-5

Simulation Setup Variables . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

C Compilation and Linking Setup Variables. . . . . . . . . . . . . . A-17

New Timescale Implementation. . . . . . . . . . . . . . . . . . . . . . . A-19

Understanding `timescale. . . . . . . . . . . . . . . . . . . . . . . . . A-20

Verilog only and Verilog Top Mixed Design . . . . . . . . . . . A-24

VHDL only and VHDL Top Mixed Designs . . . . . . . . . . . . A-25

Setting up Simulator Resolution From Command Line . . A-26

Other Useful Timescale Related Switches . . . . . . . . . . . . A-28

Non compatible switches . . . . . . . . . . . . . . . . . . . . . . . . . A-30

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30

Optional Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . A-30

Appendix B. Analysis Utilities

The vhdlan Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Using Smart Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10

The vlogan Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11

Appendix C. Elaboration Options

Option for Accessing Verilog Libraries . . . . . . . . . . . . . . . . . . C-4

Options for Incremental Compilation . . . . . . . . C-4

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Options for Help and Documentation. . . . . . . . . . . . . . . . . . . C-6

Options for SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6

Options for SystemVerilog Assertions . . . . . . . . . . . . . . . . . . C-7

Options to Enable Compilation of OVA Case Pragmas . . . . . C-13

Options for Native Testbench. . . . . . . . . . . . . . . . . . . . . . . . . C-13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18

Options for Initializing Memories and Registers with Random ValuesC-18

Options for Using Radiant Technology. . . . . . . . . . . . . . . . . . C-19

Options for 64-bit Compilation . . . . . . . . . . . . . . . . . . . . . . . . C-19

Options for Starting Simulation Right After Compilation . . . . C-20

Options for Specifying Delays and SDF Files . . . . . . . . . . . . C-20

Options for Compiling an SDF File . . . . . . . . . . . . . . . . . . . . C-24

Options for Specify Blocks and Timing Checks . . . . . . . . . . . C-24

Options for Pulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . C-25

Options for Negative Timing Checks . . . . . . . . . . . . . . . . . . . C-27

Option to Specify Elaboration Options in a File . . . . . . . . . . . C-28

Options for Compiling Runtime Options into the Executable . C-29

Options for PLI Applications . . . . . . . . . . . . . . . . . . . . . . . . . C-29

Options to Enable the VCS MX DirectC Interface . . . . . . . . . C-33

Options for Flushing Certain Output Text File Buffers . . . . . . C-33

Options for Controlling Messages . . . . . . . . . . . . . . . . . . . . . C-34

Options for Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . C-36

Options for Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-38

Options for Controlling the Linker . . . . . . . . . . . . . . . . . . . . . C-38

Options for Controlling the C Compiler . . . . . . . . . . . . . . . . . C-41

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Options for Source Protection . . . . . . . . . . . . . . . . . . . . . . . . C-43

Options for Mixed Analog/Digital Simulation . . . . . . . . . . . . . C-45

Unified Option to Change Generic and Parameter Values . . C-45

Checking for X and Z Values in Conditional Expressions . . . C-46

Options for Detecting Race Conditions . . . . . . . . . . . . . . . . . C-46

Options to Specify the Time Scale . . . . . . . . . . . . . . . . . . . . . C-48

Options for Overriding Generics and Parameters . . . . . . . . . C-49

General Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-52

Enable the VCS MX/SystemC Cosimulation Interface . . . C-52

TetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-53

Allow Inout Port Connection Width Mismatches. . . . . . . . C-53

Allow Zero or Negative Multiconcat Multiplier . . . . . . . . . C-53

Specifying a VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . C-54

Enabling Dumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-54

Memories and Multi-Dimensional Arrays (MDAs) . . . . . . C-54

Specifying a Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-55

Changing Source File Identifiers to Upper Case . . . . . . . C-56

Specifying the Name of the Executable File. . . . . . . . . . . C-56

Returning The Platform Directory Name . . . . . . . . . . . . . C-56

Maximum Donut Layers for a Mixed HDL Design . . . . . . C-56

Enabling feature beyond VHDL LRM . . . . . . . . . . . . . . . . C-57

Enable Loop Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-57

Changing the Time Slot of Sequential UDP Output EvaluationC-57

Gate-Level Performance . . . . . . . . . . . . . . . . . . . . . . . . . C-58

Option to Omit Compilation of Code Between Pragmas . C-58

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Appendix D. Simulation Options

Options for Simulating Native Testbenches . . . . . . . . . . . . . . D-2

Options for SystemVerilog Assertions . . . . . . . . . . . . . . . . . . D-10

Options to Control Termination of Simulation. . . . . . . . . . . . . D-19

Options for Enabling and Disabling Specify Blocks . . . . . . . . D-19

Options for Specifying When Simulation Stops . . . . . . . . . . . D-20

Options for Recording Output . . . . . . . . . . . . . . . . . . . . . . . . D-21

Options for Controlling Messages . . . . . . . . . . . . . . . . . . . . . D-21

Options for VPD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-22

Options for VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-25

Options for Specifying Delays . . . . . . . . . . . . . . . . . . . . . . . . D-26

Options for Flushing Certain Output Text File Buffers . . . . . . D-28

Options for Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-29

Option to Specify User-Defined Runtime Options in a File . . D-29

Option for Initializing Integer Data Type Variables at Runtime D-30

General Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-32

Viewing the Compile-Time Options . . . . . . . . . . . . . . . . . D-32

Recording Where ACC Capabilities are Used . . . . . . . . . D-32

Suppressing the $stop System Task . . . . . . . . . . . . . . . . D-33

Enabling User-defined Plusarg Options . . . . . . . . . . . . . . D-33

Enabling feature beyond VHDL LRM . . . . . . . . . . . . . . . . D-33

Specifying acc_handle_simulated_net PLI Routine . . . . . D-33

Appendix E. Verilog Compiler Directives and System Tasks

Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

Compiler Directives for Cell Definition . . . . . . . . . . . . . . . . . . E-2

Compiler Directives for Setting Defaults . . . . . . . . . . . . . . . . E-2

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Compiler Directives for Macros . . . . . . . . . . . . . . . . . . . . . . . E-3

Compiler Directives for Delays. . . . . . . . . . . . . . . . . . . . . . . . E-5

Compiler Directives for Backannotating SDF Delay Values. . E-6

Compiler Directives for Source Protection . . . . . . . . . . . . . . . E-6

Debugging Partially Encrypted Source Code . . . . . . . . . . E-7

Compiler Directives for Controlling Port Coercion . . . . . . . . . E-8

General Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . E-8

Compiler Directive for Including a Source File . . . . . . . . . E-8

Compiler Directive for Setting the Time Scale . . . . . . . . . E-8

Compiler Directive for Specifying a Library . . . . . . . . . . . E-8

Compiler Directive for File Names and Line Numbers . . . E-9

Unimplemented Compiler Directives . . . . . . . . . . . . . . . . . . . E-10

System Tasks and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11

System Tasks for SystemVerilog Assertions Severity . . . . . . E-11

System Tasks for SystemVerilog Assertions Control . . . . . . . E-11

System Tasks for SystemVerilog Assertions . . . . . . . . . . . . . E-12

System Tasks for VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . E-13

System Tasks for LSI Certification VCD and EVCD Files . . . E-15

System Tasks for VPD Files. . . . . . . . . . . . . . . . . . . . . . . . . . E-18

System Tasks for SystemVerilog Assertions . . . . . . . . . . . . . E-26

System Tasks for Executing Operating System Commands . E-27

System Tasks for Log Files . . . . . . . . . . . . . . . . . . . . . . . . . . E-28

System Tasks for Data Type Conversions . . . . . . . . . . . . . . . E-28

System Tasks for Displaying Information . . . . . . . . . . . . . . . . E-29

System Tasks for File I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . E-30

System Tasks for Loading Memories . . . . . . . . . . . . . . . . . . . E-32

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System Tasks for Time Scale. . . . . . . . . . . . . . . . . . . . . . . . . E-33

System Tasks for Simulation Control . . . . . . . . . . . . . . . . . . . E-34

System Tasks for Timing Checks. . . . . . . . . . . . . . . . . . . . . . E-34

Timing Checks for Clock and Control Signals . . . . . . .