Upgrading to SystemVerilog for FPGA Designs - Presented at FPGA Camp Bangalore Presented at FPGA Camp, Bangalore Srinivasan Venkataramanan Chief Technology Officer CVC Pvt. Ltd. www.cvcblr.com
May 06, 2015
Upgrading to SystemVerilog for FPGA Designs
- Presented at FPGA Camp BangalorePresented at FPGA Camp, Bangalore
Srinivasan VenkataramananChief Technology Officer
CVC Pvt. Ltd.www.cvcblr.com
Agenda
Introduction to SystemVerilog (SV) SV - RTL Design constructs SV - RTL Design constructs SV Interface SV Assertions Success Stories SV-FPGA Ecosystem
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About the presenterSrinivasan Venkataramanan, CTO, www.cvcblr.com http://www.linkedin.com/in/svenka3 Over 13 years of experience in VLSI Design & VerificationOver 13 years of experience in VLSI Design & Verification Designed, verified and lead several multi-million ASICs in
image processing, networking and communication domain Worked at Philips, Intel, Synopsys in various p , , y p y
capacities. Co-authored leading books in the Verification domain. Presented papers, tutorials in various conferences,
bli ti dpublications and avenues. Conducted workshops and trainings on PSL, SVA, SV,
VMM, E, ABV, CDV and OOP for VerificationHolds M Tech in VLSI Design f om p estigio s IIT Delhi Holds M.Tech in VLSI Design from prestigious IIT, Delhi.
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What is SystemVerilog? Superset of Verilog-2001 IEEE 1800-2005 standard M i f ti @ S t V il More information @ www.SystemVerilog.org Several books available:
SystemVerilog Assertions Handbook – Ajeetha, Ben Cohen, y g j , ,Srinivasan, www.systemverilog.us
A Pragmatic approach to VMM adoption – Ajeetha, Ben, Srinivasan
SystemVerilog for Designers, Stuart Sutherland
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SystemVerilog - Evolution
Properties – capture temporal B h i A ti
OOP based TestbenchConstraint driven randomizationConstrained
Classes, inheritance, polymorphism
Sequential Regular Expressions
TemporalProperty Definitions
Behavior: Assertion,Assumption, Coverage
SVA
Functional CoverageInheritancePolymorphismVirtual InterfaceQueues,A i ti
Random Data Generation
Covergroup,
SemaphoresMailboxes
Data structuresMDA
Verilog 2001
Virtual InterfaceAssociative& Dynamicarrays
g p,sampling
Enhanced programming(do hile break contin e
Strings
Data structuresenums
MDAs
Enhanced DesignConstructs, modeling
SV D i
DPI – Quickly connect C/C++Very efficient and ease of use Coverage &
Assertion API
(do while, break, continue, ++, --, +=. Etc.)
Better logical blocks –always comb ff latch
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SV-DesignDPI interface
always_comb, _ff, _latch
SystemVerilog - User view
Has 5 major parts:SVD – SystemVerilog for DesignSVD SystemVerilog for DesignSVA – SystemVerilog AssertionsSVTB – SystemVerilog TestbenchSVTB SystemVerilog TestbenchSV-DPI – Direct Programming Interfacefor better C/C++ interfacefor better C/C++ interface
SV-API – Application Procedural Interface for Coverage Assertion etc
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for Coverage, Assertion etc.
Reference Books
Source A Pragmatic Approach to VMM Adoption 2006 for Tutorial ISBN 0-9705394-9-5, http://www.systemverilog.usnd Code
(7)
and Code
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SV Design-Data Types
Enhanced data types: 2-state (bit) logic 2 state (bit), logic
Potential memory & run time improvement (2-state)improvement (2-state)
High level models can avail 2-state Clearer descriptions: a Verilog reg is
NOT necessarily a “register”
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SV Design – Data types
User Defined types Enums – local typedef Enums local, typedef Strict type checking, typecast
Better modeling style easy to read Better modeling style, easy to read, maintainSt t di i l ( t i State encoding - via language (not via tool scripts)
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Ease of debug, waveform
SV Design – logic modeling Verilog RTL – only always block Combinatorial & Sequential Inference by sensitivity list One of the top 10 error prone usages – more for
newbienewbie SV: Enhanced Modeling
always_comby _ always_ff always_latch
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What logic is being modeled?
Modeling combinatorial logic?
Use always comby _
Modeling Sequential g qlogic?
Use always_ff
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What logic is being modeled?
Modeling Latch? Modeling Latch? Use always_latch Reduces Synthesis- Reduces Synthesis-
Simulation discrepancies Language captures design Language captures design
intent (not pragmas, tool settings)
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g )
Abstract modeling - struct
l k C-like struct Well proven
data structure abstraction technique
Cut down CVC Copyright 2008www.cvcblr.com 13
Cut do# lines
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Interfaces – bread-n-butter of modernInterfaces bread n butter of modern SoCs
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Interfaces – SPI, OCP
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Old fashioned hook-up–Verilog description
Too verbose Too verbose Highly error
prone Maintenance
head-ache Not easy to
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Not easy to reuse
Typical sub-systemModeled using Verilog
AHB
Master1
AHB
Master2
AHB Slave2
AHB Slave1 Slave2Slave1
SoC is built using IPs – lot of ReUseI di id l bl k ifi d i t d l Individual blocks pre-verified in standalone
Most Bugs Occur Between BlocksA d b f “Wi i ” E
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A good number of “Wiring” Errors
Hookup various blocks – the old way
Mem din
addr module top();mem_controller mc (clk, rst_n, dout,
addr, din, wr_rd);memory mem0(clk,rst n, addr, din,
top
m_Control
Memory
din
d t
wr_rd
module mem controller (
memory mem0(clk,rst_n, addr, din,wr_rd, dout);
endmodule
ler dout_ (
input clk, rst_n,[7:0] dout,output [3:0] addr, [7:0] din, wr_rd);
task write();module memory(output [7:0] dout ();addr <= ‘haa;din <= $random;wr_rd = 1’b1;@(posedge clk);
module memory(output [7:0] dout,input clk, rst_n, [3:0] addr, [7:0] din, wr_rd);always @(posedge clk)if (wr rd)
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@(p g );wr_rd = 1’b0;
endtask : writeendmodule
if (wr_rd)mem[addr] <= din;
endmodule : memory
Interface
interface simple_bus; // Define the interfacelogic req, gnt;l i [ ] dd d
module cpuMod(simple_bus b, input bit clk);
logic [7:0] addr, data;logic [1:0] mode;logic start, rdy;endinterface: simple_bus
...endmodule
module top;p _
module memMod(simple_bus a, // Use the simple_bus interface
input bit clk);
logic clk = 0;simple_bus sb_intf; // Instantiate the
interfacememMod mem(sb_intf, clk); cpuMod cpu( b(sb intf) clk(clk));input bit clk);
logic avail;// a.req is the req signal in the ’simple_bus’
interfacealways @(posedge clk) a gnt <= a req &
cpuMod cpu(.b(sb_intf), .clk(clk));endmodule
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always @(posedge clk) a.gnt <= a.req & avail;
endmodule
Assertion-Based Verification It’s a verification technique Instruments requirements with assertions
Cla ifies eq i ements ith e ec table lang age Clarifies requirements with executable language Enables tools to preview assertion waveforms
Instruments design with assertions Added visibility White-box testing into its internal state Provision for functional coverage information
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Applying ABV - Bus based SoC
Simulate
What happened during sim?at appe ed du g s Any protocol violation? How many RW? Was xfer interrupted?
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Was xfer interrupted?
Use assertions sparingly
Non-intrusive Works with any existing flow
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The more you add, the more you gain
Ross Video – SV verificationRoss Video SV verification for FPGAs The Ross Video team created a robust verification
environment utilizing the VMM's built-in:lf h ki self-checking
scenario generation transaction-level channels transactors and messaging services.
Extensive use of SystemVerilog assertions (SVA) Extensive use of SystemVerilog assertions (SVA)
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Advantages of interface gcustomer success stories
Better design style Disambiguate the communicationg Forces to have a clear interface
specification upfront – takes little more b h ltime, but saves much more later on
Reduces integration time Add Assertions to interface, every block
using it shall have to comply with the protocol
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protocol
Impact of InterfaceImpact of Interfaceinterface utopia_i;
module netproc (SX_ux_soc, SX_ux_en, SX_ux_data, SX_ux_clav, SX_ux_clk, SX_cpu_BusMode, SX_cpu_Addr, SX_cpu_Sel, SX D t SX Rd DS SX W RWwire soc; // start of cell
wire en; // enablewire [7:0] data; // datawire clav; // cell availablewire clk; // ATM layer clock
endinterface
Syste V
SX_cpu_Data, SX_cpu_Rd_DS, SX_cpu_Wr_RW, SX_cpu_Rdy_Dtack, rst, clk);inout SX_ux_soc;inout SX_ux_en;inout [7:0] SX_ux_data;inout SX_ux_clav;inout SX ux clk;
interface cpu_i(input bit rst);wire BusMode;logic [11:0] Addr;logic Sel;wire [ 7:0] Data;logic Rd DS;
emVeri
Verilog9
inout SX_ux_clk;inout SX_cpu_BusMode;inout [11:0] SX_cpu_Addr;inout SX_cpu_Sel;inout [7:0] SX_cpu_Data;inout SX_cpu_Rd_DS;inout SX_cpu_Wr_RW;g _ ;
logic Wr_RW;wire Rdy_Dtack;
endinterface
module netproc(utopia_i ux, cpu_i cpu,input bit clk);
d d llog
95inout SX_cpu_Rdy_Dtack;input rst;input clk;wire SX_ux_soc;wire SX_ux_en;wire [7:0] SX_ux_data;wire SX ux clav;endmodule
- 3X more compact
wire SX_ux_clav;wire SX_ux_clk;wire SX_cpu_BusMode;wire [11:0] SX_cpu_Addr;wire SX_cpu_Sel;wire [7:0] SX_cpu_Data;wire SX_cpu_Rd_DS;
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3 o e co pact- Fewer wiring mistakes
_ p _ _wire SX_cpu_Wr_RW;wire SX_cpu_Rdy_Dtack;wire rst;wire clk;
endmodule
Ecosystem around SV-FPGA
All major EDA vendors support SV for Design (simulators)g ( )
Synthesis: Synplify, leonardo FPGA vendors – need more supportFPGA vendors need more support
Latest update pending Books, tutorials – plenty: Books, tutorials plenty:
www.aldec.com/Downloads Trainings: www cvcblr com/trainings Trainings: www.cvcblr.com/trainings
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Aldec’s Active-HDL
Design-flow manager
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SV & FPGA tool support Active-HDL
SV-Design, Assertions (SVA + PSL) Interface Debug Interface, Debug
Modelsim-DE SV-Design, SVA, PSL
Synplify Synplify SV-Design, synthesizable constructs
Leonardo Details awaited, call Mentor
Xilinx, Altera Unknown, call your vendor, y
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SV & FPGA advanced technologies
With adoption of SV, modern design paradigms emergep g g
ASIC prototyping – EVE Design systems Jasper’s ActiveDesign is one suchJasper s ActiveDesign is one such
technology Can create waveforms for AHB, AXI etc.Can create waveforms for AHB, AXI etc.
right from RTL No TB required, plain RTL + ActiveDesignq , p g
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Jasper’s ActiveDesign
Capture “information” during RTL design phase:p
Designer makes an assumption about the latency of output, FIFO size etc.y p , “show me a proof/witness/waveform” for such
an occurrence Can we optimize the latency to say 5 What-if I change the FIFO size to 32 here etc.
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CVC Trainings –www.cvcblr.com/trainings Verification Centric Course
Comprehensive Functional Verification (CFV) Language Course
IEEE 1800 SystemVerilog for Design (SVD) IEEE 1800 SystemVerilog for Design (SVD) IEEE 1800 SystemVerilog Assertions (SVA) IEEE 1800 SystemVerilog for Verification (SVTB) IEEE 1850 Property Specification Language (PSL) IEEE 1647 E IEEE 1647, E
Methodology VMM, OVM, AVM, CDV, ABV
WorkshopsG t L l Si l ti (GLS) Gate Level Simulation (GLS)
ABV Beyond RTL (ABV) Coverage Driven Verification (CDV) OOP for functional Verification
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CVC Publications, tutorials, workshops
•Quick start guides Tutorials•Quick start guides, Tutorials • SVA • PSL• VMMVMM
•Workshops :•Gate Level Simulation•ABV beyond RTL
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y•Coverage Driven Verification•OOP for Verification
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