9/28/2015 1 Verilog Tutorial Adapted from Krste Asanovic Verilog Fundamentals • History • Data types • Structural Verilog • Functional Verilog Originally designers used manual translation + bread boards for verification Hardware design languages enabled logic level simulation and verification Once design were written in HDLs tools could be used for automatic translation Primary Verilog data type is a bit-vector where bits can take on one of four values
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9/28/2015
1
Verilog Tutorial
Adapted from Krste Asanovic
Verilog Fundamentals
• History
• Data types
• Structural Verilog
• Functional Verilog
Originally designers used manual translation + bread boards for verification
Hardware design languages enabled logic level simulation and verification
Once design were written in HDLs tools could be used for automatic translation
Primary Verilog data type is a bit-vector where bits can take on one of four values
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The Verilog keyword wire is used to denote a standard hardware net
Verilog includes ways to specify bit literals in various bases
Verilog Basics
• Data types
• Structural Verilog
• Functional Verilog
A Verilog module includes a module name and a port list
A Verilog module includes a module name and a port list
A module can instantiate other modules creating a module hierarchy
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A module can instantiate other modules creating a module hierarchy
A module can instantiate other modules creating a module hierarchy
Verilog supports connecting ports by position and by name
Let’s review how to turn our schematic diagram into structural Verilog
Let’s review how to turn our schematic diagram into structural Verilog
Verilog Fundamentals
• Data types
• Structural Verilog
• Functional Verilog
– Gate level
– Register transfer level
– High-level behavioral
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Functional Verilog can roughly be divided into three abstraction levels