UNIT II - 8086 SYSTEM BUS STRUCTURE 8086 signals – Basic configurations – System bus timing –System design using 8086 – IO programming – Introduction to Multiprogramming – System Bus Structure – Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to advanced processors. 8086 signals The 8086 Microprocessor operates in single processor or multiprocessor configurations (System contains two or more components that can execute instructions independently, then the system is called multiprocessor system) to achieve high performance. The pin configuration is as shown in fig1. Some of the pins serve a particular function in minimum mode (single processor mode) and others function in maximum mode (multiprocessor mode) configuration. The 8086 signals can be categorized in three groups. The first are the signals having common functions in minimum as well as maximum mode, the second are the signals which have special functions in minimum mode and third are the signals having special functions for maximum mode. 8086 PIN Diagram Signals with common functions in both Modes: The following signal description is common for both the minimum and maximum modes.
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UNIT II - 8086 SYSTEM BUS STRUCTURE
8086 signals – Basic configurations – System bus timing –System design using 8086 – IO programming –
Introduction to Multiprogramming – System Bus Structure – Multiprocessor configurations –
Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to advanced processors.
8086 signals
The 8086 Microprocessor operates in single processor or multiprocessor configurations (System
contains two or more components that can execute instructions independently, then the system is
called multiprocessor system) to achieve high performance. The pin configuration is as shown in
fig1. Some of the pins serve a particular function in minimum mode (single processor mode) and
others function in maximum mode (multiprocessor mode) configuration.
The 8086 signals can be categorized in three groups. The first are the signals having common
functions in minimum as well as maximum mode, the second are the signals which have special
functions in minimum mode and third are the signals having special functions for maximum
mode.
8086 PIN Diagram
Signals with common functions in both Modes:
The following signal description is common for both the minimum and maximum modes.
AD0-AD15 : These line are multiplexed bidirectional address/data bus. During T1 they carry lower
order address bus. In the remaining clock cycles, they carry 16 bit data. AD0-AD7 carry lower
order byte of data. AD0-AD15 carry higher order byte of data.
A19/S6, A18/S5, A17/S4, A16/S3:
During the first part of the machine cycle these are used to output upper 4-bits of address.
During remaining part of the machine cycles these are used to output status, which indicates the
type of operation to be performed in that cycle. S3 and S4 indicates the segment register being
used and S5 gives status of interrupt flag and S6 is always zero.
S4 S3 Register
0 0 ES
0 1 SS
1 0 CS or None
1 1 DS
BHE*/S7:
It stands for BUS HIGH ENABLE. It is used to indicate the transfer of data over higher order
data bus (D8-D15) if it is low. Otherwise the transfer is made on lower order byte AD7-AD0.
BHE A0 Data Access
0 0 Word
0 1 Upper byte from odd address
1 0 Lower byte from even address
1 1 None
NMI
It is a non maskable interrupt. It is an active high and an edge triggered interrupt.
INTR
It is a level triggered interrupt signal. It is active high
CLK
The clock input provides the basic timing for processor operation. Clock frequency depends on
the version of 8086.
Processor Required Clock Signal
8086 5Mhz
8086 -2 8 Mhz
8086-1 10 Mhz
RESET
It is a system reset and an active high signal. When its high, microprocessor enters into reset
states and terminates the current activity. It must be active for atleast four clock cycles to reset
the microprocessor.
READY: This is an acknowledge signal from slower I/O devices or memory. It is an active
high signal. When high, it indicates that the device is ready to transfer data. When low, then
microprocessor is in wait state.
TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution
will continue, else, the processor remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock.
RD (Read ) : If it is low then 8086 reads data from memory or an I/O device.
MN/MX: 8080 works in two modes namely Minimum mode and Maximum mode. If it is high, it
works in minimum mode. If it is low it works in maximum mode.
PIN description / Signals in Minimum Mode: ( 24 to 31)
INTA: This is an interrupt acknowledge signal. When microprocessor receives INTR signal,
acknowledges the interrupt by generation this signal. It is an active low signal.
ALE: This is an address latch enable signal. It indicates that valid address is available on bus
AD0-AD15.It is an active high signal and remains high during T1 state.
DEN-Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal.
DT/R: This is a Data Transmit/Receive signal. It decides the direction of data flow through the
transceiver. When it is high, data is transmitted out. When it is low, data is received in.
M/IO: This signal is issued by the microprocessor to distinguish memory access from I/O access.
When it is high, memory is accessed. When it is low, I/O devices are accessed.
WR: It is a write signal. It is used to write data in memory or output device. It is an active low
signal.
HOLD and HLDA: A high on HOLD pin indicates that another master (DMA) is requesting to
take over the system bus. On receiving HOLD signal processor outputs HLDA signal HIGH as
an acknowledgement.
PIN description or signals for Maximum Mode:
QS1 and QS0 : These pins provide the status of instruction queue.
QS0
QS1 Status
0 0 No operation
0 1 1st
byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue
S0, S1, S2 : These status signals indicate the operation being done by the microprocessor. This
information is required by the Bus controller 8288. Bus controller 8288 generates all memory
and I/O control signals.
S2 S1 S0 Status
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Inactive-passive
LOCK: This signal indicates that other processors should not ask CPU to relinquish the system
bus. When it goes low, all interrupts are masked and HOLD request is not granted.
RQ/GT1 and RQ/GT0.: These are request/ grant pins. Other processors request the CPU through
these lines to release the system bus. After receiving the request CPU Sends acknowledge signal
on the same lines.RQ/GT0 has higher priority than RQ/GT1.
*****
Basic configurations
General Bus Operation:
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus. The main reason behind multiplexing address and data over the same pins
is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package. The bus can be demultiplexed using a few latches and transceivers, whenever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to
as T1, T2, T3, T4.
The address is transmitted by the processor during T1, It is present on the bus only for
one cycle. The negative edge of this ALE pulse is used to separate the address and the
data or status information. The ALE signal is used activate latches and thus to latch the
address.
The data transfer occurs on the bus during T3and T4. The time interval T2 is used for
changing the direction of the bus during read operations.
Ready signal is sampled during T3.
The slower peripheral devices use this signal to indicate that the device is not ready to
send the desired data within specified time. Not ready indication is given by the slower
peripheral device. Wait state TW is inserted in between T2 and T3 to give enough access
time for the slower peripheral devices. Each wait state is of the same as a clock cycle.
During this wait state, the signals on the buses remain the same as they were at the start
of the WAIT state.
During WAIT state, if the Ready signal input is high then after the 8086 will go on with
the regular T4 of the machine cycle.
If the Ready input is low at the end of a WAIT state, then 8086 insert another WAIT state
until the Ready input is made high again.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
System design using 8086
Minimum Mode 8086 System
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transceivers, clock generator, memory and I/O
devices.
The figure shows the typical minimum mode 8086 system. Interacting of memory and
I/O devices are shown with the basic minimum mode 8086 configuration. Odd and even memory
banks are needed to interface with 8086. This is implemented using two EPROM and two
RAMs. Data lines D15-D8 are connected to odd bank of EPROM and RAM, and data lines D7-D0
are connected to even bank of EPROM and RAM. Address lines are connected to EPROM and
RAM. RD* signal is connected to the output enable (OE*) signals of EPROMs and RAMs. WR*
signal is connected to WR* signal of RAMs. Two separate decoders are used to generate chip
select signals for memory and I/O devices. These chip select signals are logically ORed with
either BHE* or A0 to generate final chip select signals. For generating final chip select signal for
odd bank decoder outputs are logically ORed with BHE* signal and for even bank decoder
outputs are logically ORed with A0 signal.
The 16-bit I/O interface RD* and WR* signals are connected to the RD* and WR*
signals of I/O devics. Data lines D15-D0 are connected to the data lines of I/O device. The chip
select signal for I/O device is generated using separate decoder whose output is enabled, when
M/IO* signal is low.
Bus Timing for Minimum Mode- Read operation
Read cycle timing diagram for minimum mode
Figure shows the read cycle timing diagram. The read cycle begins in T1 with the
assertion of the address latch enable (ALE) signal and also M/IO* signal.
During the negative going edge of this signal, the valid address is latched on the local
bus. The BHE* and A0 signals address low, high or both bytes. From Tl to T4, the
M/IO* signal indicates a memory or I/O operation.
At T2 the address is removed from the local bus and is sent to the output. The bus is then
tristated. The read (RD*) control signal is also activated in T2 .
The read (RD) signal causes the addressed device to enable its data bus drivers. After
RD* goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high, when the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.
Bus Timing for Minimum Mode- Write operation
Write cycle timing diagram for minimum mode
Figure shows the write cycle timing diagram. The write cycle begins in T1 with the
assertion of the address latch enable (ALE) signal and also M/IO* signal.
In T2 after sending the address in Tl the processor sends the data to be written to the
addressed location.
The data remains on the bus until middle of T4 state. The WR* becomes active at the
beginning of T2
The BHE* and A0 signals are used to select the proper byte or bytes of memory or I/O
word to be read or written. The M/IO*, RD* and WR* signals indicate the types of data
transfer as specified in table.
HOLD Response System
The figure shows the HOLD and HLDA signal timings in minimum mode system. The HOLD
pin is sampled at leading edge of each clock pulse. If it is sampled by the 8086 before T4 of the
previous cycle or during T1 of the current cycle, the 8086 activates HLDA in the next clock
cycle. It relinquishes the control of all buses and theand it is handed over to the requesting
master. The control of the bus is not regained by the 8086 until the requesting master does not
inactivate the HOLD pin. After that 8086 regains the control of buses and inactivate the HLDA
signal.
Maximum mode 8086 system
In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this
mode, the processor derives the status signals S2*, S1* and S0*. In this mode, additional
circuitry is required to translate the control signals. Th e additional circuitry is required to
converts the status signal into the I/0 and memory transfer signals.
The bus controller chip has input lines S2*, S1* and S0* and CLK. The basic functions
of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for memory
and I/O devices), DEN*, DT/R*, ALE, etc. using the information made available by the
processor on the status lines. These inputs to 8288 are driven by the CPU. It derives the outputs
ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*.
MRDC*: Memory read command – it instructs the memory to put the contents of the address location on the data bus.
MWTC*: Memory Write Command – It instructs the memory accepts the data on the data bus and load
the data into the addressed memory location.
IORC*: I/0 Read Command – it instructs an I/O device to put the data contained in the addressed port on the data bus.
IOWC*- I/O Write Command – It instructs an I/O device to accept the data on the data bus and load the
data into the addressed port. MCE/PDEN*: Master Cascade Enable/ Peripheral Data Enable – It controls the mode of operation of
8259 ( Interrupt controller). It selects cascade operation of interrupt controller and I/O bus transceiver.