Compiled by Mr. Vishal Gaikwad, SIESGST CHAPTER 04: Peripherals Interfacing with 8086 and Applications 8086-Interrupt structure. Programmable peripheral Interface 8255. Programmable interval Timer 8254. Elementary features of 8259A and 8257 and interface. Interfacing 8255, 8254 with 8086 and their applications. University Questions 1. Write a program to blink bit 4 of port C using BSR mode of 8255 [5M_May-2015] 2. Draw and explain interrupt structure of 8086 with its IVT. [10M_May-2015, Dec_2015 3. Explain Mode 0 and Mode 1 of 8254 Timer/Counter IC with the help of timing diagram. [10M_May-2015] 4. Explain different modes of operation of 8257 DMA controller. [10M_May-2015,May- 2017] 5. Explain the importance of DMA controller. Explain method of its interfacing with 8086. [10M_Dec-2015, Dec-2016,Dec-2017] 6. Explain in brief about programmable interval timer 8254. [5M_May-2016] 7. Explain 8086 interrupt structure and its method of interfacing with 8086 microprocessor with a suitable example.(any one interrupt) [10M_May-2016,May- 2018] 8. Explain in brief about programmable peripheral interface 8255. [5M_Dec-2016] 9. Write control word of 8255 to initialize port A as input port, port B and C as output port group A and B in mode 0.[5M_May-2017] 10. State purpose of interfacing 8259 PIC to 8086. Explain interfacing of 8086-minimum mode and 8259 single mode.[10M_May-2017] 11. What are the different types of interrupts supported by 8086 and explain IVT. [10M_May-2017,Dec-2017] 12. Write control word of 8255 to initialize port A as input port, port B and C as output port group A in mode 0 and Group B in mode 1.[5M_Dec-2017] 13. Explain Bit Set Reset mode of 8255 with application. [10M_Dec-2017] 14. Explain input output control word format of 8255. Write control word of 8255 to initialize port A as input port, port B and C as output port group A and B in mode 0. [10M_May-2018]
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Compiled by Mr. Vishal Gaikwad, SIESGST
CHAPTER 04: Peripherals Interfacing with 8086 and Applications
8086-Interrupt structure.
Programmable peripheral Interface 8255.
Programmable interval Timer 8254.
Elementary features of 8259A and 8257 and interface.
Interfacing 8255, 8254 with 8086 and their applications.
University Questions
1. Write a program to blink bit 4 of port C using BSR mode of 8255 [5M_May-2015]
2. Draw and explain interrupt structure of 8086 with its IVT. [10M_May-2015, Dec_2015
3. Explain Mode 0 and Mode 1 of 8254 Timer/Counter IC with the help of timing diagram.
[10M_May-2015]
4. Explain different modes of operation of 8257 DMA controller. [10M_May-2015,May-
2017]
5. Explain the importance of DMA controller. Explain method of its interfacing with
8086. [10M_Dec-2015, Dec-2016,Dec-2017]
6. Explain in brief about programmable interval timer 8254. [5M_May-2016]
7. Explain 8086 interrupt structure and its method of interfacing with 8086
microprocessor with a suitable example.(any one interrupt) [10M_May-2016,May-
2018]
8. Explain in brief about programmable peripheral interface 8255. [5M_Dec-2016]
9. Write control word of 8255 to initialize port A as input port, port B and C as output port
group A and B in mode 0.[5M_May-2017]
10. State purpose of interfacing 8259 PIC to 8086. Explain interfacing of 8086-minimum
mode and 8259 single mode.[10M_May-2017]
11. What are the different types of interrupts supported by 8086 and explain IVT.
[10M_May-2017,Dec-2017]
12. Write control word of 8255 to initialize port A as input port, port B and C as output port
group A in mode 0 and Group B in mode 1.[5M_Dec-2017]
13. Explain Bit Set Reset mode of 8255 with application. [10M_Dec-2017]
14. Explain input output control word format of 8255.
Write control word of 8255 to initialize port A as input port, port B and C as output port
group A and B in mode 0. [10M_May-2018]
Compiled by Mr. Vishal Gaikwad, SIESGST
4.1 8086-Interrupt structure:
An interrupt is a condition that halts the microprocessor temporarily to work on a different task
and then return to its previous task. Interrupt is an event or signal that request to attention of
CPU. This halt allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs the processor completes the execution of the current instruction
and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a
program that tells the processor what to do when the interrupt occurs. After the execution of
ISR, control returns back to the main routine where it was interrupted.
The following image shows the types of interrupts we have in a 8086 microprocessor −
The different types of interrupts present in 8086 microprocessor are given by:
1. Hardware interrupt - 8086 has two pins to accept hardware interrupts, NMI and INTR.
2. Software Interrupts - These interrupts are caused by writing the software interrupt
instruction INT n where ‘n’ can be any value from 0 to 255 (00H to FFH). Hence all 256
interrupts can be invoked by software.
3. Error conditions (Exception or types) - 8086 is interrupted when some special
conditions occur while executing certain instructions in the program. Example: An error
in division automatically causes the INT 0 interrupt.
1. Hardware Interrupts –
Hardware interrupts are those interrupts which are caused by any peripheral device by sending
a signal through a specified pin to the microprocessor. There are two hardware interrupts in
8086 microprocessor. They are:
(A) NMI (Non Maskable Interrupt) – It is a single pin non-maskable hardware interrupt
which cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its
Compiled by Mr. Vishal Gaikwad, SIESGST
execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008H
and CS is loaded from the word location 0000A H.
(B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O
port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive
any interrupt type, so the value of IP and CS will change on the interrupt type received.
2. Software Interrupts –
These are instructions that are inserted within the program to generate interrupts. There are 256
software interrupts in 8086 microprocessor. The instructions are of the format INT type where
type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H. These are 2
byte instructions.
The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0…..INT 4)
B. Reserved interrupts (INT 5…..INT 31)
C. Available interrupts (INT 32…..INT 225
Some important software interrupts are:
(A) TYPE 0 corresponds to division by zero(0).
(B) TYPE 1 is used for single step execution for debugging of program.
(C) TYPE 2 represents NMI and is used in power failure conditions.
(D) TYPE 3 represents a break-point interrupt.
(E) TYPE 4 is the overflow interrupt.
Interrupt Vector Table:
In an 8086 Interrupt system the first 1 Kbyte of memory from 00000H to 003FFH is reserved
for storing the starting addresses of interrupt service routines. This block of memory is often
called the interrupt vector table or the interrupt pointer table. Since 4 bytes are required to store
the CS and IP values for each interrupt service procedure, the table can hold the starting
addresses for 256 interrupt service routines. Following figure shows how the 256 interrupt
pointers are arranged in the memory table.
Compiled by Mr. Vishal Gaikwad, SIESGST
4.2 Programmable peripheral Interface 8255
The 8255 is a programmable peripheral interface i.e. PPI 8255.
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
The Intel 8255A is a general purpose programmable I/O device designed for use with Intel
microprocessors. It consists of three 8-bit bidirectional I/O ports (24 I/O lines) that can be
configured to meet different system I/O needs. The three ports are designated as PORT A,
PORT B and PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
Port B is same as PORT A or PORT B. However, PORT C is split into two parts- PORT C
lower (PC3-PC0) and PORT C upper (PC 7 -PC 4 ) by the control word. The four ports –two
8-bit PORTs and two 4-bit PORTs are divided in two groups
Group A (PORT A and upper PORT C)
Group B (PORT B and lower PORT C) for programming purpose.
Compiled by Mr. Vishal Gaikwad, SIESGST
These two groups can be programmed in three different modes:
1. Mode-0
2. Mode-1
3. Mode-2
Mode 0: In the first mode, mode-0, each group may be programmed in either input mode or
output mode (PORT A, PORT B, PORT C lower, PORT C upper).
Mode 1: In mode 1, each group may be programmed to have 8-lines of input or output (PORT
A or PORT B) and of the remaining 4-lines (PORT C lower or PORT C upper) 3-lines are used
for handshaking and interrupt control signals.
Mode 2: The third mode of operation, mode-2, is a bidirectional bus mode which uses 8- lines
(PORT A) only for a bidirectional bus and five lines (PORT C upper 4 lines and borrowing one
line from PORT C lower) for handshaking and control signals. PORT A and PORT B have
both input and output buffers and latches but PORT C has output latch and input buffer.
Pin Diagram of 8255:
The control word format of the 8255 is shown in Fig. below. The contents of the control register
are called the control word that specifies the input/ output functions of each port.
Compiled by Mr. Vishal Gaikwad, SIESGST
The control word register can be accessed to write the control word by selecting A1 and A0 in
high condition i.e. both ON. This register is not available for read operation.
As indicated in Fig, the most significant bit (D7) of the control word specifies either I/O
function or the bit set/ reset function. With D7= 1, the 8255 works in the I/O modes as shown
below.
With D7= 0, the 8255 works in BSR mode.
Port-C operates in BIT SET/RESET (BSR) mode with D7=0 as shown in above figure.
The BSR Mode in no way affects the functioning of port-A and port-B. Following steps are
essential to communicate with the peripherals through the ports of the 8255.
Determine address of ports-A, B, or C and of the control register according to the chip
select logic and the address lines A1 and A0.
Write the control word in the control word register.
Write input/output instructions in order to communicate with the peripherals through
ports-A, B, and C of the 8255.
Compiled by Mr. Vishal Gaikwad, SIESGST
4.3 Programmable interval Timer 8254:
The Intel 8254 are Programmable Interval Timers (PITs), which perform timing and
counting functions using three 16-bit counters.
The timer has three counters, numbered 0 to 2. Each channel can be programmed to operate
in one of six modes. Once programmed, the channels operate independently.
Each counter has two input pins – "CLK" (clock input) and "GATE" – and one pin, "OUT",
for data output. The three counters are 16-bit down counters independent of each other,
and can be easily read by the CPU.
Data bus buffer contains the logic to buffer the data bus between the microprocessor and
the internal registers. It has 8 input pins, usually labelled as D7-D0, where D7 is the MSB.
Read/write logic has 5 pins, which are listed below. The "X" denotes X is an active low