UNIT-7 power electronics

7/18/2019 UNIT-7 power electronics

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UNIT-VII FET AMPLIFIERS

Common Source JFET Amplifier

small signal amplifiers can also be made using Field Effect Transistors or FET's T!esede"ices !a"e #!e ad"an#age o"er bipolar #ransis#ors of !a"ing e$#remel% !ig! inpu#impedance along &i#! a lo& noise ou#pu# ma'ing #!em ideal for use in amplifier circui#s#!a# !a"e "er% small inpu# signals T!e design of an amplifier circui# based around a

(unc#ion field effec# #ransis#or or )*FET)+ ,n-c!annel FET or e"en a me#al o$ide siliconFET or )M.SFET) is e$ac#l% #!e same principle as #!a# for #!e bipolar #ransis#or circui#Firs#l%+ a sui#able /uiescen# poin# or )0-poin#) needs #o be found for #!e correc# biasing of #!e *FET amplifier circui# &i#! single amplifier configura#ions of 1ommon-source ,1S+1ommon-drain ,12 or Source-follo&er ,SF and #!e 1ommon-ga#e ,13 a"ailable formos# FET de"ices T!ese #!ree *FET amplifier configura#ions correspond #o #!e common-emi##er+ emi##er-follo&er and #!e common-base configura#ions using bipolar #ransis#orsT!e Common Source JFET Amplifier as #!is is #!e mos# &idel% used *FET amplifierdesign T!e common source *FET amplifier circui# is s!o&n belo&

T!e amplifier circui# consis#s of an N-c!annel *FET+ connec#ed in a common sourceconfigura#ion T!e *FET ga#e "ol#age Vg is biased #!roug! #!e po#en#ial di"ider ne#&or'se# up b% resis#ors R4 and R5 and is biased #o opera#e &i#!in i#s sa#ura#ion region &!ic! ise/ui"alen# #o #!e ac#i"e region of #!e bipolar (unc#ion #ransis#or Unli'e a bipolar#ransis#or circui#+ #!e (unc#ion FET #a'es "ir#uall% no inpu# ga#e curren# allo&ing #!e ga#e#o be #rea#ed as an open circui# T!en no inpu# c!arac#eris#ics cur"es are re/uired Since#!e N-1!annel *FET is a deple#ion mode de"ice and is normall% ).N)+ a nega#i"e ga#e"ol#age &i#! respec# #o #!e source is re/uired #o modula#e or con#rol #!e drain curren#T!is nega#i"e "ol#age can be pro"ided b% biasing from a separa#e po&er suppl% "ol#age or b% a self biasing arrangemen# as long as a s#ead% curren# flo& #!roug! #!e *FET e"en&!en #!ere is no inpu# signal presen# and Vg main#ains a re"erse bias of #!e ga#e-source

pn (unc#ion In #!is e$ample #!e biasing is pro"ided from a po#en#ial di"ider ne#&or'allo&ing #!e inpu# signal #o produce a "ol#age fall a# #!e ga#e as &ell as "ol#age rise a# #!e



ga#e &i#! a sinusoidal signal An% sui#able pair of resis#or "alues in #!e correc# propor#ions &ould produce #!e correc# biasing "ol#age so #!e 21 ga#e biasing "ol#age Vgis gi"en as6

T!e inpu# signal+ ,Vin of #!e common source *FET amplifier is applied be#&een #!e 3a#e#erminal and #!e 7ero "ol#s rail+ ,8" 9i#! a cons#an# "alue of ga#e "ol#age Vg applied #!e*FET opera#es &i#!in i#s ).!mic region) ac#ing li'e a linear resis#i"e de"ice T!e draincircui# con#ains #!e load resis#or+ Rd T!e ou#pu# "ol#age+ Vou# is de"eloped across #!isload resis#ance T!e efficienc% of #!e common source *FET amplifier can be impro"ed b%#!e addi#ion of a resis#or+ Rs included in #!e source lead &i#! #!e same drain curren#flo&ing #!roug! #!is resis#or Resis#or+ Rs is also used #o se# #!e *FET amplifiers )0- poin#)

9!en #!e *FET is s&i#c!ed full% ).N) a "ol#age drop e/ual #o Rs $ Id is de"elopedacross #!is resis#or raising #!e po#en#ial of #!e source #erminal abo"e 8" or ground le"elT!is "ol#age drop across Rs due #o #!e drain curren# pro"ides #!e necessar% re"erse

biasing condi#ion across #!e ga#e resis#or+ R5 effec#i"el% genera#ing nega#i"e feedbac' Inorder #o 'eep #!e ga#e-source (unc#ion re"erse biased+ #!e source "ol#age+ Vs needs #o be!ig!er #!an #!e ga#e "ol#age+ Vg T!is source "ol#age is #!erefore gi"en as6

T!en #!e 2rain curren#+ Id is also e/ual #o #!e Source curren#+ Is as )No 1urren#) en#ers#!e 3a#e #erminal and #!is can be gi"en as6

T!is po#en#ial di"ider biasing circui# impro"es #!e s#abili#% of #!e common source *FET

amplifier circui# &!en being fed from a single 21 suppl% compared #o #!a# of a fi$ed

"ol#age biasing circui# :o#! resis#or+ Rs and #!e source b%-pass capaci#or+ 1s ser"e

basicall% #!e same func#ion as #!e emi##er resis#or and capaci#or in #!e common emi##er

bipolar #ransis#or amplifier circui#+ namel% #o pro"ide good s#abili#% and pre"en# a

reduc#ion in #!e loss of #!e "ol#age gain ;o&e"er+ #!e price paid for a s#abili7ed /uiescen#

ga#e "ol#age is #!a# more of #!e suppl% "ol#age is dropped across Rs

T!e basic circui# and c!arac#eris#ics of a Common Source JFET Amplifier are "er% similar #o #!a# of #!e common emi##er amplifier A 21 load line is cons#ruc#ed b% (oining #!e #&o poin#s rela#ing #o #!e drain curren#+ Id and #!e suppl% "ol#age+ Vdd remembering



#!a# &!en Id < 86 , Vdd < Vds and &!en Vds < 86 , Id < Vdd=R L T!e load lineis #!erefore #!e in#ersec#ion of #!e cur"es a# #!e 0-poin# as follo&s

Common Source JFET Amplifier Characteristics Curves

As &i#! #!e common emi##er bipolar circui#+ #!e 21 load line for #!e common source

*FET amplifier produces a s#raig!# line e/ua#ion &!ose gradien# is gi"en as6 -4=,Rd > Rsand #!a# i# crosses #!e "er#ical Id a$is a# poin# A e/ual #o Vdd=,Rd > Rs T!e o#!er end of #!e load line crosses #!e !ori7on#al a$is a# poin# : &!ic! is e/ual #o #!e suppl% "ol#age+Vdd T!e ac#ual posi#ion of #!e 0-poin# on #!e 21 load line is generall% posi#ioned a# #!emid cen#re poin# of #!e load line ,for class-A opera#ion and is de#ermined b% #!e mean"alue of Vg &!ic! is biased nega#i"el% as #!e *FET is a deple#ion-mode de"ice Li'e #!e bipolar common emi##er amplifier #!e ou#pu# of #!e Common Source JFET Amplifier is

4?8o ou# of p!ase &i#! #!e inpu# signal

.ne of #!e main disad"an#ages of using 2eple#ion-mode *FET is #!a# #!e% need #o benega#i"el% biased S!ould #!is bias fail for an% reason #!e ga#e-source "ol#age ma% rise

and become posi#i"e causing an increase in drain curren# resul#ing in failure of #!e drain"ol#age+ Vd Also #!e !ig! c!annel resis#ance+ Rds,on of #!e (unc#ion FET+ coupled &i#!!ig! /uiescen# s#ead% s#a#e drain curren# ma'es #!ese de"ices run !o# so addi#ional!ea#sin' is re/uired ;o&e"er+ mos# of #!e problems associa#ed &i#! using *FET@s can begrea#l% reduced b% using en!ancemen#-mode M.SFET de"ices ins#ead

MOSFETs or Me#al .$ide Semiconduc#or FET@s !a"e muc! !ig!er inpu# impedances andlo& c!annel resis#ances compared #o #!e e/ui"alen# *FET Also #!e biasing arrangemen#sfor M.SFETs are differen# and unless &e bias #!em posi#i"el% for N-c!annel de"ices and

nega#i"el% for P-c!annel de"ices no drain curren# &ill flo&

Common Gate amplifier.

A common-gate amplifier is one of #!ree basic single-s#age field-effec# #ransis#or ,FETamplifier #opologies+ #%picall% used as a curren# buffer or "ol#age amplifier In #!is circui##!e source #erminal of #!e #ransis#or ser"es as #!e inpu#+ #!e drain is #!e ou#pu# and



#!e ga#e is common #o bo#!+ !ence i#s name T!e analogous bipolar (unc#ion #ransis#or circui# is #!e common-base amplifier

Figure 46 :asic N-c!annel common-ga#e circui# ,neglec#ing biasing de#ails curren#source I D represen#s an ac#i"e load signal is applied a# node V in and ou#pu# is #a'enfrom node V out ou#pu# can be curren# or "ol#age

Figure 56 ;%brid pi model &i#! #es# source i x a# ou#pu# #o find ou#pu# resis#ance

T!e amplifier c!arac#eris#ics are summari7ed belo& in Table 4 T!e appro$ima#ee$pressions use #!e assump#ions ,usuall% accura#e r O BB R L and g mr O BB 4

e

Short-circuit

current gain

"pen-circuit

voltage gain

#nput resistance

"utput resistance

http://en.wikipedia.org/wiki/Gain




http://en.wikipedia.org/wiki/Input_resistance

http://en.wikipedia.org/wiki/Output_resistance




http://en.wikipedia.org/wiki/Input_resistance

http://en.wikipedia.org/wiki/Output_resistance




In general #!e o"erall "ol#age=curren# gain ma% be subs#an#iall% less #!an #!eopen=s!or# circui# gains lis#ed abo"e ,depending on #!e source and load resis#ancesdue #o #!e loading effec#

1losed circui# "ol#age gain

Ta'ing inpu# and ou#pu# loading in#o considera#ion+ #!e closed circui# "ol#age gain ,#!a#is+ #!e gain &i#! load R L and source &i#! resis#ance RS bo#! a##ac!ed of #!e commonga#e can be &ri##en as6

+

9!ic! !as #!e simple limi#ing forms

+

2epending upon &!e#!er g m RS is muc! larger or muc! smaller #!an one

In #!e second case RS CC 4= g m and #!e T!D"enin represen#a#ion of #!e source is useful+

producing #!e second form for #!e gain+ #%pical of "ol#age amplifiers :ecause #!e inpu#impedance of #!e common-ga#e amplifier is "er% lo&+ #!e cascode amplifier of#en is usedins#ead T!e cascode places a common-source amplifier be#&een #!e "ol#age dri"er and #!e

common-ga#e circui# #o permi# "ol#age amplifica#ion using a dri"er &i#! RS >> 1/g m

Common !rain amplifier or Source Follo$er.

A common-drain amplifier+ also 'no&n as a source follo$er+ is one of #!ree basicsingle-s#age field effec# #ransis#or ,FET amplifier #opologies+ #%picall% used as a "ol#age buffer In #!is circui# #!e ga#e #erminal of #!e #ransis#or ser"es as #!e inpu#+ #!e source is#!e ou#pu#+ and #!e drain is common #o bo#! ,inpu# and ou#pu#+ !ence i#s name T!e

analogous bipolar (unc#ion #ransis#or circui# is #!e common-collec#or amplifier T!iscircui# is used #o #ransform impedances

:asic N-c!annel *FET source follo&er circui# ,neglec#ing biasing de#ails

A# lo& fre/uencies+ #!e source follo&er !as #!e follo&ing small signal c!arac#eris#ics



%oltage gain&

Current gain&

#nput impedance&

"utput impedance&

T!e "ariable g m #!a# is no# lis#ed in Figure 4 is #!e #rans conduc#ance of #!ede"ice ,usuall% gi"en in uni#s of Siemens

FET iasing methods.

Unli'e :*Ts+ #!ermal runa&a% does no# occur &i#! FETs ;o&e"er+ #!e &ide

differences in ma$imum and minimum transfer characteristics ma'e I2 le"elsunpredic#able &i#! simple fi$ed-ga#e bias "ol#age To ob#ain reasonable limi#s on

/uiescen# drain curren#s I2 and drain-source "ol#age V2S+ source resis#or and po#en#ial

di"ider bias #ec!ni/ues mus# be used 9i#! fe& e$cep#ions+ M.SFET bias circui#s aresimilar #o #!ose used for JFETs Various FET biasing circui#s are discussed belo&

Fi(ed ias.

21 bias of a FET de"ice needs se##ing of ga#e-source "ol#age V3S #o gi"e desired drain

curren# I2 For a *FET drain curren# is limi#ed b% #!e sa#ura#ion curren# I2S Since #!e



FET !as suc! a !ig! inpu# impedance #!a# no ga#e curren# flo&s and #!e dc "ol#age of#!e ga#e se# b% a "ol#age di"ider or a fi$ed ba##er% "ol#age is no# affec#ed or loaded b%#!e FET

Fi$ed dc bias is ob#ained using a ba##er% V03 T!is ba##er% ensures #!a# #!e ga#e is al&a%snega#i"e &i#! respec# #o source and no curren# flo&s #!roug! resis#or R 3 and ga#e#erminal #!a# is I3 <8 T!e ba##er% pro"ides a "ol#age V3S #o bias #!e N-c!annel *FET+ bu#

no resul#ing curren# is dra&n from #!e ba##er% V33 Resis#or R 3 is included #o allo& an%ac signal applied #!roug! capaci#or 1 #o de"elop across R 3 9!ile an% ac signal &illde"elop across R 3+ #!e dc "ol#age drop across R 3 is e/ual #o I3 R 3 i.e. 8 "ol#

T!e ga#e-source "ol#age V3S is #!en

V3S ) - V3 VS < V33 8 < V33

T!e drain -source curren# I2 is #!en fi$ed b% #!e ga#e-source "ol#age as de#ermined b%e/ua#ion

T!is curren# #!en causes a "ol#age drop across #!e drain resis#or R 2 and is gi"en as VR2 <I2 R 2 and ou#pu# "ol#age + Vou# < V22 I2 R 2

Self-ias.

T!is is #!e mos# common me#!od for biasing a *FET Self-bias circui# for N-c!annel*FET is s!o&n in figure

Since no ga#e curren# flo&s #!roug! #!e re"erse-biased ga#e-source+ #!e ga#e curren# I3 <

8 and+ #!erefore+"3 < i3 R 3 < 8 9i#! a drain curren# I2 #!e "ol#age a# #!e S is Vs< I2 R s

T!e ga#e-source "ol#age is #!en



V3s < V3 - Vs < 8 I2 R s < I2 R s

So "ol#age drop across resis#ance R s pro"ides #!e biasing "ol#age V3g and no e$#ernalsource is re/uired for biasing and #!is is #!e reason #!a# i# is called self-biasing

T!e opera#ing poin# ,ie 7ero signal I2 and V2S can easil% be de#ermined from e/ua#ion

and e/ua#ion gi"en belo& 6

V2S < V22 I2 *R 2 > R S

T!us dc condi#ions of *FET amplifier are full% specified Self biasing of a *FET s#abili7esi#s /uiescen# opera#ing poin# agains# an% c!ange in i#s parame#ers li'e #rans conduc#anceLe# #!e gi"en *FET be replaced b% ano#!er *FET !a"ing #!e double conduc#ance #!endrain curren# &ill also #r% #o be double bu# since an% increase in "ol#age drop across R s+#!erefore+ ga#e-source "ol#age+ V3S becomes more nega#i"e and #!us increase in draincurren# is reduced

+otential-!ivider iasing.

A slig!#l% modified form of dc bias is pro"ided b% #!e circui# s!o&n in figure T!eresis#ors R 3l and R 35 form a po#en#ial di"ider across drain suppl% V22 T!e "ol#age V5

across R 35 pro"ides #!e necessar% bias T!e addi#ional ga#e resis#or R 3l from ga#e #osuppl% "ol#age facili#a#es in larger ad(us#men# of #!e dc bias poin# and permi#s use of larger "alued R S

T!e ga#e is re"erse biased so #!a# I3 < 8 and ga#e "ol#age

V3 <V5 < ,V22=R 34 > R 35 R 35

And



V3S ) V3 VS < V3 - I2 R S

T!e circui# is so designed #!a# I2+ Rs is grea#er #!an V2 so #!a# V3S is nega#i"e T!is pro"ides correc# bias "ol#age

T!e opera#ing poin# can be de#ermined as

I2 < ,V5 V3S= R S

And

V2S < V22 I2 ,R 2 > R S

G E$plain FET as a "ol#age "ariable resis#or,VVR

FET AS A V.LTA3E VARIA:LE RESIST.R ,VVR6

FET is opera#ed in #!e cons#an# curren# por#ion of i#s ou#pu# c!arac#eris#ics for #!e linear applica#ions In #!e region before pinc! off + &!ere Vds is small #!e drain #o source

resis#ance rd can be con#rolled b% #!e bias "ol#age VgsT!e FET is useful as a "ol#age"ariable resis#or ,VVR or Vol#age 2ependen# resis#or

In *FET #!e drain source conduc#ance gd < Id=Vds for small "alues of Vds &!ic! ma% bee$pressed as gd < gdo H 4-, VgsVp

4=5 &!ere gdo is #!e "alue of drain conduc#ance

&!en #!e bias "ol#age Vgs is 7eroSmall signal FET drain resis#ance rd "aries &i#!applied ga#e "ol#age Vgs and FET ac# li'e a VARIA:LE PASSIVE RESIST.R

9!en V2S C VP+ Id V2S+ &!en V3S is cons#an# ie+ FET ac#s as a resis#orIn #!is regionFET is used as a Vol#age con#rolled resis#or .r Vol#age "ariable resis#or .r Vol#agedependan# resis#or

!ifferences bet$een JT and FET

4 FET is uni polar de"ice curren# I2 is due #o ma(ori#% ,9!ere as :*T is:ipolar c!arge carries onl%



5 FET is less nois% as #!ere are no (unc#ions,in conduc#ion c!annel FET

J FET Inpu# impedance is "er% !ig! ,488 M ,due #o re"erse bias

K FET is "ol#age con#rolled de"ice+ :*T is curren# con#rolled de"ice

G FETs are eas% #o fabrica#e

FET performance does no# c!ange muc! &i#! #empera#ure FET !as Ve #emp1oefficien#+ :*T !as >Ve #emp coefficien#

FET !as !ig!er s&i#c!ing speeds

? FET is useful for small signal opera#ion onl%

:*T is c!eaper #!an FET

,ni-Junction Transistor*,JT

A uniunction transistor ,,JT is an elec#ronic semiconduc#or de"ice #!a# !as onl% one (unc#ion T!e U*T !as #!ree #erminals6 an emi##er ,E and #&o bases ,:4 and :5 T!e base is formed b% lig!#l% doped n-#%pe bar of silicon T&o o!mic con#ac#s :4 and :5 area##ac!ed a# i#s ends T!e emi##er is of p-#%pe and i# is !ea"il% doped T!e resis#ance be#&een :4 and :5+ &!en #!e emi##er is open-circui# is called in#erbase resis#ance

T!e U*T is biased &i#! a posi#i"e "ol#age be#&een #!e #&o bases T!is causes a po#en#ialdrop along #!e leng#! of #!e de"ice 9!en #!e emi##er "ol#age is dri"en appro$ima#el%one diode "ol#age abo"e #!e "ol#age a# #!e poin# &!ere #!e P diffusion ,emi##er is+curren# &ill begin #o flo& from #!e emi##er in#o #!e base region :ecause #!e base regionis "er% lig!#l% doped+ #!e addi#ional curren# ,ac#uall% c!arges in #!e base region causes

conduc#i"i#% modula#ion &!ic! reduces #!e resis#ance of #!e por#ion of #!e base be#&een#!e emi##er (unc#ion and #!e :5 #erminal T!is reduc#ion in resis#ance means #!a# #!eemi##er (unc#ion is more for&ard biased+ and so e"en more curren# is in(ec#ed ."erall+#!e effec# is a nega#i"e resis#ance a# #!e emi##er #erminal T!is is &!a# ma'es #!e U*Tuseful+ especiall% in simple oscilla#or circui#s

Construction& A unijunction transistor is composed of a bar of N-#%pe silicon !a"ing a P-#%pe connec#ion in #!e middle S!o&n in Figure belo&,a T!e connec#ions a# #!e endsof #!e bar are 'no&n as bases :4 and :5 #!e P-#%pe mid-poin# is #!e emi##er 9i#! #!eemi##er disconnec#ed+ #!e #o#al resis#ance R ::.+is #!e sum of R :4 and R :5 as s!o&n inFigure belo&,b T!e in#rinsic s#andoff ra#io O is #!e ra#io of R :4 #o R ::. I# "aries from8K #o 8? for differen# de"ices T!e sc!ema#ic s%mbol is Figure belo&,c



Unijunction transistor !a" #onstruction$ !%" Mo&e'$ !c" S(m%o'

T!e Uni-(unc#ion emi##er curren# "s "ol#age c!arac#eris#ic cur"e ,Figure belo&,a

s!o&s #!a# as VE increases+ curren# IE increases up IP a# #!e pea' poin# :e%ond #!e pea' poin#+ curren# increases as "ol#age decreases in #!e nega#i"e resis#ance region T!e"ol#age reac!es a minimum a# #!e "alle% poin# T!e resis#ance of R :4+ #!e sa#ura#ionresis#ance is lo&es# a# #!e "alle% poin# VP is #!e "ol#age drop across R :4 plus a 8Vdiode drop see Figure belo&,b VV is es#ima#ed #o be appro$ima#el% 48 of V::

? 2escribe #!e applica#ion of U*T as a rela$a#ion oscilla#or

T!e rela$a#ion oscilla#or in Figure belo& is an applica#ion of #!e uni(unc#ion oscilla#orR E c!arges 1E un#il #!e pea' poin# T!e uni(unc#ion emi##er #erminal !as no effec# on #!e

capaci#or un#il #!is poin# is reac!ed .nce #!e capaci#or "ol#age+ VE+ reac!es #!e pea'"ol#age poin# VP+ #!e lo&ered emi##er-base4 E-:4 resis#ance /uic'l% disc!arges #!ecapaci#or .nce #!e capaci#or disc!arges belo& #!e "alle% poin# VV+ #!e E-R:4 resis#ancere"er#s bac' #o !ig! resis#ance+ and #!e capaci#or is free #o c!arge again



2uring capaci#or disc!arge #!roug! #!e E-:4 sa#ura#ion resis#ance+ a pulse ma% be seenon #!e e$#ernal :4 and :5 load resis#ors+ Figure abo"e T!e load resis#or a# :4 needs #o be lo& #o no# affec# #!e disc!arge #ime T!e e$#ernal resis#or a# :5 is op#ional I# ma% bereplaced b% a s!or# circui# T!e appro$ima#e fre/uenc% is gi"en b% 4=f < T < R1 A moreaccura#e e$pression for fre/uenc% is gi"en in Figure abo"e

T!e c!arging resis#or R E mus# fall &i#!in cer#ain limi#s I# mus# be small enoug! #o allo&IP #o flo& based on #!e V :: suppl% less V P I# mus# be large enoug! #o suppl% IV basedon #!e V:: suppl% less VV

UNIT-7 power electronics

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