UNB - Library and Archives Canada PSK Modulation and Demodulation ... 4.2 Demodulator Code Components ... Figure 4- 1 Demodulator Implemeitation Block Diagram ...

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Abstract

With increasing demands being placed on available bandwidth for data

communications systems, there is a requirement for bandwidth efficient modulation

protocols to minimize overall spectnun requirements. Often, it is also desirable to

maintain low overall bit error rates, particularly in wireless applications such as HF

radio.

Multiple carrier modulation techniques can provide high bandwidth efficiencies in

both wireless and 'land line" (wired) communications links. This thesis presents the

development of a parallel phase shift keying demodulator, able to demodulate four

simultaneous BPSK modulated independent carrier tones at keying speeds of 3 1.25

Baud. The system has also been proven to be able to isolate and demodulate single

modulated channel carriers f?om 600 Baud BPSK up to 300 Baud 8PSK in a multiple

parallel carrier environment. The previous generation PSK demodulator at UNB

operated on a single DSP CPU, with a "conventionai" single carrier tone signal. The

work presented here is a p d e l processing implementation on a multiprocessor

platform, incorporating narrowband input signal filtering? demodulating up to four

independent carrier tones simultaneously. Taking advantage of the powerful parallel

processing huictions of the DSP hardware, the demodulator remains flexible through

software parameter reconfiguration to p d t variations in carrier fiequencies,

modulation orders, and keying speeds on each carrier tone.

Acknowledgements

Without the assistance of the individuals 1 shall List below, completion of this project

would most certainly have been doubtful. 1 extend my deepest thanks to Dr. Richard

Tervo for his support and guidance throughout the course of the work; appreciations

and gratitude are also extended to Cindy Robichaud for the assistance she graciously

offered at various stages dong the way. 1 offer sincerest thanks to Patrick McCarthy

for his help with the screen capture software used in the presentation of results;

appreciation is also extended to Derrick Whalen for the valuable senice he provideâ

in helping to produce the scan images. 1 remain thaakful to those faculty members

who offered their support via numemus Teaching Assistantships to substantially

lessen the financial burden of my studies. My highest regards and appreciations are

offered to the Electrical Engineering office staff (Shelley, Saundra, Denise, Laurie,

and Linda), past and present, for their assistance over the years 1 have spent at UNB.

Finally, 1 wish to express my th& to my family and fkiends for their encouragement

and support.

Table of Contents

. . Abstract.. .................................................................. .il

S.. ..................................................... Acknowledgements. .u

...................................................... Table of Contents.. .iv

... ........................................................... List of Tables.. vrii

............................................................ List of Figures.. ix

List of Symbols and Abbrevirtions.. ................................. .xi

CHAPTER 1

............................................................. INTRODUCTION. .1

. . .......................................................... 1 . 1 Motivabon.. 1

. . ........................................................... 1.2 Objective. .2

CHAPTER II

... DEMAND FOR BANDWIDTH - CAUSES AND SOLUTIONS.. ..4

2.1 Increasing Demands for Bandwidth.. ............................. 5

2.2 Emerging Solutions to Bandwidth Constraint Limitations.. ..7

...................................................... 2.3 DSP Systems.. 10

........................................... 2.4 Previous Work at UNB. 1 1

...................................... 2.5 The Development System.. .12

THEORETICAL BACKGROUND . MODULATION AND .......................................................... DEMODULATION 16

3.1 PSK Modulation and Demodulation O An O v e ~ e w .................. 16

3.2 PSK Modulation and Demodulation . Theoreticai Background ... 17

............................................... 3.3 Digital Filtering Overview 24

............................... 3.4 A Parallel Carrier Pmtocol: CL0VER.U 31

CHAPTER IV

................................................. DEMODULATOR SOFTWARE 35

................................................. 4.1 Overall Program Mode1 35

...................................... 4.2 Demodulator Code Components 38

................................... 4.2.1 Intempt S e ~ c e Routine 38

........................................ 4.2.2 Input Signal Filtering 39

....................... 4.2.3 Data Exchange nom Node to Node 40

.................................... 4.2.4 The Demodulation Loop 41

.................................... 4.2.5 Automatic Gain Control 42

.............................. 4.2.6 Symbol/Bit Synchronization 42

4.2.7 Carrier Lock Adjustments ................................. 43

4.2.8 Symbol Output .............................................. 44

CHAPTER v

........................... DEMODULATION TESTING AND RESULTS 45

5.1 Synthesizer Generated Test Sigoals ................................. 45

5.2 CLOVER-II Generated Test Signals ................................ 61

5.3 Actual Received Radio Signals ...................................... 65

5.4 Filtering Verification .................................................. 66

CHAPTER VI

................................................................... CONCLUSIONS 69

APPENDIX I

DEMODULATOR SOURCE CODE EXAMPLES ......................... 76

Demodulation Code for "CPU-A" ...................................... -76

Demodulation Code for "CPU C" ....................................... 85 -

APPENDIX II

SAMPLE BATCH FILES FOR CODE COMPILATION ................ 94

APPENDIX III

SAMPLE CALLING PROGRAM ............................................. 95

APPENDIX IV

CALLING PROGRAM WITH BPSK BITSTREAM DISPLAY ......... 102

APPENDIX v

CONVOLUTION ROUTINE ................................................. 1 O8

APPENDIX Vi

ORIGINAL FILTERING CODE a C VERSION .......................... 110

List of Tables

................................................. Table 3-1 Typical Window Function Propdes 28

.............. Table 5- 1 Maximum Baud Rates-Multipmcessor Single Tone Demodulation 47

................................. Table 5-2 Maximum Baud Rates-Four Independent Carriers 55

viii

List of Figures

Figure 2-1 Spectrum Signal Proassig Quad C40 Board Schematic ..................... 15

Figure 3-1 Coherent PSK Demodulator Phase Lock Loop ................................. 20

Figure 3-2 Modifîed PLL for Carrier S ynchronizaüon ..................................... 22

Figure 3-3 Ideal Low Pais FilterfBandpw FUter Characteristic ......................... 30

......................................................... Figure 3-4 Typical Multipath Scenario 31

Figure 3-5 CLOVER-II Carrier Tone Sequence .............................................. 33

Figure 4- 1 Demodulator Implemeitation Block Diagram .................................. 37

.......................................................... Figure 4-2 SymboVPhase Assignment 42

Figure 5- 1 Single Tone Multiprocessor Demodulation-2PSK 300 Baud ................ 48

Figure 5-2 Single Tone Multiprocesaor Demodulation -3000Hz Fiiter. 2PSK 1200 Baud. ............................................ 49

Figure 5-3 Single Tone Multiprocessor Demodulation-QPSK 300 Baud ............... 50

Figure 5-4 Single Tone Multiprocessor Demodulation ........................................... -3000Hz Filter. QPSK 1200 Baud. 51

................. Figure 5-5 Single Tone Multiprocessor Demodulation-8PSK 50 Baud 52

Figure 5-6 Single Tone Multiprocessor Demodulation 3000Hz Filter. 8PSK 600 Baud. ............................................... 53

......... Figure 5-7 Four Carrier Tone Demodulation.1.5kHz Filter. 2PSK 600 Baud 56

Figure 5-8 Four Carrier Tone Demodulation-500Hz Filter. QPSK 300 Baud ......... 57

Figure 5-9 Four Carrier Tone Demodulation-lkHz Fiter. 8PSK 300 Baud ........... 58

.................................... Figure 5- 10 Demodulation With Noise-8PSK 300 Baud 60

.................................... Figure 5-1 1 CLOVER Four Tone Test BPSK Symbols 62

........................ Figure 5-12 CLOVER Four Tone Test BPSK Output Bitstream 63

Figure 5- 13 Filter Response to White Noise Input-C Fiiter.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 5- 14 Fiiter Response to White Noise Input-CONVOLVE Routine.. . . . . . . . . . . .67

Figure 5-1 5 Four Tone Test Filtering and Demodulation - CONVOLVE Routine.. .68

List of Symbols and Abbreviations

ADC

ADM

ADSL

AGC

AM

ARQ

BFSK

bps

CCITT

CLOVER

COFF

CPU

DIA

dB

DMA

DPSK

DSP

DSPLINK2

Analog to Digital

Analog to Digital Converter

Analog Daughter Module

Asymmetrical Digital Subscriber Line

Automatic Gain Control

Amplitude Modulation

Automatic Repeat Request

Binary Frequency Shifi Keying

Bits per second

Consultative Cornmittee For International Telephone and Telegraph

HAL Communicatio11~ Corp. Trademarked Data Communications Protocol

Cornmon Object File Format

Central Processing Unit

Digital to Analog

Decibel

Direct Memory Access

Differential Phase Shifi Keying

Digital Signal Processor

Loughborough Sound Images Trademarked Interfacing Standard

Center Frequency

Cutoff Frequency

FEC

FIR

FSK

h",,,uk

HF

HP

Hz

IIR

VO

ISR

ITU

JPEG

kbps

kHz

LIA

LMCS

LSI

Mbps

M N P S

MOPS

MPEG

mV

Forward Error ControVCorrection

Finite Impulse Response

Frequency Shifi Keying

Impulse Response (ideal) for FIR Filter

High Frequency

Hewlett Packard

Hertz

infinite Impuise Response

IIlputlOutput

Interrupt SeMce Routine

International Telecornmunications Union

Joint Photographie Experts Gmup

Kilobits (one thousand bits) Per Second

Kilohertz (one thousand Hertz)

Link Interface Adapter

Local Multipoint Communications SeMces

Loughborough Sound Images

Megabits (one million bits) Per Second

Microcorn Networking Rotocol 5

Million Operations Per Second

Motion Picture Experts Gmup

Millivolt

xii

NCO Numencally Controlled Oscillator

PC Personal Cornputer

PCS Personal Communications Services

PLL Phase Lock Loop

PSK Phase Shift Keying

PSM Phase Shift Modulation

PSTN Public Switched Telephone Network

QAM Quadrature Amplitude Modulation

QPSK Quadrature Phase Sbift Keying

S Number of Sarnples per Penod

TI Texas Instruments

TMS320C30 Texas Instruments Third Generation Floating Point DSP Chip

TMS320C40 Texas Instruments Fourth Generation Floating Point DSP Chip

UNB University of New Brunswick

v Volt

v.42bis Voiceband ITU/CCITT Telephone Modem Coding Standard, With Compression

VLSI Very Large Scale Integration

VME MC68000-Based Hi&-Speed Multiprocessor Bus

xiii

Chapter 1

INTRODUCTION

1.1 Motivation

The past decade has seen an unprecedented increase in demand for high speed

communications. Increasingly, intbnnation is being transmitted digitally to allow for

greater throughput, reliability, and reduced error rates. More and more high bandwidth

applications are emerging, such as digital video, high speed file transfer, remote hosting

of applications on servers, videoconferencing, and many others too nurnerous to mention.

This trend is further taxing the capacity of communications channels and networks based

on traditional time-honored modulation approaches, and bas created the need for more

efficient and robust modulation techniques to better utilize the limited available

bandwidth.

Advancements in digital signa1 processing @SP) hardware and techniques have enabled

modems to squeeze more information into a narrower overall bandwidth. Using DSP

components in modem systems brings with it several advantages, particularly increased

flexibility and reduced overall circuit board component counts for ease of manufacture

and increased reliability. Very hi@ perfomance DSP processors are available on a

single VLSI chip and are easily configured via software programming to handle a wide

variety of modulation methods and signals. Multiple modulatioddemodulation functions

are often performed in real tirne on this single chip, including filtering, clock recovery

and bit synchronization. This allows complex modulation and coding methods to be

easily and reliably implemented, often resulting in highet throughput capacity and

reduced overall error rates.

1.2 Objective

The main objective of this îhesis was to develop a software demodulator capable of

demodulating a multiple carrier phase shift keyed signal, perfonning al1 signal

processing in real time while simultaneously being easily reconfigured for different

carrier fiequencies and keying speeds. The primary goal within this objective was the

ability to demodulate the CLOVER-II HF radio data protocol to M e r extend the

demodulation abilities of the generic demodulator platform at UNB.

Development work toward achieving this goal utilized and exploited the abilities and

functions of the existing laboratory equipment, including the Spectrum Signal Processing

Quad C40 DSP processor board, HAL Communications PCI-4000 CLOVER-II Radio

Data Modem, and various pieces of test equipment including oscilloscopes, spectrum

analyzers, and plotters. Testing of the performance of the demodulator employed test

signals generated within the lab using fùnction generators and the CLOVER-II modem.

The remaining chapters of this thesis are outlined briefly as follows.

Chapter Two discusses the underlying causes of the desire for increased bandwidth

efficiency and some of the approaches and technologies under development to provide

solutions to the bandwidth problem. The development system is also descrïbed in detail

in this chapter.

Chapter Three reviews the theoretical background and analysis of phase shift keying

demodulation, and also investigates the design appmaches to digital filtering, which is of

particular importance to this project's realization.

Chapter Four discusses the software realization of the demodulator, providing detailed

discussions and explanations of each element of the demodulator solution.

Chapter Five presents the testing methods, procedures, and results obtained h m the

testing of the demodulator.

Chapter Six offers conclusions for the work and suggests possible fùture enhancements

and endeavours that could be pursued for further research.

References and Appendices are given to further support and expand upon the work

presented in this document.

Chapter II

DEMAND FOR BANDWIDTH - CAUSES AND SOLUTIONS

Applications with great bandwidth needs are continuously emerging in the modem world

as we move forward in the "iiifomation age" of a fûily intemetworked and connected

world. The development of highly competitive global markets and commerce continues

unabated, and is the mot cause of the desire for increased communications abilities

among the nations and regions of the world, stemrning h m the requirement for

increased speed and efficiency in modem business undertakings. In addition, public

interest in bandwidth-intensive applications continues to increase, fueled by the

widespread popularity of the Internet and acceptance of the personal computer as an

essential device in modem society. Indeed, as more bandwidth becomes available, more

applications emerge with even greater data rate requuements. This chapter will address

some of the current approaches under development to effectively "squeeze" more net

data throughput into limited channel bandwidths, both in the "wired world" of terrestrial

communications nebvorks and the burgeoning field of sophisticated wireless systems.

Additionally, the paramount role of digital signal processing in bandwidth-efficient

cornmunications systems is discussed. Particular reference to the development system

used in this thesis shall be given at the end of this chapter, providing an example of a

typical modem DSP system.

2.1 Increasing Demands for Bandwidth

A virtual revolution bas begun in the ways we wotk and coxnmunicate with one another.

The widespread use and availability of sophisticated and powemil personal coquters,

coupled with the explosive growth of the Intexnet, has led to an unprecedented demand

on the global telecommunications t structure. A network which was originally

designed to carry primarily analog voice t d f i c has had to adapt and evolve into a fùlly-

interconnected and user-transparent digital neîwork carrying al1 manner and fonns of

information (voice, video, imaging, software applications, etc.) as binary data.

Increasingly, society is becoming reliant on rapid and reliable access to information at

high rates of speed and "on demand" as the information is required.

The dernand for speed is quite apparent when a cornparison is Qawn between what was a

"state of the art" dial-up PSTN modem only a few years ago and the curent widely used

standard device. Only a few years ago, such a device would operate at 14.4kbps and cost

perhaps a few hundred dollars; the de facto minimum standard today is a 28.8kbps

device that is available in a package not much bigger than an audio cassette tape, has

sophisticated built-in error correction, data coxnpression, and even fax capabilities, and

sells for under $200. In fact, it is almost impossible to buy a "mere" 14.4kbps modem

today, the 28.8kbps device has all but relegated the slower modem to the history books.

By exploiting sophisticated data compression algorithms as modems have become

"smarter", the present-day standard issue modem has gone beyond the theoretical data

rate limit (in ternis of end-user net &ta throughput) imposed on analog signaling by the

limitations of a simple twisted-pair copper loop phone line [IA.

The "wired world" network topology discussed thus far has an "ultimate" solution for

maximum bandwidth - the widespread deployrnent of "fiber to the home", providing

every residence and building with an optical fiber network connection, allowing virtually

unlirnited bandwidth capacity, to the gigabit per second range and beyond. However,

fiber deployrnent on this kind of scale is costly and most service providers (i.e.,

telephone companies, cable companies, or other cornpetitive access providers) are

reluctant to invest the massive amounts of capital that would be required in such an

undertaking. Higher speed alternatives that yield more bandwidth from existing copper

and coaxial loops are under intense development and testing, perhaps most notably

asymmetrical digital subscnber line (ADSL) technology [54].

The situation in the wireless world is more complex. Uitimately there is the problem of

only having a finite "slice" or portion of the radio spectrum, which is becoming

increasingly crowded as new services emerge such as digital cellular telephone service,

wireless Internet comectivity, PCS, and LMCS. Spectrum availability is of even greater

concem in heavily or densely populated urban areas where many services are

concentrated. Of course, as the data rate (keying speed) of a radio channel increases, so

does the amount of spectnun (bandwidth) required to cany the signal using traditional

modulation methods (i.e., single carrier AM, FSK, PSK, QAM, etc.) [Ml.

Wireless channels are also subject to greater potential for signal degradation as well.

Bunt e m due to lightning, fading due to atmosphexic effects and weather conditions,

and multipath environments al1 present challenges to the transmission of clean high

speed data signals. Additionally, as keying speeds increase in attempts to yield higher

data rates, errors that do occur become more potaitially catastrophic in nature; a burst

error of a hunàred milliseconds due to a lightning surge or severe mulitpath fade might

obliterate several tens or hundreds of kilobytes of data on a high speed radio data link

unless special error control and recovery mechanisms are employed in the signaling

system, while on a slower link such a burst might destroy "only" a few huadred bytes

and be easily managed by a simple retransmission of the bad bytes by the transmitting

station. Obviously, if higher net throughputs are desired, it would be advantageous to

reduce the amount of redundant data that must be transmitted to protect data fiom errors,

so a robust, emr-resistant signaling method is required [IO].

2.2 Emerging Solutions to Bandwidth Constraint Limitations

While there are differences between wired and wireless communication links, it is

important to remember that many techniques and approaches aimed at increasing

bandwidth efficiency can be applied to either system with often similar results.

Techniques such as multiple carrier modulation and data compression are ofien equally

beneficial in either kind of system [3].

Traditional voiceband telephone modems have corne a long way both in terms of

performance and sophistication. Modems used on the PSTN have gone h m fairly bulky

and expensive low speed devices (in the 3ûûbps range) to very small, multifeatured

affordabie devices operating at speeds of up to 33.6kbps over standard phone lines and

supporting multiple data compression and error checking~correction features, and even

facsimile transmission modes. Sophisticated modulation and data compression methods

such as quadrature amplitude modulation (QAM) and MNPS compression have pushed

modem throughput speeds to higher and higher levels. Many of these features have been

made realizable through the use of sophisticated DSP power built in to these modem

modems. Much of the signal processing features are now accomplished under software

control, versus more complex discrete component hardware implementations that are

inherently less flexible or adaptable to varied signal formats 11 71.

Where it was once thought that 28.8kbps or 33.6kbps modems represented the maximum

data rate possible over standard telephone loops, progress continues in stretching

performance limits even hirther. US Robotics, a prominent manufacturer of modems and

cther computer peripherals, recently announced its plans to ship a 56kbps dial-up modem

in early 1997. By taking advantage of the evolving high speed backbone architecture of

the PSTN (where most central offices are now interconnected on fùlly digital high speed

tanks) and the power of dedicated DSP chipsets, the Company has managed to

effectively double the available bandwidth in a traditional dial-up line. Perhaps more

significantly, this has been accomplished without resorting to elaborate data compression

algorithms; US Robotics claims full compatibility with most widely used compression

schemes for the "x2" modem, indicathg the potential for even greater net throughput in

Iùtiire releases 1531.

Much effort is also underway in the development of asymmetrical digital s u b s c r i ~ line

(ADSL) technology. ADSL aims to provide very high bit rates (up to perhaps 10Mbps)

to residential customers over standard phone lines. While the actual modulation

techniques employed in ADSL are not yet finalized into an industry standard, most

versions under development use some form of multiple carrier modulation [54].

Multiple carrier modulation is a technique whereby a data Stream is modulated onto

multiple lower-speed carrien to produce a "data transmission in parallel" resultant

signal. Each carrier may be modulated in any manner desired, so that one may be FSK

modulated while the other carriers are PSK, QAM, or combinations of modulation

approaches. By breaking the signal d o m into low speed "subcaniers" the spectral

bandwidth of the resulting signal can be constrained, and ofien the lower keying speeds

provide added resistance to transmission impairments such as multipath fading or phase

dispersion [6,10,23].

Data compression algorithms have become an increasingly popular way to "streamline"

more net &ta throughput into a nmowband chanael. Many coding and compression

techniques exist; it would be beyond the scope of this thesis to attempt to investigate and

explore al1 of the workings and nuances of these techniques. It is instead more

appropriate to mention the underlying pnnciples that allow &ta compression to be an

effective means of increasing throughput rates.

Most compression schemes rely on some form of repetitive or interpretive pattern within

a data Stream. By eliminating a longer repetitive pattern of bits and replacing it with a

simpler, shorter pattern (which the receiver recognizes), fewer bits are transmitted while

the net bit throughput remains the same. Very sophisticated algorithms exist which can

interpret patterns and isolate "meaningfiil" information (dependent on the message that

the data itself represents) in uncompressed data (e.g., MPEG, JPEG compression

schemes). These approaches are capable of varying degrees of compression depending

upon whether lossy or lossless compression is employed. Suffice it to say that data

compression is a very powerfiil throughput enhancing tool in a digital communications

system 1171.

2.3 DSP Systems

It is apparent that today's modems can be veq sophisticated devices indeed, employing

many techniques for data compression, modulation, and error control. Such tasks are

usually easier to accomplish in software since parameters can be quickly and easily

adapted or changed to meet transmission channel characteristics and throughput

requirements.

The modem dedicated DSP chip is a very powerfùl device, well-suited to the nurnerically

and computationally intense demands of sophisticated modem signalling standards, since

in essence a DSP processor can be thought of as a fast dedicated math copmcessor. DSP

computational power has also been advancing steadily over the years to the point where

very fast DSP's are affordable, reliable, and readily available. A typical high

performance floating point DSP chipset today can operate at more than 275 million

operations per second (MOPS), and usually supports many extemal peripheral devices

and systems such as extemal memory, ,gh speed communications ports, extemal

interrupts and clock control features, etc. [SOI. Often such systems are incorporated on a

single board which is easily installed in a mical PC system. With interconnection to an

ADC device such a system becomes a very powerfùl signal processing platform, easily

capable of performing many of the sophisticated functions typical of an advanced

modem system. A user can easily reconfigure the system as desired by writing

appropriate sofhvare instruction code to accomplish the desired hinctions on the system

[43l

2.4 Previous Work at UNB

Development of a DSP-based demodulator platfonn has been underway at UNI3 for

several years. Andrew Hillier developed a basic PSK demodulation algorithm for use on

carrier fiequencies below 5lrHz [22]. Dr. Tervo (the project supervisor) extended this

work tùrther to encompass FSK signals. More recently Ke Zhou implemented a genenc

BFSK demodulator capapble of demodulating any typical BFSK signal without any pnor

knowledge of the signalling format beyond the basic "BFSK nature" wherein two

different clusters of fkequencies represent the binary signalling elements 1561. Saul

Mwakatapanya implemented a generic PSK dernodulator capable of demodulating single

carrier n-PSK signals, including 16-QAM [32 1. Rogerio Emiquez developed a Costas

Tan Lock Loop with adaptive filtering specifically aimed at detecting and tracking

Doppler shifted signals [7].

All of the previous endeavours at UNB were implementedsndhe "old" Texas

instruments TMS320C30 DSP platfom on a VME bus backplane. Dr. Tervo adapted

most of the original modem applications to run on the new TMS320C40 PC-based DSP

system currently in use. Various other students have contributed to the development of

other features of the demodulator system including Paul Beer (iho developed a menu-

based modem manager facility for the CJONME based system) and Eric Newcomb (who

developed a test bed facility for genenc modem development in the lab [33]); most of

these features have been adapted for use on the new C40/PC-based system.

2.5 The Developrnent System

The current generic modem development system at UNB consists of a dedicated DSP

penpheral board installed in a 486-based PC "host platfom". A dedicated "daughter

module" provides the VO intefiace for the DSP system. Code is written on the host PC,

compiled and linked using resident TI-authored software, and downloaded onto the DSP

chips on the penpheral board. A suitable calling program is written to execute on the PC

which loads the appropriate code to the DSP's and commands them to begin code

execution [42,43].

The DSP peripheral board i?self is a Spectrum Signal Processing Quad C40 Processor

Board. As its name suggests, this board is equipped with four Texas Instruments

TMS320C40 DSP processors. The TMS320C40 is a floating point l lSP running on a

40Mhz clock, and has a peak arithrnetic performance of 275 million operations per

second (MOPS). Additionally, the C40 DSP incorporates many features airned at

enhancing its parallel processing abilities in a multi-processor configuration, including

six high speed (20Mbyte/sec) communications ports for inteiprocessor com~unications.

The C40 device also incorporates a d k c t memory access @MA) coprocessor (which

relieves the DSP CPU of VO fiinction control, thus maximizing sustained CPU :

performance), support for linear, circular and bit-reversed addressing, many single cycle

functions (requiring only one instruction cycle of the DSP CPU to execute, including

branches, calls, and shift operations), high speed onthip memory, and separate intemal

program, data and D M . buses [50].

On the Quad C40 Processor Board, the four DSP's are interconnected in a ring topology

using the on-chip high speed communications ports. Each DSP is separately addressable

for independent code allocation and processing functions via a link interface adapter

(LIA) interconnect to the host PC. The processor board itself is interconnected for I/0

functions to the "outside worlâ" via an analog daughter module (descnbed in m e r

detail below) using the Loughborough Sound Images (LSI) DSPLINK;! intedacing

standard. This interface provides a high speed bidirectional bus pemiitting I/O directly

to/f?om the Quad C40 DSP board without passing across the host PC bus. Each C40 DSP

resides in a module site node (either "A", 'B", "C", or "D" - refer to Figure 2-1) on the

Quad C40 board; however, under the current implementation of this board at UNB, only

the processor resident in Module Site "A" actually "sees" the interface to the ADM for

VO fùnctions [42,43].

The Spectrum Signal Processing Burr-Brown Andog Daughter Module is a

dedicated UO board for the Quad C M Processor Board. The ADM supports fiil1 16 bit

dual channel conversion at sarnpling rates up to 500kHz for output signal conversion,

and allows input signal sampling at rates to 200kHz. Both input and output channels use

low pass filters to limit the affects of noise and aliasing; on the output channels the

filtenng also serves to "smooth" the normally "stepped" D/A converter output. These

built in filters are easily modified with resistor packs to obtain diEerent cutoff

fiequencies [42].

to ADM...

1 PC Interface 1

- DO D3 CO C3- BO B3. A0 A3.

Figure 2-1: Spectrum Signal Processing Quad C40 Board Schematic

%ode "Da'

D4 I Linîi

1 II terîiice Adat~ter

A

Sade "C"

C4

Xode "Bq'

B1

Node %"

Al

Chapter XII

THEORETICAL BACKGROUND - MODULATION AND DEMODULATION

The previous chapter highlighted the need for higher speed, more spectrally efficient

modulation methods for digital signals and also discussed some curent efforts undeway

in the development of such systerns. This chapter focuses on the theoretical and

mathematical analysis of a phase shift keyed demodulator, a discussion of digital

filtering as it applies to the work presented in this thesis, and an overview of a

commercial approach to multiple carrier PSK modulation (the HAL Communications

Inc. "CLOVER-II" protocol).

3.1 PSK Modulation and Demodulation - An Ovedew

The ultimate goal of any communications system is to convey information with mcuracy

and speed, whether across a terrestrial based land-line network of fiber optic cabling or

copper wires, or through wireless propagation between antema sites. As more and more

applications emerge that are "bandwidth intensive" (meaning that they require high bit

rates to execute properly), systems that cm coax more data throughput into narrow

frequency bands become increasingly important so that more services and applications

can simultaneously share the same transmission "pipe" of lirnited bandwidth.

Bandwidth efficiency is defined as the ratio of data rate to channel bandwidth, expressed

in bits per Hz [l 51. Phase shift keying modulation has traàitionally been the modulation

format of choice in spectrally efficient applications. Generaliy speaking, as a modem

device operates at higher and higher bit rates, the spectrum bandwidth it requires also

increases. Combinations of phase keying and amplitude keying (such as QAM) manage

to squeeze more data (i.e., higher throughput rates) into bandlimited channels, with the

risk of increased sensitivity to noise and other channel impairments. For these reason

some form of coding is usually employed (such as Trellis coding or v.42bis) [17].

Traditional PSK systems rely on varying the phase of a continuous carrier tone to

represent the message data. This usually results in a wide signal bandwidth at higher

speeds; an interesting alternative is PSK applied to an on-off carrier pulse, where the

phase of the camer is changed during the "off' intervals. Again, combinations of

modulation methods may be used with an on-off camier arrangement, and multiple low

speed camen can be grouped together to yield a higher net throughput rate [IO, 1 11.

3.2 PSK Modulation and Demodulation - Theoretical Background

A general expression for a PSK modulated signal of order N is given by:

where E , is the transrnitted signal energy per syrnbol (which in the case of combined

amplitude/phase keying, such as QAM, can assume varying discrete values according to

the number of amplitude signalling levels employed), T is the duration of the signalling

interval, and/, is the carrier fkquency, chosen so that/, = njT where n, is a fixed

integer.

Equation (3.1) represents the transmitted signal at the output of the transmitting device

(i.e., before it has propagated over any channel). The signal present at the input of the

receiver is given by

where n(t) represents the noise component introduced by the transmission properties of

the channel. n(t) is generally assumed to be a zero mean, white Gaussian signal.

In a multiple camer scenario, there are M discrete camier frrguenciesf, ; it follows thcn

that r,& assumes a set of M discrete values according to the number of camers

used.

A general fùnctional form of an N-PSK coherent receiver is given by a phase

discriminator whose output is directly proportional to the phase of the received carrier

signal. The presence of noise in the received signal causes deviations fiom the expected

phase, which in tum c m cause the phase discriminator to give an incorrect decision

output when the noise induced phase perturbation exceeds m. Thus, it is seen that

higher order systems are more susceptible to errors resulting h m the presence of noise,

and typically would require a "clean" signal, and a receiving device with a very precise

and stable local phase reference.

A PSK dernodulator mixes the incoming modulated signal with reference sine and cosine

waveforms whose fiequency is set ta match the frequency of the carrier as closely as

possible. Typically, PSK demodulation is p e b e d by a phase lock loop (PLI,). In a

coherent demodulator the receiver is both time synchronized (meanhg that the receiver

knows the instants in time when the modulation of the transmitted signal changes state)

and phase synchronized or locked (meanhg that the receiver follows or tracks the phase

of the transmitted signal),via some form of a PLL, to the receiver.

In a non-coherent system, on the other hand, no such phase tracking is employed. DSPK

(differential phase shifl keying) is a non-coherent form of PSK, DPSK operates by

transmitting a signal wavefom with a 180" advanced phase to represent a binary "O",

while leaving the transmitted phase unchanged to represent a binary " 1". The receiver is

able to store the phase of the received signal for two successive bit intervals, and by

determining the difference between the phase values the bit information of the message

can be extracted [l 51.

Following the mixing process in a coherent PSK PLL demodulator, the mixer outputs are

low p a s filtered (integrated over S samples, where S is the number of samples per period

T, as given in Equation 3.2), yielding in-phase and quadrature signal components which

may then be used to calculate the phase and amplitude of the received signal.

Differences between the calculated phase and the expected reference phase are used to

adjust the loop to properly "track" the incoming received signal. Refer to Figure 3-1 for

a simplified diagram of this process.

t ' pmdt ) b Low Pass FSer

r',wmudt)

a

Figure 3-1: Coherent PSK Demodulator Phase Lock Loop

From Figure 3- 1, if the in-phase mixed received signal r,,,.,,-(t) is given by:

(3.3) rh-ph ( t ) = 2 - A, (t)g[cos(o,t + 0, ( t)) + n(t)] coso,t

where 2A[ijK is the amplitude terni,

€),O is the phase term containing the baseband data,

and n(t) is the noise process induced by the transmission channel,

then rhqk can be expressed as:

(3.4) ph-, ( t ) = A, ( t ) ~ [cos(2o , t +9, (1)) + cosû, ( t ) ] + K& n(t) coso, t

M e r passing through the low pass filter (integrator) the noise and high Çequecy ternis

are removed, yielding:

which is the phase tenn containing the baseband signal multiplied by a gain constant

A&-

While Equation (3.5) would appear to give an expression Çom which the baseband signal

is easily extracted, the issue of synchronization remains to be addressed.

Synchronization is of paramount importance in the field of digital communications.

Receiving and transmitting devices must negotiate or adhere to an acceptable and

compatible protocol to provide for proper exchange of information; the number. of bits

representing a data word, the number of words within a frame, packet, or cell, and

h i n g rnethods must al1 be properly established. At a lower "signalling level", carrier

and bit synchronization are of primary importance in the proper demodulation of a

received signal.

As mentioned previously, the coherent PSK demodulator must maintain a lock or

synchronism with the received carrier wave. This carrier synchronization task c m be

performed by the modified PLL s h o w in Figure (3-2).

b Wched Fiber it)

-e EIToc +halmaa~:~+ LowEbssF5CT 4

-*CO: Phase Discrkninator > (maaging)

Figure 3-2: Modified PLL for Carrier Synchronization

A matched filter is defined by Haykin as follows: "A filter whose impulse response is a

time-reversed and delayed version of some signal 4j(t) is said to be matched to k(t)."

(pg. 53). Haykin also states that a physically realizable matched filter must have a zero

impulse response for any time t O. One property of such a filter as employed in the

PLL of Figure (3-2) is that the maximum signal to noise ratio of the filter output is

produced at t = T, where T is the length of the symbol period [15].

Referring to Figure (3-2), the output q(t) of the in-phase matched filter is given by

Removal of the noise component yields:

(3.7) xi ( t ) = A, K cosû, ( t )

which is similar to Equation (3.5).

Likewise, the quadrature section of the loop yields:

(3.8) x, ( t ) = A, K sine, ( f )

A simple arctangent calculation of these expressions produces the received signal phase

0,-

The received signal phase produces a phase e m r term O,, when compared with the

expected phase 0, of the signal. The error term is then used to adjust the phase of the

reference signal, via the numerically controlled oscillator NO), to match the reference

phase to the received signal. By averaging the error term over consecutive instances,

sudden phase changes resulting h m noise can be reduced. Since the demodulator

"knows" al1 phase values possible for the incoming signal, a cornparison is made

between the calculated phase 0, and the stored reference phase value which most closely

matches it, so as to produce the minimum phase e m r 8,,. The reference value is

assumed to represent the current phase of the transmitted signal. At this point the loop is

"locked" to the incoming signal and proceeds to track or follow the signal until a phase

change is detected, at which point the process repeats.

When devising a bandwidth efficient digital communications system, it is obvious that

one should endeavour to ensure that most of the transmitted bits represent "real" message

information, with a minimum of overhead so that one would strive to utilize as much of

the channel bandwidth as possible for message-bearing data transmission. It is therefore

desirable that the receiver in such a system be able to extract or recover timing

information kom the message Stream itself, rather than rely on a separate clock channel.

Additionally, a separate clock channel would have to be recombined at the receiving end

with the incoming message signal, adding complexity to the system.

An alternate method is called data derived syrnboVbit synchronizattion. The receiver is

given prior knowledge of the expected syrnbol rate (keying speed) and generates a local

clock signal running at the same rate. When a phase (symbol) change is detected, the

timing of the local clock is adjusted to match t5e symbol transitions. This is usually

perfomed over a specified interval containhg a fixed nurnber of symbols, and an

assumption is made that the difference over this interval between the local clock rate and

the incoming symbol rate is some unknown but constant value. The entire process also

assumes that the incoming symbol rate is known and constant.

3.3 Digital Fitering OveMew

Filters can be an important component in a communications system. Often they are used

to limit the spectral bandwidth of the signal source to suit the characteristics of the

transmission channel or of the modulation rnethod. in digital systems, fi1tering.i~

performed on the source signal to strip off high frequency components that may cause

aliasing following the analog to digital conversion process; fiequencies higher than one

half the sarnpling rate (the Nyquist fiequency) are removed by a low pass filter to

safeguard against high fiequency aliasing effects. Filtering can also be used to reduce or

accentuate a fiequency band (or bands) of interest, as is often perfomed in the

suppression of noise or echo effects at the receiver 11,301.

The design and irnplementation of analog filters h m discrete circuit components can be

a complicated and costly effort, not to mention the drawbacks h m a noise, reliability,

and flexibility standpoint of adding more analog stages to a system. Filter design

becomes particularly tncky in the case of sharp nmwband filters, which usually

produce a complex design with a complicated phase response characteristic.

Filtenng can be accomplished in the digital domain, which allows virtually any chosen

response to be realized. Of course, when such a filter is implemented as a software

routine running on a dedicated DSP device, it becomes fairly easy to teconfigure the

filter to obtain different responses, while an equivalent analog filter is effectively

"hardwired" to its original design response. Additionally, a software-based digital filter

maintains consistent performance in a variety of operating environments and is not

nearly as vulnerable to performance degradation over time as an analog multistage filter

(in the analog world, breakdown over tirne in the dielectric materials used in capacitors

often affects the filter response and performance) [46].

Digital filtenng is of particular interest to the work presented in this thesis. In a parallel

or multiple camer system, isolation of each carrier tone is desirable to allow

demodulation and recovery of the original message signal. In a spectrally efficient

modulation scheme, it is obvious that the carrier tones are likely going to be quite closely

spaced in fiequency in order to limit the overall spectnim requirements of the transmitted

signal; thus, narrow and sharp (Le., steep cutoff) filtering is required to achieve c h e r

isolation. Realizing such a filtering fùnction on a DSP architecture ensures easy

modification of the filter charactenstics (adding an element of flexibility to the system)

and precludes the requirement for any external filtering device (such as an analog filter

bank). The ability to implement a filter with a predictable and consistent phase response

is also a benefit to a digital filter design, particularly when, in a PSK system, the phase of

the filtered signal contains the information required to properly demodulate the message

fiom the camer tone.

Digital filtering is a very broad field, and it would be well beyond the scope of the work

presented here to attempt to cover al1 aspects of the topic in depth. Instead, discussion

shall be limited to the investigation of two filtering approaches attempted during the

course of the project.

Digital filtering systems are usually classified in ternis of their impulse response duration

as either infinite impulse response (IIR) or finite impulse response (FR). The F R (or

non-recursive) filter can exhibit extremely linear phase response, but requires a relatively

large number of filter coefficients (taps) to obtain a sharp cutoff charactenstic. In the

DSP world, a large number of taps equates to a lengthy computation process to realize

the filter. The W (or recursive) filter usually contains fewer taps for a sharp cutoff

characteristic, but realization of a linear phase characteristic makes the design

substantially more complicated and involved [30].

It is important to remember that the entire filtering process must be perfonned in an

interval less than the sampling period dwation to avoid "missed" or lost sarnples of the

input signal. This effectively places a limit on the maximum number of taps that can be

used, which corresponds to a maximum "sharpness" or cutoff slope that is realizable,

given the sampling rate and the computational speed of the DSP CPU.

FIR filtering was chosen for this project due to the existence of a well-designed F R

filtering package on the TMS320C30 DSP platfonn (originally written by Eric Newcomb

and Paul Beer [2]). The linear phase characteristics of this type of filter was also a

consideration due to the desire to maintain demodulator phase accuracy across a wide

range of possible carrier fiequencies.

Several design methods exist for F R filters, including the Fourier senes method,

windowing, and fiequency transformationltranslation methods. The windowing

technique is perhaps the most intuitive and straightforward, and is discussed in some

detail here.

The ideal fiequency response of a FIR filter is denoted by H,(o), with a corresponding

impulse response given by This impulse response is characterized by the

following expression:

T (3.10) h,m,,, (n) = - I~i(o )@"do [36]

2~ -,

This is simply an infinite Fourier series, where h,(n) are the Fourier coefficients.

To obtain a finite impulse response filter, the inîïnite Fourier series terms are simply

limited to some finite number. However, simple ûuncation of an infinite Fourier senes

produces the Gibbs phenomenon, whereby oscillations exist on either side of the

(intended) cutoff fiequency. Obviously, this is not acceptable if a smooth, sharply

defined filter output characteristic is desired [36].

A windowing function may be applied to the filter impulse response senes to lessen the

Gibbs phenomenon. Several window functions exist, ranghg from a simple rectangle

type (where the window function is sirnply equal to either "1" or "û" across the senes of

terms) to complex functions such as the Hanning window or Blackman window.

Generally speaking, the more complex the windowing function, the lower the "ripple"

in the filter stopband output characteristic (i.e., the smoother the overall response and

decreased "pass through" of unwanted signal energy in the stopband). Table 3- 1

highlights some of the properties of common window functions [30,35,46].

WINDOW TYPE

Rectangular

Hamming

Blackman

Table 3-1: Typical Window Function Properties

SIDELOBE RIPPLE

-13.3 dB

-42.7 dB

-58.1 dB

STOPBAND ATTENUATION

20.9 dB

1

54.5 dB

75.3 dB

The F R design package resident on the TMS320C30 platfom employs a Blackman

window tùnction for filter realization; as such, the package is merely a filter tap

(coefficient) calculator. The tap values it produces are then incorporated into an

algorithm that realizes a FIR structure. The following pseudo-code segment

implements a FIR filter:

N = filter order input-array (0) = new-samplejnput filtersum = 0.0 loop: for (j = N, 1, j--) do

filter-surn = filter-sum + tap0)*input-arrayu) input-array(j) = input-my(i- 1)

endloop filter-out = filter-sum + tap(O)*hput-array(0)

The actual C Ianguage source code is found in Appendix VI at the end of this

document. Unfortunately, a sharp, nmwband FIR filter requires a large number of

filter tap coefficients (high filter order), typically 100 or more, and the above

pseudocode did not execute quickly enough when written in C on the TMS320C40

platform when more than about 85 taps were used at a maximum sarnpling rate of

about 9 kHz (remembering that a lower sarnpling rate enables a greater number of

taps, since the DSP CPU has more time to perform the multiplications and additions

for each new sample when the interval between successive sarnples is increased).

When running this filtenng routine, the TMS320C40 DSP CPU was also unable to

perform any of the demodulation hinctions; since it was desired to be able to both

filter demodulate simultaneously on each DSP CPU in a multiple (parallelj

carrier scenario, an alternative method for filtering was required.

Concurrent with the work on this thesis, a similar project was underway by another

graduate student, Cindy Robichaud. Robichaud's work was aimed at the successfui

demodulation of a parallel FSK signal, and therefore involved similar filtering

objectives for carrier tone isolation. Through the course of this work a simpler and

faster approach to the filtering problem was devised.

If the ideal fiequency response of a simple "brickwall" low pass filter is given by the

illustration in Figure 3-3, it stands to reason that such a filter cm be rnixed or translated

out io 2 desired center fiequency (fd through a convolution operation to realize a

bandpass filter. By selecthg an appropriate value for and applying an appropriate

number of sinc function terms (taps) to obtain a desired "sbrpness" of fiiter response, a

convolution operation about a chosen center fiequency f,, yields a bandpass filter

centered at fo. The algorithm to accomplish this was written in assembly language and

took advantage of many of the perfoxmance enhancing and optimization features of the

TMS320C40 DSP platfonn to produce a fast routine capable of real t h e operation as

part of a parallel carrier demodulator system.

Figure 3-3: Ideal Low Pass Filterl Bandpass Filter Characteristic

3.4 A ParaIlel Carrier Protocol: CLOVERIII

CLOVER-II is a novel packet data protocol which has been specifically designed to be

highly effective for HF radio packet data transmission. The HF band (3 to 30 MHz) is a

particularly nasty environment in which to send data. Ionosphenc effects oflen Iead to

signal dispersion and phase "smeariag" of received signals. In essence, the ionosphere

produces a lot of multipath intenerence, whereby a single onginating signal anives at

the receiver via a number of different propagation paths; the receiving antema merely

sums al1 of the signals it gets and passes these on to the input stage of the receiver.

Indeed, along these multiple paths the transmitted signal is subjected to varying levels

of attenuation, added noise, and time delay factors due to the varying path lengths, so

the received signal is usually not a very accurate replica of the originating signal.

Figure 3-4 illustrates a typical multipath scenario.

Figure 34: Typical Multipath Scenario

The smearing problems presented by the mulitpath effects are very destructive to data

transmission. Tirne smearing of the transmitted data Stream causes the receiver to lose

track of the "space" and "mark" intervals in the signal itself, and the phase and

amplitude ambiguities introduced by the multipath can also cause emneous symbol

detennination [IO].

In order to combat these problems and still offer a relatively high data throughput

capability, the CLOVER group of waveform protocols were developed. It was desirable

to have the transmitterlreceiver adapt automatically to the the-varying conditions

present on a typical HF radio link and also to minimize the overall spectrum

requirement, since in the amateur radio world, bandwidth is a shared (and therefore

limited) resource, and the larger the bandwidth used by a transmitter, the greater the

overall average power needed to transmit the signal (amateur radio operators are

regulated by goveming bodies with respect to fiequencies and power output levels, and

of course a high-power transmitter system is inherently more costly than a

cornparatively lower-powered system). This basically led the way for the developers of

CLOVER to seek a DSP-based solution [20,23].

The underlying premise of CLOVER modulation is to use a slow base keying speed

(only 3 1.25 Baud) and rely on multi-level phase/amplitude changes to increase the

overall data throughput. Additionally, the use of very n m w (125 Hz bandwidth)

multiple carrier tones in a parallel configuration further enhances both the overall

throughput spectrum efficiency.

CLOVER-II does not stop there in attempts to M e r strengthen the transmit/receive

performance. Since normal phase shift keying of a carrier tone produces a

fairly wide spectrum (particularly at higher keying speeds), CLOVER-II instead uses an

"odoff' signalling arrangement, whereby each camer tone is transmitted with a

phase and amplitude for only a 16ms duration, with al1 state (i.e., phase and

amplitude) changes occming during the "off' interval. The four carrier tones are time

overlapped with 8 ms between the center of each pulse. Refer to Figure 3-5 for fiirther

clarification.

Figure 3-5: CLOVER-II Carrier Tone Sequence 1101

The end result is that the CLOVER-II protocol can produce a 750bps net throughput,

using 500Hz of bandwidth and a combination of 4 amplitude levels superimposed on

16-PSK [IO]. Using real-tirne analysis of traasmitted signal path conditions based on

received signal quality, the receiver is able to negotiate with the transmitting device to

"ramp up" or "gear down" to the f a s t d iable modulation speed continuously during

a one-to-one transmission (two stations conversing & with each other). The error

performance of the protocol is lùrther enhanced by the use of forward e m r correction

(FEC) employing Reed-Solomon variable block size coding for ermr recovery and

correction when operating in "broadcast" mode (one station to many, where the

trammitter selects a block size and modulation f o m t or speed to use exclusively for

the duration of the transmission). in a one-to-one or "ARQ (automatic repeat request)

mode, the two participating stations are continuously adapting the modulation and

Reed-Solomon coding "on the fly" to suit the varying conditions on the radio link..

M e r factoring in the variations in error control coding with the multiple modulation

formats (10 in all, fiom two channei diversity fkequency shift modulation to 16-PSK, 4

amplitude level modulation), the CLOVER-II protocol can support 160 differeut overall

wavefom modes [10,11].

Chapter IV

DEMODULATOR SOFTWARE

This chapter incorporates the demodulation and filtering approaches discussed in the

previous chapter into a parallel cairier PSK demodulator implernentation, operating in

real tirne on the Quad C40 Processor Board and host PC. A general o v e ~ e w of the

software implernentation mode1 is presented first, followed by an in-depth discussion of

each major code component. Complete source code exarnples are given in the

Appendices at the end of this document.

4.1 Overall Program Mode1

Demodulator code is written on the host PC (using any suitable text editor application),

and compiled, assembled and linked for conversion into executable COFF (common

object file format) files for download ont0 the individual DSP CPU's residing in the

four processor nodes on the Quad C40 board. The compiler, assembler, and linker

applications reside on the host PC in the fom of a shell program, with user-selectable

parameters for invoking various optimization features and option. Typically the

compiIer shell commands are invoked through the use of batch files (refer to the

exarnples given in Appendix II).

A "calling program", written in C, executes on the host PC, and sends the appmpriate

executable files to the DSP's. The calling program controls the operation of the DSP

CPU's, coordlliating start, stop, and reset tirnes. The calling program can also accept

inputs fiom each DSP CPU, comunicated via the link interfàce adapter (LIA), for

fiirther processing of the demodulator outputs (for example, symbol displays, bitstream

output, and symboVmessage decoding). An example is given in Appendix m.

Referring to the functional block diagram in Figure 4-1, an input signal is fed in to the

ADC board, which is intercomected to the DSP residing in "Node A" (CPU-A). This

DSP passes the input samples on to "Node B , 'Wode B" passes them on to Wode C",

etc. In this manner al1 four DSP's "seey' the input samples as they arrive. Each DSP

then perfonns a narrowband filtering operation centered at the carrier Erequency of

interest to isolate each carrier tone of the four carrier composite parallel input signal. A

phase lock loop runs on each node, locked to the center fkequency of the carrier for that

particular node. Demodulated symbols fiom the PLL are then sent to the host PC via

the LIA. The host can then display these symbols on the screen, Save them to a file, or

perfonn fùrther manipulations in efforts to recover the original message.

Figure 4-1: Demodulator Implementation Block Diagam

Each DSP is given pnor knowledge of the expected canier fiequency, frequency

separation (spacing) between camer tones, the expected modulation order (i.e., number

of phase states), and the expected keying speed (baud rate). By passing appropriate

parameters to the DSP's via the host calling program, the DSP's are easily configured

for different camer fiequencies, baud rates, and modulation orders. An element of

flexibility is ensured through the relative "independence" of the demodulation process

running on each node; in essence, each DSP is its own demodulator, with the output

symbols fiom al1 four CPU's repackaged on the host PC. Complete demodulation

source code examples are given in Appendix 1.

The calling program running on the host accepts user inputs for setting the signal

(demodulator) parameters. These parameters are then fed to the appropriate DSP nodes

along with the actual executable files for the demodulator ninning on each node. As the

DSP's perform the filtering and demodulation, the output syrnbols are fed back to the

host over the LIA. This is the point in the process wbere M e r ancillary processing

may be perfomed to decode the original message data, perforrn m r correction and

recovery, etc. A user-inputteci control sequence or character (such as the "ESC' key

typed in h m the keyboard) causes the calling program to halt the DSP's and the calling

program (symbol display loop) itself.

4.2 Demodulator Code Components

Whiie the demodulator itself may be considered to be a parallel assembly of

independent demodulators, each m i n g on a specific DSP node, the hardware

configuration of the Quad C40 Processor board requires one DSP (the CPU residing in

"Node A") to act as the I f 0 interface to the analogkiigital conversion board. As such,

the code written for this particular processor contains an interrupt procedure to handle

signal VO functions. Refer to Appendix 1, "Demodulator Code For CPU-A".

4.2.1 Interrupt Service Routine

The interrupt service routine (ISR) ninning on "Node A" detects the presence of an

interrupt fiom the Analog Daughter Module. This interxupt signals the arriva1 of a new

input signal sample. The ISR reads in the new signal sample and r e m s this value to

the main program; the main program then passes the new sample on to the DSP in

"Node B" using one of the high speed interpmcessor communications ports provided on

the TMS320C40 architecture. An important consideration here is the sampling rate

established in the main demodulation program; the analog daughter module board must

not produce a new sample (i.e., the sampling rate must be sufficiently low) befpre the

main demodulation program has had time to perform one demodulation "loop", h m

filtenng of the input sample through demodulation and symbol output. If interrupts

(new samples) occur faster than the demodulation loop can process them, the

demodulation algorithm will not fiinction comctly.

4.2.2 Input Signal Filtering

The input signal is narrowband filtered to isolate the specific carrier tone to be

demodulated on each DSP node. The CONVOLVE assembly language routine (given

in Appendix IV) plays a fundamental role in the filtering process. The nurnber of taps

for the filter is set as a program parameter (remembering h m the discussion of digital

filtering in the previous chapter that a greater number of taps produces a "sharpei' filter

response, and also increases the processing tirne required to execute the filtering

algorithm); using this constant (TAPS), the desired width of the narrowband filter

(WIDTH), the sarnpling rate (Fs), and the selected center fiequency (Fc, which

represents the carrier frequency to be demodulated), a filter tap array is calculated (pnor

to the amval of any VO processing intenupts/ISR actions) based on the sine and cosine

components required to "mix" the filter response out to the center (carrier) fiequency Fc

(refer to the discussion of this filtering technique in Chapter 3). This filter tap array is

then used as a "look-up table" in the CONVOLVE routine.

The CONVOLVE routine uses a circular addressed buffer to loop through the tap values

in a present-past input array multiplication. The array of signal input values is k t

initialized to zero, and as a new sample arrives it is inserted into the fmt (top) array

element position, and dl previous samples are shüted down one position. The input

signal array is then convolved with the filter tap anay, and the result of the convolution

operation (the filter output) is retumed.

4.2.3 Data Exchange from Node to Node

It is possible to configure each DSP node to accept inputs h m the LIA; demodulation

parameters may be passed directly to each node in this manner. An alternative approach

is io pass parameters to the "Node A" DSP CPU, and then have these parameters pass

over the high speed interprocessor communicatioos ports to the other DSP nodes, or, the

parameters may be b'preset" in the code written for a specific DSP node. In any case,

the nodes are easily initialized and configured to allow flexibility and independence in

their demodulation fùnctionality; in this manner the demodulator system retains the

ability to demodulate independently modulated carrier tones in a multiple (up to a total

of four) carrier tone signal (provided that PSK is the modulation method employed).

The camer fkequencies, keying speeds, and modulation orders can al1 be different across

the parallel carrier tones.

4.2.4 The Demodulation Loop

The demodulation loop is a phase locked loop algorithm implemented in C. As

mentioned previously, the demodulation loop process is an infinite loop which is

intempted by the arriva1 of a new input signal sample passed into the main program by

the ISR. n i e demodulation loop "waits" for the anival of a new input sample, which is

then filtered, and rnixed with the locally generated sine and cosine wavefoms, stored as

"look-up" tables.

The mked in-phase and quadrature components are integrated in a circular buffer (a

moving average filter). A new mixed sample is inserted at the "head" or start of the

buffer, added to the cumulative sum, and the sample at the '?ail'' or end of the buffer is

deleted fiom the sum. This process is perfomed for both the sine and cosine mixed

samples, over an integral (buffer) length (INTLEN) set equal to the sampling rate

divided by the center fiequency (INTLEN=SAMPLE/CENTER). nie results of the

integration appear as alternating sine and cosine rnixed values, stored as

SIN-NIEGRAL and COS-INTEGRAL. These values are used in a direct arctangent

calculation using the built-in library function a-, to yield the received signal phase,

which is then low-pass filtered (averaged) over four consecutive instances to reduce

noise effects. The averaged phase is then compared to the reference phase most closely

matching if and based on the division of the received signal phase space into an

appropriate number of sectors corresponding to the modulation order used. The

reference phase for any particular symbol assigmnent is assurneci to lie in the center of

the appropriate phaseangle sector. Figure 4-2 illustrates the phase angle (reference

phase) sector assignments.

Figure 4-2: SymboVPhase Assignment

4.2.5 Automatic Gain Control

The relative energy of the rnixed sine and cosine components varies in relation the

received amplitude of the input signal. An automatic gain control (AGC) adjustment is

performed to keep the mixed signal energy values within a preset "optimum" range of

values. The magnitudes of the cosine and sine integrals are squared and summed to

yield a net cumulative magnitude. This value is then compared to the predefined

optimum range to produce an AGC scaling factor for use on the next incoming sample.

The task of symboÿbit synchronization is performed within the demodulator by

establishing an interna1 clock signal (Le., a square wave) on each n d e that runs at twice

the baud rate of the incoming signal. The peiod of this clock is adjusted each thne a

symbol change is detected to cause the clock period to converge on the incoming

symbol rate. Detection of symbol transitions usuaily occurs at the midpoint of the

symbol interval; edge detection (leading/nsing or trailing/falling) is used to trigger

srnaIl step adjustments (BITITSYNCCCORRECTION) to the intemal bit clock according

to the previous clock value, synchronizing it with the incoming symbol stream.

4.2.7 Carrier Lock Adjustments

A small deviation in received carrier fiequency is allowed in the PLL. An important

consideration to keep in mind here is that when using a very narrowband filter, the

frequency deviation can result in improper filtering action since the center frequency of

the filter remains constant (set to the carrier fiequency). The narrower the filter, the

greater the potential for errors sternming h m fiequency deviations in the received

carrier.

Frequency lock correction is performed by adjusting the size of the steps through the

sinekosine "look-up tables" prior to mixing the new (latest) input sample. A fiequency

correction factor is appiied to the step size parameter to adjust and converge the PLL on

the fiequency of the received carrier signal.

4.2.8 Symbol Output

The demodulated symbols are passed directly back to the host PC via the LIA. The

calling program performs an infinite loop, checking the LIA addresses comsponding to

each DSP node for the anival of symbols. These symbols are then outputted to the PC

display in sequence as they arrive h m the DSP's (i.e., the symbol h m the DSP in

"ode A" - CPU-A - is displayed first in each group of four syrnbols on the screen); a

user-entered control character or sequence (e.g., the "ESC" key) teminates the calling

program and halts the DSP's.

Testing procedures and results for the demodulator are presented in the next chapter.

Cbapter V

DEMODULATION TESTING AM) RESULTS

This chapter discusses the tests conducted on the demodulator implemented on the Quad

C40 DSP board. Descriptions of the methodologies and equipment employed in the

testing pmcedures are also provided.

Three testing methods were used in the evaluation of the demodulation system. The

HP-8904A Multifunction Synthesizer was used to generate PSK signals at various

frequencies to confimi the operation of the individual demodulation processes on each

DSP node; the CLOVER-II board was used to produce two diagnostic test signals, and

then to test the operation of the demodulator on a "real wodd" received signal fiom

CLOVER-II transmissions on HF radio.

5.1 Synthesuer Generated Test Signals

The HP8904-A Multifiuiction Synthesizer feahues 16 RAM registea which can be

individually programmed with desired signal characteristics (i.e., fiequency, phase, and

amplitude) and then "hopped" through various state combinations to effect a modulation

wavefom on the primary output carrier wavefom. By establishing parameters for

phase (and amplitude/fkequency) in the synthesizer's hop RAM addresses and then

inputting a Cbit control sequence via the parallel port on the synthesizer, the resulting

wavefom can be "hopped" through any of the desired phase angles with keying speeds

ranging fiom 1 to 1200 Baud. ine interface to the parallel port is supported by a simple

single-chip control box that allows the user to select which hop RAM states are

"activated" , the rate at which they are "hopped" (the keying speed, triggered

automatically by an intemal clock signal or rnaflually by pushing a manual clock trigger

button), and the order in which the hop sequence is perfonned (i.e., either in a random

order or in numencally increasing sequence).

Additionally, the HP-8904A allows simultaneous output of four individual component

carrier signals over a single output channel. In combination with the "hop" capability,

the fùnction generator can produce a four c h e r test signal with one camer "hop

modulated" with vanous PSK modulation parneters (i.e., order and keying speed).

The first test involved a continuous, unmodulated single tone fiequency outputted h m

the HP-8904A. The demodulator was configured in software to run independent phase

lock loops on each DSP node centered at the single common carrier fiequency. The

phase of the carrier was then varied, both by hand (yielding a very slow effective baud

rate, merely equal to the speed of the hand operating the phase adjustment control on the

function generator) and by using the "hop" registers and control box to produce PSK

modulation on the camer. This test was perfomed over a range of PSK orders, h m 2

to 8-PSK, and at a range of baud rates (both "real" h m the timing of the hop register

control box and "simulated" via user activation of phase state changes on the HP-

8904A). Screen captures of the demodulated symbol outputs are provided in Figures 5-

1 through 5-6 for this testing procedure. Output on the screen shows a repeating pattern

of symbol letters "A" through "H", depending on the modulation order selected. Table

5-1 provides a summary of results.

RATE

(manual keying)

2-PSK

QPSK

8-PSK

4800

4800

2400

Table 5-1: Maximum Baud Rates - Multiprocessor Single Tone Demoduiation

MAX BAUD

RATE/ 125Hz

FILT. WIDTH

(hop ram)

300

300

50

The demodulator output when subjected to this test procedure produces, as expected, a

repeating sequence of syrnbols; since each DSP node is demodulating the same input

signal (i.e., a single fkequency carrier that is PSK modulated) this result indicates that al1

four DSP nodes are independently locking on to the incoming signal and demodulating

it correctly. Keying speeds up to 1200 Baud were realized with 2-PSK; QPSK

supported 1200 Baud, and 8-PSK signals yielded maximum 600 Baud penormance

(after widening the demodulator input filter bandwidth) . The upper limit on the keying

speed is constrained by the performance of the DSP nodes (since each node is still

MAX BAUD PSK ORDER

RATE1 REQ

FILT. WIDTH

(hop ram)

1200/ 3000Hz

1200/ 300OHz

600/ 3000Hz

MAX BAUD

pedonning real-time filtering and interprocessor communication of both input signals

and output symbols) and the width of the filter employed for camer tone isolation (as

keying speeds and modulation orden increase, so does the overall bandwidth of the

modulated camer tone). The buffer integration length in the PLL was adjusted to yield

optimum performance at the vanous baud rates and modulation orders; al1 other

parameters (i.e., sarnpling rate and number of filter taps) remained fixed during this test.

Figure 5-1: Single Tone Multiproccssor Demodulation 2PSK 300 Baud

Figure 5.2: Single Tone Multiprocesmr Demodulation

- 3000Hz Filter, 2PSK 1200 Baud -

Figure 5-3: Single Tone Multiprocessor Demodulation - QPSK 300 Baud

Figure 5-4: Single Tone Multîprocessor Demodulation

- 3000Hz Filter, QPSK 1200 Baud -

Figure 5-5: Single Tooe Multiprocessor Demodulation - 8PSK 50 Baud

Figure 5-6: Single Tone Multiprocessor Demodulation

- 3000Hz Filter, 8PSK 600 Baud -

Confïguring k e e channels on the HP-89û4A to produce independent output carrier

tones (of fixed phase and amplitude) wbile simultaneously outputthg a PSK modulated

carrier (using the "hop" RAM) provided a means of evaluating the relative degree of

"isolation" of the parallel carrier channels across the DSP nodes. During this test, each

DSP node was assigned a carrier/center fiequency corresponding to one of the four

output tones h m the HP-8904A. The carrier tones were initially chosen to match the

carrier frequencies of the CLOVER-II waveform as closely as possible as a precursor to

testing the demodulator with a "reai" CLOVER signal, and the input signal filtering

bandwidth on each channel was initially set to the CLOVER-II default width of 125Hz.

Of course, due to the flexible nature of the demodulator code, the choice of carrier tones

is quite arbitrary, within the consûaints of the Nyquist theorem (tbe maximum c h e r

fiequency cannot have a value greater than one-half the input signal sarnpling rate) and

allowing for camer "spread" as modulation orders and keying speeds increase (i.e., the

overall bandwidth of the modulated carrier must not overlap the center fiequencies of

the other three carrier tones; this "spread" effect may be controlled somewhat through

the use of special measures such as onoff signalling or namw output signal f i l t e ~ g at

the transrnitter).

Bandwidth spread effects limited the maximum keying speeds to about 50 Baud with

the "default" filter widths of 125Hz (an indicator of the level of spectmm control used

in the CLOVER hardware); widening the filter widths (and consequently moving the

unmodulated camer tones to fiequencies outside of the adjacent filter passbands)

allowed higher keying speeds to work properly. The maximum keying speed

performance results h m this test are summarized in Table 5-2, while screen captum of

the output symbol displays are given in Figures 5-7 to 5-9, once again showing a

repeating sequence of symbol output letters. Figure 5-8 shows the demodulation

occumng on Node C, illustrating the flexibility of the demodulation configurations.

PSK ORDER

2-PSK

Table 5-2: Maximum Baud Rates - Four Independent Carriers

Effective thmughputs here for a tme four camer modulated signal range h m 2400bps

for 2-PSK at 600 Baud to 3600bps for four carrier 8-PSK at 300 Baud.

MAXIMUM BAUD RATE /

REQUIRED FILTER BW

600 / ISOOHZ

QPSK 300 / 500Hz

Figure 5-7: Four Carrier Tone Demodulation - 1.SkBz Filter, 2PSK 600 Baud

(center freqs: 2062,2850,3000,3200Hk)

Figure 5-8: Four Carrier Tone Demodulation- 5 O O H z Fiiter, QPSK 300 Baud

(cen ter freqs: l83O9I985,l3 l3,26SO& - symbols from node "C")

Figure 5-9: Four Carrier Tone Demodulation - lm Filter, 8PSK 300 Baud

(center freqs: 2062$700,2900,3 100Az)

Noise performance was evaluated by selecting one channel on the HP-8904A to output

an 8 V peak to peak random white noise signal, while simultaneously outputting a PSK

"hop RAM" modulated carrier (demodulating on each DSP node simultaneously), and

selecting varied canier amplitudes while obseiviog the output symbol display for slips.

The effects were minimal for lower modulation orders (2-PSK) and became more

significant in the form of "missed" or "slipped" output symbols at higher orders. This is

expected since higher orders imply h e r differences in signal phases between symbol

states, and as these received signal phases become more varied due to the presence of

noise, erroneous phase detenninations become more probable. An example of the

"noisy" output symbols for an 8-PSK 300 Baud input signal is given in Figure 5-10; the

signal to noise ratio represented in this test is -20.6dB, given a camer amplitude of

750mV and noise amplitude of 8.0V.

Figure 5-10: Demodulation With Noise - 8PSK 300 Baud

5.2 CLOVER-II Generated Test Signnls

The CLOVER-II board supports some usefid testing modes. The board can be

instnicted to transmit a continuous phase "four tone test" which, in effect, is a

CLOVER-II modulated waveform carrying no data. The purpose of this mode is to

allow an HF radio operator to c o n f h and adjust transmit power levels, but it proved

quite usefùl to verify the fhctionality of the demodulation system. The four tone test

was fed into an audio cassette deck, recorded at an appropnate level, and then played

back as an input to the C40 DSP demodulator via the Analog Daughter Module ADC

board, with each DSP node centered on a different CLOVER tone center frequency

(2062,2187,23 13, and 2437Hz) at a 3 1.25 Baud rate.

While the CLOVER Reference Manual does not indicate what particular modulation

fonnat is ernployed during the "four tone test" operation, selecting BPSK seemed to

produce meaningful results. The output symbols were seen toggling across each DSP

node in a regular pattern; examination of the real-time bitstream produced h m the

demodulated syrnbols yielded a repeating pattern of bits, which in al1 likelihood

represent the "CLOVER Control BlocW encapsulated in the transmission. Since there

is no way of determining the coding used in the control sequence with respect to actual

control block "message content" (requests for this information ftom HAL

Communications Corp. were flatly denied by the Company president), the repetitive

nature of the bit patterns (10001 10001 and 1000 1 1 1001 l), the apparent timing

correlations with an observed "dip" or "glitch" in the audible level of the test signal

while Iistening to the signal, and the consistency of these characteristics during repeated

testing would seem to confhm correct operation of the demodulator on this particular

CLOVER signal. Refer to Figures 5-1 1 and 5-12 respectively for the symbol and

bitstrearn outputs h m this input test signal.

Figure 5-1 1: CLOVER Four Tone Test BPSK Symbols

Figure 5-12: CLOVER Four Tone Test BPSK Output Bitstream

Another mode that was used as a test is the "FEC" or '%roadcast" mode of the

CLOVER board. In this mode, the board takes a message (Le., a text message, data file,

etc.) and broadcasts it without any handshaking or protocol agreement with the

receiving stations. The user selects the modulation format to be used for the duration of

the transmission, fiom a simple diversity fiequency shifi keying scheme (where two of

the four carriers form a redundant fiequency shift pair) right up to a 16-PSK, 4

amplitude "QAM"-type modulation format.

At first glance this would seem like an ideal signal to veriQ the demodulator's

performance; however, the CLOVER-II board incorporates Reed-Solomon error

correction coding when operating in FEC mode [IO], and the parameters associated with

the requisite coding (i.e., coder efficiency, polynornial length, etc.) are "buried" in the

control blocks within the CLOVER-II protocol. Thus, the demodulator is, in effect,

seeing a "scrambled" wavefom and the output symbols and bitstreams obtained h m

this test did not seem to really reflect any recognizable pattern, consistent with the

"scrarnbled" nature of the Reed-Solomon error correction coding employed by the

protocol, and with the "on-off' nature of the carrier signalling in CLOVER-II (as the

individual carrier toncs are switched "on" and "off', the corresponding DSP nodes are

each attempting to acquire phase lock on a noise input, and thus when the carrier is

switched back "on", the demodulator will be conducting a phase cornparison with the

last random phase pulled h m the noise input). Decoding of the e m r correction

parameters was not possible due to the indecipherable nature of the specific format of

the control blocks within the transmitted signal; the manufacturer refused to provide any

information regarding a patented and propnetary waveform to any outside Party, other

than reiterating the information fond in the published literature on the CLOVER

protocol, narnely that the control blocks fonn an integrai part of the forward error

correction and codeword generation process.

5.3 Actual Received Radio Signnls

Using the CLOVER-II board, in conjunction with the iCOM G R 7 1A Communications

Receiver, a few signals were found matching the CLOVER-II protocol and recorded to

tape for fuhire use in testing. While it was interesthg to observe the fairly quick (for

HF packet radio at least) incoming datastreams from the radio equipment, the same

protocol related issues arose to limit the utility of such "real world" signals in the

evaluation of the demodulator. Since, duing a CLOVER-II ARQ ("station to station")

mode transmission, the modulation format and e m r correction coding are under

continuous evaluation by the two stations involved in the transmission, it is virtually

impossible to "eavesdrop" and acquire the correct modulation order to enable

demodulation. If more infiormation were available regarding the e m r correction coding

and control block formats, the demodulator's operator could assume a "guess" at the

modulation order and observe the symbols, making further assumptions as required to

obtain correct symbol outputs. However, even if this were the case, the correct received

message could not be confirmed unless one knew what was originally being

transmitted! Suffice it to say that %al world" signal testing produced results of no real

significance other than what appeared to be bnef instances of "consistent'' symbol

outputs for a few symbol durations.

5.4 Filtering Verification

The performance of the filtering mutines (both the CONVOLVE assembly language

routine and the slower C-based windowing filter) was evaluated by feeding a white

noise source (readily available as a built-in signal tiuiction on the HP-8904A) with a 4V

amplitude into the Quad C40 system input (the input port on the Analog Daughter

Module ADC Board) with the processor(s) running the filtenng routine(s) with and

without the demodulator code. A M e r verification was performed by inputting the

CLOVER "four tone test" signal to judge the degree of camer isolation provided by the

filtering algorithms. The fact that the filter output for the CONVOLVE routine

remained very well defined even when the demodulator code was simultaneously

executing and outputting valid symbols indicates that the system was not "bogging

down" on the filtenng execution; however, the system was not able to simultaneously

filter and demodulate when running the C-filter, as evidenced by emneous "garbage"

symbol outputs and a severely aliased filter response. On its own the C-filter did do a

fairly good job of merely filtering the input signal sequence; Figures 5-13 and 5- 14

provide examples of the filter testing responses (with no demodulation processes

running) obtained h m the spectnim analyzer, while Figure 5-15 illustrates the filter

spectnim output while demodulating the CLOVER "fou tone test" signal.

W C L . k S D P

P-00 NO. a

Figure 5-13: Filter Response to White Noise Input - C FUter

(sample ratHkHz, taps=ûS, wid th=2SOHz, fC=2lrAz)

Figure 5-14: Filter Response to White Noise Input - CONVOLVE Routine

(sample ratdkHz, tapd5, width=250Hz, fc=2kEIz)

Figure 5-15: Four Tone Test Filtering and Demodulation - CONVOLVE

(sample ratdkHz, taps450, width=125Hz, fe=2062.5Hz)

Routine

The skth chapter presents a bief discussion of the conclusions drawn fkom the project,

and highlights some related areas that may benefit h m further research.

Chapter VI

CONCLUSIONS

A real-time DSP-based parallel PSK demdulator has been developed. The

demodulator has demonstrated the ability to demodulate four parallel carriers up to 8-

PSK in the 2kHz fiequency range, at keying speeds approaching 600 Baud depending

on the modulation order employed.

The system remains flexible, with al1 parameters easily reconfigured "on the fly" in

software by the user. Indeed, the parallel data stream nature of the signalling provides

many possible configurations that remain to be investigated, such as carrier datastream

redundancy across multiple carriers, fiequency hopped carrier tones, etc.

Future work should also entai1 the development of a real-time post-demodulation Reed-

Solomon error correction and recovery decoder capable of processing multiple input

symbol strearns simultaneously. When coupled with a demodulator "hold" feature to

preserve phase lock states during camer "off' times, this would allow true verification

of test messages transmitted via the CLOVER-II Board or sirnilar "on-off' keyed

signals .

Of course, extension of the work to incorporate the ability to successfully demodulate

QAM-type sigaals, using phase and amplitude keying, would be a worthwhile

development to broaden the application range of the demodulator. The incorporation of

a front-end FFT, capable of shultaneous operation acmss multiple fiequencies, would

allow the system to dynamically determine the carrier fiequency tones present and set

the demodulation and filtenng parameters without pnor knowledge provided by the

user. A " s p e c ~ m approximation" could also be incorporated to allow dynamic

allocation of filter widths and response slopes, producing a very "intelligent" multiple

carrier PSK demodulator.

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DEMODULATOR SOURCE CODE EXAMPLES

Demodulation Code for 'CPU-A":

/* Written by R.Tervo ** JüNE 1995 ** for PLL development */ /* does generic PSWFSK demodulation (no bit sync yet: July 14, 1995) */ /* -------O,,,,-,.---,,------- - ---------- - ---- */ /* PSK40.C : R.Tervo JULY 28,1995 */ /* Fully-working N-PSK (N= 0.3) including bitsync & symbol output */ /***********************************************************/ /* PLL Version June 19, 1992 - rt */ /* C40 version May 1 7, 1995 - rt (nineteen hundred and ninety five) */ /* OPTIMIZATION TESTS June 18,1992 maximum dock speed = 10 kHz */ /* Using opt3O and other mods June 24,1992, maximum speed = 14 kHz */ /* Using the C40 boards, runs easily at 25 kHz no special tricks *I /* L-----------i ---------O--- ----------------------.-- */ /* With filter mods (160 taps), single proc. nuis at l2Khz MAX!! June 1996 */ /******************************************************************/ /* * / /* Modified by Barry Lanàry October 1996 */ /* - Parallel PSK Demodulator TESTTNG ROUTINE * / /* - Mu1 ti-processor usage */ /* - does contain FIR bandpass filtering */ /* (test for symbol outputs) */ /* to isolate a single carrier tone */ /* - this code is intendeci to run on the DSP in */ /* Module Site "A" of the QPCC40 Board */ /* ("CPU-A") */ /*****************************************************************/

Header Files ....................

#include <prts\intpt40.h> /* Intempt support: parallel nuitirne library */ #include qanier.h> /* Defines ptrs to DSPLiNK registers, for DMCB */ #include ~ o m p t 4 O . b #include <float.h> #include <math.h> #include <&ainit. h> #include Kstdlib. h>

#define TRUE 1 #define FALSE O #definepi 3.1415926 Mefine TAPS 100 /* choose the number of taps for the filter */ Mefine BUFSIZE 1024 /* MUST BE A POWER OF TWO and MUST BE >= TAPS */

#define MAXPOINTS 2048 #inchde <rom.h>

l* variables used by the intempt senrice routine */ long int inputA; volatile double input, t input0 , tiuput l=0; volatile ht iflag; double *data = (double *) 0x80001000, I* MUST BE ON A 0000 BOüNDARY */ double filter[TAPS]; /* set up an array for filter taps */

/* extemal assembly language convolve() prototype */ double convolve( double *data, double *filter, int taps, int bufsize );

/*----- Global Variables -----*/

double outputA; double width = 125; /* bandpass filter width in Hz */ double Fc = 2062; /* filter center freq in Hz. */ double Fs = 10000; /* sampling rate in Hz. */ int i = BUFSIZE; /* pointer to input data array */ int x,t; double y;

/* BE SURE THAT "Fc" IS EQUAL TO USER-ENTERED CARRIER FREQ.!! */

double sinus[2048]; /* lookup table */

int channel[2] = @,O}; /* scope outputs */

/* PSK 600 BAUD 1800 Hz carrier $1 /* OLD VALUES RT */ 1* int gOOûp0 = 0x0080; I* pams: f-correction * 65536 */ /* int gOOûpl = 0x0180; /* parms: p-correction * 65536 */ /* int shift = 20; /* allowable +/- Fc shifi (Hz) */

int gOOOp0 = 0x0080 12; /* p m s : f-correction * 65536 */ int gOOOp15 ûxOl8O 1 2; /* panns: p-correction * 65536 */

int intlen = 20; /* parms: integral length */ int simple = 10000; /* parms: sample rate */ int shift = 20; /* allowable +/- Fc shift (Hz) */

/* THESE TERMS WILL BE OVERWRITTEN BY USER-SUPPLIED VALUES */ int centre = 2062; /* parms: center (Hz) */ int mode = 4; /* defhe WPSK order */ float baud = 3 1.5; /* define keying speed (bps) */

long* timer0_control= (long *) 0x0100020; long* timer0-count = (long *) 0x01 00024; long* therOqeriod = (long *) 0x01 OOO28;

int setperiod, newperiod; int fifo[ 2048 1, ix19~, outpt~û; double r; main() { /* ------O-------- R.Tewo ---- April8, 1992 - - - */ /* In which 1 construct a PLL */

int sin-integral, sin-integral-insync; int cos-integral, cos-integral-insync; int bit-sync-correction;

int unsigned-sin, unsigned-cos; double mixed-datai5 121; I* altemathg sin&cos mixed-data */

double cos2, sin& magnitude, diff, ideal = 10000 * 10000, agc = l5OOOO.O;

char f?eqstr[80]; int xpos=O, endpoint;

/***BIT SYNC ***/ int symbol, old-symbol, edge; int clock, oldclock;

int j, & x, Y; int counter, debut, fin; /* buffer pointers *I int dcount, dend, dendx;

char message[80], text[80];

double x-in;

double sample-rate, mixing-fiequency ; double step-size, thi-tep, initialalstepepsue, max-step, minstep; double mixin~sin, mixing-COS; double oldlphasd, old2phasec0, old3phasec0, temp; double p-factor, f-correct, p-correct; double error, phase, reference=û;

/* N-PSK MODE = 0..8 "1 int mode=+ sector; double sectorsize, halfsector;

unsigned long *COMO = (unsiped long *) 0x0010004 unsigned long *COMI = (unsigned long *) 0x00100050;

/*** READ GENERIC DEMOD PARAMETERS FROM THE PC ****/ /*** for CARRIER FREQ, KEYING SPEED, PSK ORDER *********/ ...........................................................

COM 1 [O] = 0x00000 1 0; P enable PORT A 1 for INPUT */

while( !(COMI [O] & OxOlE00) ); /* wait for data */ centre = COM1[1] & Ox0000FFFF; /* get carrier */ while(cp-out-level(0)); /*wait to pass on to CPU-B *I out-word(centre,O) ;

while( !(COMI [O] & OxOlE00) ); /* wait for data */ baud = *( float *) &COMl[l]; /* get baud rate */ if( baud < 1 ) baud = 1; while(cp-out-level(0)); /* wait to pass on to CPU-B */ out-word(baud,O);

while( ! (COM 1 [O] & 0x0 1E00) ); I* wait for data */ mode = COM1[1] & 0xO000001F; /* get mode */ if(mode=O)mode= 1; while(cp-out-level(0)); /* wait to pass on to CPU-B */ out-word(mode,O);

/* set integral length to two cycles of carrier */ /*intlen = (sample 1 centre);*/ intlen = 50; /* parms for 4 carrier demod */ shift = centre * 0.03;

/***************+**********************************/ /* henceforth COMl is used exclusively for output */

COM I [O ] = 0x0000008; /* enable PORT A 1 for OUTPUT */ /*** BIT SYNC ***/

setpenod = 20000000 / (4 * baud); /* set for 2x baud clock */ *timerOqeriod = newperiod = setperiod; *timerûerOcontrol = OxO3C3;

/* bit sync PLL correction factor is 1/32 of one period */ bit-sync-correction = setperiod / 32;

/* choose N-PSK MODE = 0.3 */ /* The angular divisions (decision boundaries) /* defining PSK states are derived dynamically for N-PSK /* without the need for a lookup table (or switch statement) /* Symbols are assigned automatically starting with the letter 'A1*/

sectorsize = 2 * pi / mode; /* a.k.a. "pi a la mode" */ halfsector = sectorsize / 2;

p-factor = 1024 / (2 * pi); /* phase lock correction factor */ /* steps per radian in sin table. */

/* CREATE A sine[2048] LOOKUP TABLE with period = 1024 pts */ for( x=O; ~ ~ 2 0 4 8 ; x* ) sinus[x] = sin( 2 * pi * x / 1024.0 );

sarnple-rate = (double) sample; Fs = sample-rate;

mixing-fiequency = (double) centre; /* Hz */ Fc = mixing-fiequency;

initi-tep-size = 1024.0 * meg-fkquency / sample-rate; max-step = 1024.0 * (muring-fiequency + shift) I sarnple-rate; min-step = 1024.0 * (mi~ing~fiequency - shift) sarnple-rate; step-size = initial-step-size;

f-correct = ((double) g000p0) 1 65536.0; /* read parms from global RAM */ f-correct /= pi; p-correct = ((double) g000pl) / 65536.0 * p-factor;

h = 2 * intlen; /* buffer integration interyal */ debut = 0;

this-step = 0; sin-integral = 0; cos-integral = O;

for( x=O; x<BUFSIZE; x*) data[x] = 0.0; /* initialize data array to zero */

for( t ~ 0 ; t<rAPS; t++ ) { y = (double) (t - TAPS/2);

if(-) y = 0.0001; filter[t] = (l/@i*y)) * sin(pi*y*width/Fs) * cos(2*pi*y*Fc/Fs);

1 /* MAIN PROCESSING LOOP STARTS HERE */

MA-Init( sarnple-rate ); i = BUFSIZE;

/* */ while(1) { /* infinite loop */ while( iflag ); /* wait for a sample (ISR clears iflag) */ iflag = 1; /* reset iflag */

/* */

/* wait to pass sample on to CPU-B */ while(cp~out~leve1(O)); out-word(inputA, O);

if(--i < O ) i = (BUFSIZE -1); data[i] = (double) inputA; /* new sample input *l

/* AGC bottlenecks/ /* perfom agc adjustrnents penodically (once every screen refresh) */ /* cos2 = cos-integral

sin2 = sulintegral; magnitude = cos2 * cos2 + sui2 * sin2; /* do as float, avooi overflow */ agc += ( magnitude - ideal ) 1 10000.0; if( agc > 1 O000000 ) agc = 10000000; if( agc c 0x80 ) agc = 0x80; */

this-step += step-size;

if( this-step > 1024.0 ) this-step = 1024.0; if( this - step c 0.0 ) this-step += 1024.0;

outputA = convolve( &data[i], filter, TAI'S, BUFSIZE ); /* convolve */

r = outpuwagc; I* scaled accordingly */

I* EVEN # ENTRIES IN mixeci-data FORM THE SINE INTEGRAL */ /* ODD # ENTRIES IN mixed-data FORM THE COSINE INTEGRAL */

mixing-sin = sinus[ (int) this-step 1; sin-integrai += (mixededdata[fin++] = (int) (r * mixing-sin)) - mixed-data[debut*];

mixing-cos = sinus[ 256 + (int) this-step 1; cos-inteprai += (mixed-data[fin++] = (int) (r * mixiirg-cos)) - mixeci-data[debut++];

if( fïn>255) h = O ; ifldebut > 255 ) debut = 0;

/* find phase fiom math library (NOT LOOKUP TABLE) */ phase = atan2( (double) sininintegral , (double) cos-integral );

/* lowpass FIR filtering afler the arctan block */ temp = ( phase + oldlphase + old2phase + old3phase ) / 4; old3phase = old2phase; old2phase = oldlphase; oldlphase = phase;

phase = temp;

/* ............................... ----,,,---------.-------.- */ /* define N-PSK decision boudaries dynamically */ /* based on expected constellation order: mode = N *I /* -pi <= phase <= +pi, scaled to an integer sector */ I* where "sector is O <= phase < mode */ /* the "reference" phase is centered in the sector */ /* e.g for QPSK, mode = 4, defining four sectors as */ /* sector = ( 0, 1,2,3 ), symbol = { A, B, C, D } */ /* symbols are labelled ccw starting with 'A' @ -pi */ /* e.g. */ /* *B D * 1 * C */ /* BPSK ----- QPsK -------- */ /* * A A * I * B */

sector = (int) ( mode * ( (phase 1 pi) + 1 ) 1 2.0 ); symbol = sector + 'A'; reference = sectorsize * sector + haifsector - pi;

error = phase - reference; /* phase emr in radians */ this-step = error * p-correct; I* do a jump phase correction */

/* frequency can be adjusted UP if anywhere below max-step (error < 0) */ /* frequency can be adjusted DN if anywhere above minstep (error > 0) */ /* the size of the correction drops as correct phase lock is approached */

step-size = f-correct * error, iq step-size < minstep ) step-size = minstep; if( step-size > macstep ) step-size = max-step;

if( symbol != old-symbol ) { edge = TRUE;

old-symbol = symbol; 1

clock = ( *timerO_control& 0x080 ) ? 1 : 0;

if( edge ) /* bit edge !! */ {

if( dock ) { newperiod = setperiod + bit-sync-correction; ) else { newperiod = setperiod - bit-syn~~correction; 1 edge = FALSE;

if( clock < oldclock ) /* 2x BIT-CLOCK FALLING EDGE (rniddle) */ i

cos-integral-insync = cos-integral; sin-integral-insync = sin-integral;

fifo[ inqe ] = symbol; I* output one symbol */ b t r = ( in* + 1 ) & ûx07FF;

if( ! (COM 1 [O] & 0x0 1 EO) ) ( COM1[2] = fifo[ outptr 1;

outptr = ( outptr + 1 ) & Ox07FF; 1

oldclock = clock; 1

if( clock > oldclock ) /* 2x BIT-CLOCK RISING EDGE */

*timerûqeriod = newpenod; newperiod = setperiod;

ifl ingtr != outptr ) if( !(COMI [O] & Ox01EO) ) { COMl[2] = fifo[ outptr 1;

outptr = ( outptr + 1 ) & Ox07FF; 1

oldclock = dock;

/* end infinite loop */

) /* end of maino */

Intempt Service Routine ...............................

void c-int04(void) /***************************************~********************** The is the intempt service routine for the IIOFl intempt. This intemipt occurs on the event that the input data regs are empty. Outputs the next value for the ramp to Channel O and Channel 1 outputs.

Inputs: i: Global Variable used as a counter.

****************************************************************/ { volatile unsigned long dummy;

dummy = *DMl-lNT-STATUS; /* Clear the intempt. */

/* --- interrupt service routine -- */ inputA = *DM1-CHO-IN-DATA; /* fetch the new sample */ iflag = 0; /* signal intemipt event */

) /* end ISR */ /******************************************************************/

Demodulation Code for TPU_Cm:

/* Written by R-Tervo ** JUNE 1995 ** for PLL developmuit */ /* does generic P S W K demodulation (no bit sync yet: July 14, 1995) */ /* -- --- */ /* PSK40.C : R.Tervo JULY 28,1995 /* Fully-working N-PSK (N= 0.3) including bitsync & symbol output /*********************trCit*rCf*8**t***************************/

/* PLL Version June 19, 1992 - rt */ /* C40 version May 17, 1995 - rt (nineteen hundred and ninety five) */ /* OPTIMIZATION TESTS Junei 8,1992 maximum clock speed = 10 kHz */ /* Using op00 and other mods June 24,1992, maximum speed = 14 kHz */ /* Using the C40 boards, nuis easily at 25 kHz no special tricks */ /* C ------ -A--- H----UHIIII --mUIINNIHII--------- */ /* With filter mods (160 taps), runs at 12K.z MAX!! June 1996 */ /*********************************************************/ /* */ /* Modified by Barry Landry Oct. 1996 */ /* - Parallel PSK Demodulator TESTING ROUTINE */ /* - Multiprocessor usage */ /* - does contain FIR bandpass f i l t e ~ g * / /* (test for symbol outputs) */ /* to isolate a single carrier tone */ /* - this code is intended to run on the DSP in * / /* Module Site "Cm of the QPCC40 Board */ /* ("CPU-Cl') */ ..............................................................

/****************** Weader Files

*à*****************/

#include cprtsüntpt40.h> /* Intempt support: parallel runtime library *l #include ~arrier.h> /* Defines ptrs to DSPLINK registers, for DMCB */ #include <compt40.h> #include <float.h> #include <math.h> #include qtdlib .h>

#define TRUE 1 #define FALSE O #define pi 3.1415926 #define TAPS 100 /* choose the number of taps for the filter */

#define BUFSUE 1024 /* MUST BE A POWER OF TWO and MUST BE TAPSS/

#define MAXPOINTS 2048 #include <rom. h>

/* variables used by the intempt service routine */ volatile double data-in, tinputû=û, thput 1 4 ;

double *data = (double *) 0x80003000; /* MUST BE ON A 0000 BOUNDARY */ double filter[TAPS]; /* set up an a m y for filter taps */

/* extemal assembly language convolve0 prototype */ double convolve( double *data, double *filter, int taps, int bufsize );

/*----- Global Variables -----*/ long int input; double outputc; double width = 125; /* bandpass filter width in Hz */ double Fc = 2062; P filter center fkq in Hz. */ double Fs = 10000; /* sampling rate in Hz */ int i = BUFSIZE; I* pointer to input data amy */ int x,t; double y;

/* BE SURE THAT "Fc" IS EQUAL TO USER-ENTERED CARRIER FREQ.!! */

double sinus[2048]; /* lookup table */

/* PSK 600 BAUD 1800 Hz carrier */ int gOOOpO = 0x0080 / 2; /* p m s : 0.5*(f-correction * 65536) *1 int gOOOpl = 0x0180 / 2; /* parms: OS*(p_correction * 65536) */ int intlen = 20; /* parrns: integral length */ int sample = 10000; /* parms: sample rate */ int shift = 20; /* allowable +/- Fc shift (Hz) */

1' THESE TERMS WILL BE OVERWRITTEN BY USER-SUPPLIED VALUES */ int centre = 2062; /* parms: center (Hz) */

*/ int mode = 4; /* define N-PSK order float baud = 3 1.5; /* define keying speed (bps) */

long* timer0_control= (long *) 0x0100020; long* timerûrOcount = (long *) 0x0100024; long* time-enod = (long *) 0x0100028;

int setperiod, newperiod; int fifo[ 2048 1, ingû=û, ou tpH; double r; maino { /* ----- RTervo -- April8,1992 -- */ /* In which 1 construct a PLL */

int sin-integral, sin-integral-insync; int cos-integral, cos-integral-insync; int bi t-sync-correction;

int unsigned-sui, unsigned-cos; double mixed-data[5 121; /* altemating sin&cos mixadata */

double cos2, sin2, magnitude, diff, ideal = 1ûûOO * 10000, agc = 150000.0;

char fieqstr[80]; int xpos=O, endpoint;

/*** BIT SYNC ***/ int symbol, old-symbol, edge; int clock, oldclock;

int j, k, x, y; int counter, debut, fin; /* buffer pointers */ int dcount, dend, dendx;

char message[lO], text[80];

double x-in; double sarnple-rate, mixing-fiequency; double step-size, this-step, initial-step-size, m-tep, mkstep; double mixing-sin, mixingcos; double oldlphase4, old2phasd, old3phasec0, temp; double p-factor, f-correct, p-correct; double error, phase, referencd;

/* N-PSK MODE = 0. .8 */ int mode=4, sector; double sectorsize, halfsector;

unsigned long *COMO = (unsigned long *) 0x00100040;

unsigned long *COM4 = (unsigned long *) 0x00100080;

/*** READ GENERIC DEMOD PARAMETERS FROM THE PC ***/ /*** for CARRIER FREQ, KEYING SPEED, PSK ORDER ********/ /*********************************************************/

while( !cp_in_Level(3)); /* wait for data */ centre = in-word(3); I* get carrier */

while(cp~out~level(0)); /* wait to pass on to CPU-D */ out-word(centre,O); l* send on to CPU-D */

while( !cp-in-level(3)); /* wait for data */ baud = in-word(3); /* get baud rate */

while(cp-out-level(0)); /* wait to pass on to CPU-D */ out-word(baud,O); /* send on to CPU-D */

while( !cp_in_level(3)); /* wait for data */ mode = in-word(3); /* get mode */

while(cp~out~level(0)); I* wait to pass on to CPU-D */ out-word(mode,O); /* send on to CPU-D */

/* set integral length */ I* intlen = (sample / centre);*/ intlen = 50; /* p m s for 4 carrier demod. */ shift = centre * 0.03;

/* henceforth COM4 is used exclusively for output */ COM4[0] = 0x0000008; /* enable PORT C4 for OUTPUT to LIA */

/*** BIT SYNC ***/

setperiod = 20000000 1 (4 * baud); /* set for 2x baud clock */ *timerOjenod = newperid = setperiod; *timerO_control= OxO3C3;

I* bit sync PLL correction factor is 1/32 of one period */ bit-sync-correction = setperiod 1 32;

/* choose N-PSK MODE = 0.3 */ /* The anplar divisions (decision boudaries) /* definhg PSK states are derived dynamicaüy for N-PSK I* without the need for a lookup table (or switch statement) /* Symbols are assigned automatically starting with the letter 'A'*/

sectorsize = 2 * pi / mode; /* a.k.a "pi a la mode" *1 halfsector = sectorsize 1 2;

p-factor = 1024 1 (2 * pi); /* phase lock correction factor */ /* steps per radian in sin table. */

P CREATE A sine[2048] LOOKUP TABLE with period = 1024 pts */ for( x=O; xQ048; x++ ) sinus[x] = sin( 2 * pi * x 1 1024.0 );

sample-rate = (double) sample; Fs = sarnple-rate;

rnixing-fiequency = (double) centre; I* Hz */ Fc = mixing-fiequency;

initial-step-size = 1 024.0 * mixing-fiequenc y I sample-rate; max-step = 1024.0 * (rnixiag-fiequency + shifi) 1 sample-rate; min-step = 1024.0 * (mixing-fiequency - shift) 1 sample-rate; step-size = i n i t i a @ q @ z e ;

f-correct = ((double) g000p0) 1 65536.0; /* reaii parms h m global RAM */ f-correct /= pi; p-correct = ((double) g000p 1) / 65536.0 * p-factor;

for(x=O; xc5 12; x*) mixed-data[x] = 0;

fui = 2 * intlen; /* buffer integration interval */ debut = 0;

this-step = 0; sin-integral = 0; cos-integral = 0;

for( x=O; XCBUFSIZE; x*) data[x] = 0.0; /* initialize data array to zero */

{ y = (double) (t - TAPS/2); if-) y = 0.0001; filterrt] = (l/@i*y)) * sin@i*y%wîdth/Fs) * cos(2+pif yfFc/Fs);

1

/* = MAIN PROCESSING LOOP STARTS HERE */

i = BUFSIZE;

/* */ while(1) { /* infinite loop */

/* */ while(!cpcpinin1eve1(3)); /* wait for new sample fron "B" */ input = in-word(3);

while(cp~out~level(0)); /* wait to pass on to CPU-D */ out-wordjinput,O); /* send on to CPU-D */

if(--i c O) i = (BUFSIZE - 1); data[i] = (double) input; /* new sample input */

/* AGC section bottleneck */ /* perform agc adjustments periodically (once every screen rehsh)

cos2 = cos-integral; sin2 = sin-integral; magnitude = cos2 * cos2 + sin2 * sin2; */ /* do as float, avoid overflow */

agc += ( magnitude - ideal ) / 10000.0;

if( agc > 1OûOûOûO ) agc = 10000000; if'( agc c 0x80 ) agc = 0x80;

this-step += st-size;

if( this-step > 1024.0 ) this-step = 1024.0; if( this-step < 0.0 ) this-step += 1024.0;

outputC = convolve( &data[i], filter, TAPS, BUFSIZE ); /* convolve */

r = outputC / agc; /* scaled accordingly */

/* EVEN # ENTRIES IN mixeci-data FORM THE SINE INTEGRAL */ /* ODD # ENTRIES IN mixed-data FORM THE COSINE INTEGRAL */

mWngsin = sinus[ (int) this-step 1; sinjntegral += (mixed-data[-] = (int) (r * mixing-sin)) - mixed-data[debut++];

mWagcos = sinus[ 256 + (int) this-step 1; cos-iniegral += (mixed-data[h++] = (int) (r * mixing-cos)) - mixed-&ta[debut++];

if( fin>255) h = O ; ifldebut > 255 ) debut = 0;

/* find phase fiom math library (NOT L O O m TABLE) */ phase = atan2( (double) sininuitegral , (double) cos-integrai );

/* lowpass FR filtering d e r the arctan block */

ternp =(phase+oldlphase+old2phase+old3phase)/4; old3phase = old2phase; old2phase = oldlphase; oldlphase = phase;

phase = temp;

/* -------------------œ- - ---------- -------- --o.--------.-- -0 *! /* define N-PSK decision boundaries dynamically */ /* based on expected constellation order: mode = N */ /* -pi C= phase <= +pi, scaled to an integer sector */ /* where "sector" is O <= phase < mode */ /* the "reference" phase is centered in the sector */ I* e.g for QPSK, mode = 4, defining four sectors as */ /*sector={O,l,2,3),symbol={A,B,C,D} */ /* symbols are labelled ccw starting with 'A' @ -pi *I /* e.g. */ /* * B D * I * C */ /* BPSK ----- QPSK --------- */ /* * A A * I * B */

sector = (int) ( mode * ( @hase 1 pi) + 1 ) 1 2.0 ); symbol = sector + 'A'; reference = sectorsize * sector + halfsector - pi;

error = phase - reference; /* phase error in radians */ this-step -= error * p-correct; /* do a jump phase correction */

/* fiequency can be adjusted UP if anywhere below max-step (enor < O) * 1 /* fiequency can be adjusted DN if anywhere above minstep (emr > 0) *I /* the size of the correction drops as correct phase lock is approached */

step-size = f-correct * error, if( step-size < min-step ) step-sue = minstep; if( step - size > max-step ) step-size = max-step;

ifl symbol != old-symbol ) { edge = TRUE;

old-symbol = symbol; 1

clock = ( *timerO_control & 0x0800 ) ? 1 : 0;

if( edge ) I* bit edge ! ! *I {

if( dock ) ( newpenod = setpenod + bit-sync-correction; } else { newpenod = setperiod - bit-sync-correctiou; } edge = FALSE;

if( clock < oldclock ) /* 2x BIT-CLOCK FALLING EDGE (middle) */ {

cos-integral-insync = cos-integral; sin-integral-insync = sin-integral;

fifo[ inqtr ] = symbol; /* output one symbol */ inqtr = ( U t r + 1 ) & Ox07FF;

if( !(COM4[0] & Ox01EO) ) { COM4[2] = fifol outptr 1;

outptr = ( outptr + 1 ) & Ox07FF; 1

oldclock = clock; 1

if( clock > oldclock ) /* 2x BIT-CLOCK RISING EDGE */

* timerûqeriod = newpenod; newpenod = setperiod;

if( in- != outptr ) iT( !(COM4[0] & 0x0 1 EO) ) ( COM4[2] = fifol outptr 1;

outph- = ( outptr + 1 ) & Ox07FF; 1

oldclock = clock; 1

} /* end infinite loop */

) /* end of maino */

SAMPLE BATCH FILES FOR CODE COMPILATION

DSP Code Batch Fie %omp-dsp.batW Example:

echo off rem Compile and link using the TI C floating point compiler ver 4.5 rem To be used for TMS320C40 C source code

PC Calling Program Batch File ~compgcb.bat" Example:

bcc -w -ml -N -ICi\C~~~OARD\app - lib -LC:\C40BOARDbpp_lib\bor testerx c4xapp.lib 1bcfglib.lib

APPENDIX III

SAMPLE CALLINC; PROGRAM

/*******************************************************************/ // // // PARALLEL PSK DEMODULATOR CALLING (PC) PROGRAM 11 - written by Barry Landry // January 1996 // - loads (and nuis) the executable COFF files to the C40 board // - outputs the symbols h m the C40 DSP's to the screen // - uses fiuiction key toggles for output channel display /*******************************************************************/

Header Files ******************/ #inchde "c4xapp.h" /* NETAPI Applications Library */ #include <stdio.h> 1* Standard IO library */ #inchde cconio. h> #include <fcntl.h> #include <sys\types. h> #include <sys\stat.h>

Define Constants ...................... #define QPCC40-FILEA "ATEST.outqq I* COFF File to down load to QPC/C40B*/ #define QPCC40-FILEB "BTEST.out" I* COFF File to down load to QPC/C40B*/ #define QPCC40-FILEC "CTEST.out" /* COFF File to down load to QPC/C40B*/ #dehe QPCC40-FLED "DTEST.out" /* COFF File to down load to QPC/C40B*/

/* Set Stack Size if using BOFUAND C */

#ifdef BORLANDC- extem unsigned -stklen = Ox40OOU; #endif

//ASCII symbols : H A B C D E F G int colors[] = { 7, 12, 14, 149, 13, 1 1, 15);

Function Prototypes ************************/

void checkReturnCode(U1NT rehunçode);

Main Program ******************/ void main(int argc, char.* argv ) { UINT ret; PROC-ID *handleA, *handleB, *handleC, *handleD; int outfile; char *outfiletext, message[BO];

long newvalueA, newvalueB, newvaluel, newvalueD; unsigned long carrier, order; float baud;

int key=0, bitcounH, width=80; /* define the channel we print {1,2,3,4), where O is al1 (default) */ int channel-OUM; int letter-A = '?', letter-B = '?'; int letter-C = '?', letter-D = '?';

if(argc != 4 ) ( printf(" usage: psk carrier baud phases in"); printf("EXAMPLE: psk 2400 600 4 hW'); printflWBaud can be fiactional (e.g. 3 1.25) \nùiW); exit(- 1);

1 carrier = atol(argv[lJ); baud = atof(argv[2]); order = atol(argv[3]);

outfiletext = "PAR BITS.TXTV; outfile = open( outfiletext, O-RDWR ( O-TRUNC ( O-BINARY); iqoutfile = -1) // create the output file! outfile = open( outfiletext, O-RDWR 1 O-CREAT 1 O-BINARY. 3 84); iqoutfile = -1)

{printrùi\n\n CANNOT CREATE FILE! ! W); exit(- 1); 1

11 Reboot the C40 network. printf("a""); printf('lnRebooting the C40 network ...."); ret = G1obalalNetwork_Rebmt(); c heckRehunCode(ret); printflwOK");

11 ûpening Processor p~tf("\nOpening processor A ....."); ret=Open-Processor-Il( &hande& "CPU-A", NULL ); checkReh~nCode(ret); prhtfl"OKn);

f / ûpening processor printf("\nûpening processor B . .. . ."); remen-Processor_ID( &handleB, "CPU - B", NULL ); checkRetumCode(ret); printf("0K");

// ûpening processor printf("\nOpening processor C . . . . ."); ret=ûpen-ProcessorJD( &handleC, "CPU-C", NULL ); c hec kRetumCode(ret); print f("OKV);

// Opening processor printf("\nûpening processor D .... ."); ret=OpenJ?rocessorJD( &handleD, TPU-Dw, NLnL ); checkRetumCode(ret); printf("0Kn);

// Load and start the C40 program. printf("\nloading C40 program D %s ....", QPCC40-FILED ); ret=Load-And-Run-File-LIA( handleD, QPCC40-FILED ); chec kRetumCode(ret); printf("0K");

// Load and start the C40 program. printf("\nLoading C40 program C %s . ...", QPCC40-FLEC ); ret=Lod-AnddRununFileeLIA( handleC, QPCC40-FiLEC ); checkRetumCode(ret); print f("0Kg');

// Load and start the C40 program. printf("ùiLoading C40 program B %s ....ln, QPCC40-FILEB ); ret=Load-AnddRununFileeLIA( handleB, QPCC40-FILEB ); checkRehimCode(ret); printf("0K");

// Load and start C40 pmgram. printf("Woading C40 program A %s ....", QQPCC40-FILEA ); ret=Load-And-Run-FileeLIA( handleA, QPCC40-FILEA ); checkRetuniCode(ret); printf("OK\n\n");

pnntf("Sending demodulation parameters: ln"); printflWCarrier = %li Hz \n", carrier); printf("Keying Speed = %SSf Baud\n", baud ); printfT"PSK Order = %li-PSK W, order ); prinq"\n\n");

sprintq message, "%5.2f BAUD %Li-PSK %li HzW, baud, order, carrier); write( outfile, message, strlen( message ) + 1);

ret = Write-LIA-Words-32@andleA, 1, &carrier); i f(ret ! = RC-NO_ERROR) exit(3); ret = Wnte-LIA-FloatsJ2(handleA, 1, &baud); /* send dem0d.V iqret ! = RC-NO-ERROR) exit(3); /* parameters */ ret = Wnte-LIA-Words-32(handleA, 1, &order); /* to CPU-A */ if(ret != RC-NO-ERROR) exit(3);

printf('ln\nWaiting for bits ... Press ESC to Stop.\nW);

while( key != ESC ) { key = O;

if( kbhito ) { key = getcho; iq !key ) { key = 0x80 + getcho; /* printf(" [%02x] ", key ); */

switch( key ) { case Oxbb : chamel-out = 1;

textcolor(l5);

cprintfC"\n\r DISPLAY CH Ahk"); bitcount = 0; break;

case ûxbc : chamelout = 2;

case ûxbd :

textcolor(l5); cprintf("\n\r DISPLAY CH B\n\r"); bitcount = 0; break; :hannel-out = 3; textcolor(l5); cprinW1\n\r DISPLAY CH Ch\?'); bitcount = 0; break;

case Oxbe : chamel-out = 4; textcolor( 15); cprintf("\n\r DISPLAY CH Dh\r"); bitcount = 0; break;

case Oxbf : charnel-out = O; /* F5 is 'al1 channels' */ textcolor(l5); cprintrl\n\r DISPLAY ALL 4\n\Y8); bitcount = 0; break;

1 1

1 if( (bitcount+ 4) width) //

(cprintf("\n\r"); // controls symbol display on screen bitcount = 0; //

get output symbols from the DSPts! */ */ */

ret = Read-LIA-Words-32( handleA, 1, (unsigned long *) &newvalueA); if( ret != RC-NO-ERROR ) exit(3);

letter-A = (char) (newvalueA & oXO7F);

textcolor( colors[ letter-A & 0x071); if( !chamel-out II chamel-out = 1 ) { cprintq"%c", letter-A); bitcount = bitcount + 1;

ret = Read-LM-Words-32( handleB, 1, (unsigned long *) &newvalueB); if( ret != RC-NO-ERROR ) exit(3);

letter-B = (char) (newvalueB & oXO7F);

textcolor( colors[ letter-B & 0x071); if( !chamel-out II chamel-out = 2 ) { cprintf("%cm, letter-B); bitcount = bitcount + 1 ;

} write(outfile, &letter-B, 1);

ret = Read-LIA-Words-32( handleC, 1, (unsigned long *) &newvalueC); if( ret != RC-NO-ERROR ) exit(3);

letter-C = (char) (newvaluec & Ox07F);

textcolor( colon[ letter-C & 0x071); if( !chamel-out II chamel-out = 3 ) { cprintf("%cW , lette-); bitcount = bitcount + 1;

'

1 write(crutfile, &letter-C, 1);

ret = Read_LIA_WordsJ2( handleD, 1, (unsigned long *) &newvalueD); if( ret != RC-NO-ERROR ) exit(3);

letter-D = (char) (newvalueD & Ox07F);

textcolor( colors[ letter-D & 0x071); if( !chamel-out II chamel-out = 4 ) { cprint f("%cW , letter-D); bitcount = bitcount + 1;

1 write(outfiIe, &letter-D, 1);

} // end while !key

close( outfile); textcolor( 1 1 + 0x80); cprintf('ln\r\n\r Output text is in me: %SM', outfïletext);

textcolor(l5); cprintf("\n\n goodbye. .\de); normvideoo;

ret = Close-Processor-ID( handleA ); checkReumCode(ret);

ret = Close-ProcessorJD( handleB ); c heckReumCode(ret);

ret = Close-ProcessorJD( handleC ); checkRetwnC9de(ret);

ret = Close-Processor-ID( handleD ); checkReturnCode(ret);

/* end of main0 */

/* include subroutine for NETAPI error handler $1

CALLING PROGRAM WTH BPSK BITSTREAM DISPLAY

/*******************************************************************/ // // // PARALLEL PSK DEMODULATOR CALLING (PC) PROGRAM // - written by Barry Landry I l January 1996 // - loads (and runs) the executable COFF files to the C40 board 11 - outputs the BPSK bitstreams h m the C40 DSPts to the screen /*******************************************************************/

Header Files ******************/ #i.clude "c4xapp.htf /* NETAPI Applications library */ #inchde ~ td io .h> l* Standard IO iibrary */ #include Cconio. h> #inchde <fcntl.h> #indude <sys\types.h> #inchde <sys\stat. h>

Define Constants *********************/ #define QPCC40-FILEA "ATEST.outW /* COFF File to down load to QPC/C40B*/ #define QPCC40-FILEB "BTEST.out" /* COFF File to down load to QPC/C4OB*/ #define QPCC40-FILEC "CTEST.outW /* COFF File to down load to QPC/C40B*/ #define QPCC40-FILED "DTEST.outW /* COFF File to down load to QPC/C40B*/

/* Set Stack Size if using BORLAND C */

#ifdef BORLANDC- extem unsigned -stklen = Ox4000U; #endif

//ASCII symbols : H A B C D E F G int colors[] = { 7, 12,14,10,9, 13, 11 , lS ) ;

Function Prototypes ************************/ void checkRetumCode(U1NT retumlode);

Main Program ******************/ void main(int argc, c h a F argv )

UINT ret ; PROC-ID *handleA, *handleB, *handleC, *handleD; int outfile; char *outfiletex& rnessage[80];

long newvalueA, newvalueB, newvaluel, newvalueD; unsigneci long carrier, order; float baud;

int key=0, bitcount=û, width=80; int letter-A = '?', letter-B = '?'; int ietter-C = 'T, letter-D = '?';

int bit A=O, bit-B=O, bit-C=û, bit-D=O; int 01 cletter-~=O,old_letter-~4,old - letter-C=O,oId-letter_D=0;

if(argc != 4 ) ( printfl" usage: psk carrier baud phases W); printq"EXAMPLE: psk 2400 600 4 Mn"); printflWBaud cm be Wtional (e.g. 3 1.25) hW'); exit(- 1);

1 carrier = atol(argv[L]); baud = atof(argvL21); order = atol(argv[3]);

outfiletext = "PAR_BITS.TXT"; outfile = open( outfiletext, O-RDWR 1 O-TRUNC 1 O-BINARY); if(outfi1e = -1) // create the output file! outfile = open( outfiletext, O-RDWR 1 O-CREAT 1 O-BINARY, 384); if(outfi1e = -1)

( print fT "\n\n\n CANNOT CREATE FILE! ! W); exit(- 1); 1

// Reboot the C40 network. prind("\n"); printf("\nRebooting the C40 network ...."); ret = Global-Networic-RebootQ; c heckRetunCode(ret); printf("0K");

// Opening Processor printf("\nOpening processor A ....."); remen-Processor-ID( &hanclle& "CPU-A", NüLL ); checkRetumCode(ret); pnntf("0K");

11 Opening processor print$'\nOpening processor B . . . .."); ret=OpenJrocessor-ID( &handleB, "CPU - B", NULL ); checkRetumCode(ret); printf("0K");

// Opening processor printf("\nOpening processor C . . ..."); ret=Open-Processor-ID( &handleC, "CPU-C", NULL ); checkReturnCode(ret); printf("0K");

// Opening processor pnntf("\nOpenhg processor D . ...."); ret=ûpen~Processor~~( &handleD, "CPU-D" , NULL ); checkRetumCode(ret); printf("OKW);

// Load and start the Ca0 program. pnntf("\nloading C40 program D %s ....", QPCC40-FILED ); ret=Load-And-Run-FileeLIA( handleD, QPCC40-FILED ); checkReturnCode(ret); prinw OK") ;

11 Load and start the C40 program. printf("\nloading C40 program C %s ....", QPCC40-FILEC ); ret=Load-AnddRununFileeLIA( handleC, QPCC40-FILEC ); checkRetumCode(ret); pnntf("0K");

// Load and start the C40 program. printf("ùiLoading C40 program B %s ....", QPCC40-FILEB ); ret=Load-AnddRunUIIFiIeeLIA( handleB, QPCC40-FILEB ); checkRetumCode(ret); printfT"0K");

// Load and start C40 program. printfT"hLoading C40 program A %s . . ..", QPCC40-FLEA ); reFLoad-And-Run-File-LIA( handleA, QPCC40-FILEA ); checkReturnCode(ret); printf("0KùiW');

printf("Sending demodulation parameters: \n"); print$'Carrier =%Li* \n" , carrier); printfll'Keying Speed = %5.2f BaudW. baud ); printfTWPSK Order = %li-PSK in", order ); printfl1'Mn");

spnntf( message, "%5.2f BAUD %li-PSK %li Hzh", baud, order, carrier); d i e ( outfile, message, strlen( message ) + 1);

ret = Write-LIA-Words_32(handle& 1, &carrier); if(ret != RC-NO-ERROR) exit(3); ret = Write_LIA_FloatsJ2(handleA, 1, &baud); /* send demod.*/ if(ret ! = RC-NO-ERROR) exit(3); If piirameters */ ret = Write_LIA_Words_32(handleA, 1, &order); P to CPU-A */ i f(ret ! = RC-NO-ERROR) exit (3);

printf("\n\nWaiting for bits ... Press ESC to Stop.h\n");

while( key != ESC ) ( key = O;

if( kbhito ) { key = getcho;

if( !key ) key = 0x80 + getcho; 1 if( (bitcount+ 4) >= width) //

(cprint$'\nù"); 11 controls symbol display on screen bitcount=O; 11 1

/* */ /* get output symbols nom the DSP's! */ /* */

ret = Read-LIA-Words-32( handleA, 1, (unsigned long *) BnewvalueA); if( ret ! = RC-NO-ERROR ) exit(3);

letter-A = (char) (newvalueA & Ox07F);

textcolor( colon[ (bit-A & 0x07) + 11); cprintf("%c", bit-A); write(outfile, &bitA, 1); bitcount = bitcount + 1 ;

ret = Read-LIA-Words-32( handieB, 1, (unsigned long *) &newva.iueB); if( ret != RC-NO-ERROR ) exit(3);

letter-B = (char) (newvalueB & Ox07F);

bit-B = ( old-letter-B = letter-B ? '1' : 'O' ); old-letter-B = letter-B; textcolor( colon[ (bit-B & 0x07) + II); cprint$"%cW, bit-B); write(outfile, &bit-B, 1); bitcount = bitcount + 1;

ret = Read-LIA-Words-32( handleC, 1, (unsigned long *) 8rnewvalueC); if( ret != RC-NO-ERROR ) exit(3);

lette- = (char) (newvaluec & Ox07F);

bit-C = ( old-letter-C = letter-C ? ' 1 ' : '0' ); old-letter-C = letter-C; textcolor( colors[ (bit-C & 0x07) + 1 1); cprintf("%cW, bit-C); write(outfi1e. &bit-C, 1); bitcount = bitcount + 1 ;

ret = Read-LIA-Words-32( handleD, 1, (unsigned long *) &newvalueD);

if( ret != RC-NO-ERROR ) exit(3);

letter-D = (char) (newvalueD & 0A07F);

bit-D = ( old-letter-D = letter-D ? '1' : Y)' ); old-letter-D = letter-D; textcolor( colors[ (bit-D & 0x07) + 1 1); cprintf("%cN, bit-D); write(outfile, &bit-D, 1); bitcount = bitcount + 1;

} // end while ! key

close( outfile); textcolor( 1 1 + 0x80); cprintf("\n\r\n\r Output text is in file: %s\rW, outfiletext);

textcolor(l5); cpnntf("\n\n goodbye. .\nn); norrnvideo0;

ret = Close-Processor-ID( handleA ); checkRetuniCode(ret);

ret = Close-Processor-ID( handleB ); checkRetwnCode(ret);

ret = Close~Processor~TD( handleC ); checkRetumCode(ret);

ret = Close~ProcessorJD( handleD ); checkReumCode(ret);

/* end of maino */

/* include subroutine for NETAPI error handler */

CONVOLUTION ROUTINE

; C-CALLABLE CONVOLUTION ROUTINE MAR 28 1996 ; Input array MUST be on a block boundary for CIRCULAR ADDRESSING mode.

FP .SET AR3 ; FP is a pseudonym for AR3

.GLOBAL convolve ; entry point of execution

.BSS DATAPml ; receive a pointer to the data array

.BSS FILTER, 1 ; receive a pointer to the data anay

.BSS TAPSJ ; receive the number of filter taps

.BSS BUFSIZEJ ; receive the input bufKer size

convolve: - ; INITIAL,LZE C-FUNCTION PUSH FP ; Save dedicated registers LDI SP,FP PUSH RC PUSH BK PUSH AR4 PUSH AR5

LDI *-FP(2),RO ; ;ove passed arguments to desired locations STI RO,@DATAPTR LDI '-FP(3),RO STI RO,@FILTER LDI *-FP(4),RO STI RO,@TAPS LDI *-FP(S),RO STI RO,@BUFSIZE ; (1024) MUST BE A POWER OF TWO

LDF O.O,R2 ; initialize R2 = temporary output integd LDF O.O,RO ; initialize RO = final output integral LDI @ILTER,AR4 ; Point to the filter array LDI @DATAPTR,ARS ; Point to the data array LDI @TAPS,RC ;Loop#oftimesinTAPS

SUBI 1,RC ; subtract one h m the loop counter LDI @BUFSIZE,BK ; set BK (used for circular addressing)

RPTB CONV ; repeat block RC times (down to CONV) MPYF3 *ARS++%,*AR4*,RO ; mult. filter and input data (circular) ADDF3 RO,R2,R2 ; accumulate results

CONV LDF R2,RO ; put m e r in RO

POP AR5 ; RESTORE THE REGISTER VALUES AM> RETURN POP AR4 POP BK POP RC POP FP RETS

APPENDIX VI

ORIGINAL FILTERING CODE - C VERSION

/* */ /* Barry Landry */ /* February 1996 */ /* */

/* - implements a F R filter structure on the QPCC40 board */ /* - filter order must be set before compihg! ! ! */ /* - configured with tap calculator for a BANDPASS filter */ /* - tap calculator originally authored by Paul Beer, UNB, June 1991 */ /* */

Header Files *******************/

#inchde <prts\iatpt40.h> /* Interrupt support: parallel runtime library */ #inchde aarrier.h> /* Defmes ptrs to DSPLINK registers, for DMCB */

#define TRUE 1 #define FALSE O

#define MAXPOINTS 2048 #inchde <rom.h> /* variables used by the intempt senice routine */ volatile double input, data-in, tinput0=0, tinput l=0; volatile int iflag;

int channelp] = {0,0); /* scope outputs */

int fs = 20000; /* panns: sample rate */

long* (long *) 0x0 1 00020;

long* timer0-count = (long *) 0x01 ûûûî4; long* theioqenod = (long *) 0x01 OO28;

ICS- 1 OOV BAND PASS FILTER TAP GENERATOR

This program calculates the tap values for the FIR section of the ICS- 1 00V ND-DIA board in the VME bus. The calculated taps are stored in an ASCII text file dong with a header that gives information about the fiher that was created.

When this program is done calculating and storing the filter TAP2SRE.C is run to create a Motorolla S-record file that can be downloaded to the ICS- 1 00V directly.

AUTHOR : PAUL E. BEER DATE : JUNE6,1991 EXECUTE : tap2.exe COMPILER: MicroSoft C version 5.1 COMPILE : cl /AS tap2.c graphics.lib Aink /ST:Ox4000

OTHER FILES REQUIRED: tap2sre.exe

Software created at The University of New Brunswick

unsigned long *COMO = (unsigned long *) 0x001 00040; unsigned long *COMl= (unsigned long *) 0x00100050;

maino

int i, j, k, X, y;

/* filter section variables */

int end; double yout, sum, x-in; double x-m[25 51; double sarnple-rate;

int n, half, count; unsigned int order; unsigned long int bw, fs, scale-fat; float @, fc, hi[256], hb[256], wn[256]; float pi, arg, scalebp, largejos, large-neg;

/* SET THE FILTER ORDER */ /****************************/

/**********************************/ /* SET THE SAMPLING FREQUENCY */ /**********************************/

/* SET THE CENTER FREQUENCY */ /* - MUST be less than 112 */ /* sample rate! ! ! */ /************************************/

/* SET THE BANDWIDTH */ /**************************/

/*****************************************************************/ /* D M D E bw BY TWO TO GET THE EXPECTED BANDWIDTH OTHERWISE THE */ /* NEGATIVE BANDWIDTH WILL ALSO BE INCLUDED CAUSING THE FILTER */ /* TO BE TWICE AS WIDE AS EXPECTED */ /*****************************************************************/

fp = (float) ( (float)bw 1 (tloat)fs ); half = (order- 1)/2;

for ( n 4 ; nc-rder- l ; nt+) {

arg = (n-haif); if (2*pi*@*arg = 0.0) {

M[n] = 1 .O; 1

else

hl[n] = sin(2 *pi*fp*arg)/(2*pi*Q*arg); 1

wn[n] = 0.42-OS*cos(2+pi*n/(order- l))+O.O8 *cos(4*pi*n/(order- 1)); hl[n] = hl[n]*wn[n]; hb[n] = hl[n]*cos(2*pi*fc*arg);

1 /*************************************************/ /* henceforth COMl is used exclusively for output */ /****************************((i*******************/

COM 1 [O] = 0x0000008; /* enable PORT Al for OUTPUT */

sarnple-rate = (double) fs;

/* MAIN PROCESSING LOOP STARTS HERE */ n = order- 1 ; /* this is the filter order (N- 1) */

D2A-Init( sarnple-rate ); end = order; /* = initialize the anay of input samples to zero!! */ for (i=O; i .: end; i++)

x_in[i] = 0.0; 1

/* */ while(1)

{ /* infinite loop */ sum = 0.0; /* reset filter sununations on each new sample */ while( iflag ); I* wait for a sample (ISR clears iflag) */ iflag = 1; /* reset iflag */

/* */ /* FIR FILTER SECTION * /

x-m[O] = input110000.0; 1* new sample input, scaled to avoid overfiow */ for (k = n; k > O; k-)

( sum = sum + hb@c]*x-mp]; x-m[kI = x-mk- 111;

1 yout = sum + hb[O]*x-m[O]; /* filter output *I channel[O] = (int) ( yout * 0.1); /* scale output */ } /* end infinite loop */

) /* end of maino */

Intempt Service Routine ******************************/

void c-intO4(void) /******************************************************************* The is the intempt semice routine for the IIOFl h t m p t . This intempt occurs on the event that the input data regs are empty. Outputs the next value for the ramp to Channel O and Channel 1 outputs.

Inputs: i: Global Variable us& as a counter.

********************************************************************/

volatile long dummy;

dummy = *DM 1-INT-STATUS; I* Clear the intempt. */

/* --- intempt service routine --- */

*DM 1-CHO-OUT-DATA = (channel[O] CC 16); dummy = *DMlCHO-IN-DATA; data-in = (double) dummy; input = data-in; *DMl-CHI-OUT-DATA = input; /* echo input to scope *1 *DM2-CHO-OUT-DATA = input; I* echo input to scope */ iflag = 0;

) /* end ISR */ /*****************************************************************/