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Design ing w ith th e UCC28600 Quasi-Res
This worksheet is designed for use with Microsoft Excel 5.0 or later. Its use is intended to a
routine, day-to-day calculations.
Component values are calculated as ideal, not to nearest production values
DisclaimerThis product is designed as an aid for customers of Texas Instruments. No war
or implied, with respect to this software or its fitness for any particular purpose is
Instruments or the author. The software is licensed solely on an "as is" basis. T
quality and performance is with the customer.
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nant Flyback Converter
ssist power supply designers in their 2005
Rev. 1.0
anties, either express
claimed by Texas
he entire risk as to its
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QR Design Tool Instructions
Be sure to Enable the Macros and to have a check in the AnalysisT oolPak box in the Add-Ins section of the Tools
uas - esonant y ac converter es gn s an terat ve process. s es gn too re uces t e ar ware
iterations by simulating the steady state operating maps that show the converter modes under different input and
load conditions. Design adjustments can be explored in order to optimize the power system. Although the design
spreadsheet is organized around a bridge rectifier bulk capacitor line rectifier, it can be used for fixed output
Power Factor Corrector (PFC) or voltage follower PFC systems. Systems with PFC must allow the QR flyback
stage to start-up under the low ac line condition. However, the steady state conduction losses to the QR flyback
stage will only occur at the PFC bulk capacitor voltage levels.
Design Tool worksheet. This step also requires an initial selection of the power MOSFET and the output rectifier.
Enter data in the cells with the BLUE text; the calculated values are in the cells with the RED text. The
parameters for the UCC28600 are already included. The design tool will generate a recommended design that
includes transformer parameters. Verify that the current and voltage stresses are compatible with the MOSFET
and output rectifier that were initially selected. The recommended values in the design may not be practical due
to integer transformer turns, standard values, etc. Yet the operation of the converter can be significantly alteredby using the closest parameter.
,
recommended by the QR Design Tool worksheet. The Magnetic Specification sheet can be printed and used as
a guideline for the recommended transformer design. The next step is to see how the design performs using the
QR Simulator worksheet.
The QR Simulator will carry over the Converter Requirements, MOSFET Specifications, Diode Data and the
UCC28600 Characteristics. The transformer information and the programming components, RS (current sense
resistance), RPL (power limit programming), ROVP1 and ROVP2 (over-voltage programming resistors) must be
entered by the user. The recommended values are shown beside the cells as a reminder for the ideal values.
After entering the final values, examine the operating maps. They reveal the boundaries of the different modes of
operation. The operating maps portray the power levels, peak switch currents, feed back voltages and switching
frequencies for the full array of line voltages and loads that the converter would experience. These maps can be
used to explore design alternatives, such as different current sense resistor values, different transformers, etc.
For example, it might be desirable to change the power level where burst mode occurs in order to avoid audio
noise at a common load operating point. The QR Simulator worksheet also shows rms currents, whether the
converter is in power limit, the operational mode among other potentially useful data that can be used to optimize
For PFC systems that have a fixed bulk voltage, estimate the PFC output voltage at the peak of its ripple.
Calculate the equivalent ac voltage to achieve that maximum voltage level. Enter that ac voltage as the VAC(max)level. Enter the minimum operational ac line voltage as the VAC(min) level because the QR Flyback must power up
correctly in order to start the PFC stage.
For voltage follower PFC systems, estimate the PFC output voltage at the peak of its ripple during maximum line
conditions. Calculate the equivalent ac voltage to achieve that maximum voltage level. Enter that ac voltage as
the VAC(max) level. Enter the minimum ac line voltage as the VAC(min) level because the QR Flyback must power up
correctly in order to start the PFC stage. In the least, converter must be designed to operate at safe temperatures
under the steady state operating rms currents that occur at the minimum PFC voltage and at the maximum PFC
voltage. The data tables in the QR Simulator worksheet can assist in finding the required values.
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menu.
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Converter Requirements
POUT(max) limit 120 W
POUT, during soft start 120 WRLOAD during
SS =4.800
efficiency ratio 0.96
PIN = 125.000 W
VAC(min) 230 VAC VBULK(min_pk) = 325.269
VAC(max) ** 264 VAC VBULK(min_valley) = 260.215
VBULK(ripple), %pp 20 % VBULK(max_pk) = 373.352
VAC(max) shutdown
margin %10 % VBULK(ov) = 410.688
fS(max), value
must be between
40kHz and 130kHz,
default value should
be 130kHz
130.0E+3Hz, high line,
max loadTS(min) = 7.692E-6
VOUT 24 VDC
VOUT(ripple), max pp 0.12 V
VOUT(shutdown) 28 V
Load step, Watts 100 W
max dVOUT due to
Load step0.5 V
Design Synthesis - type in the blue data
UCC28600
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estimated fCO, Hz 3.0E+3 Hz
VBIAS at full load 19.4 V
Snubber overshoot %
of reflected VOUT50 %
MOSFET Specifications
VDS(max) rating 650 V
VDS derate % 15 %
VDS(max) limit = 552.5 V
COSS estimate, at VDStest V
40.0E-12 F VDS test V 25
Co', F-sqrt(V) = 2.00E-10 F
CDS, stray 25.0E-12 F
CISS 1.6E-9 F
Qg 60E-9 C
Transformer Estimates
Leakage to
magnetizing
inductance %
1.5 %mag Ind
Leakage to
magnetizing
inductance ratio
=
0.015
Diode Estimates
VF 0.670 V
UCC28600 Parameters
VFB, no load 4.87 V, = VREF in chip, @ no load
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RFB 20.0E+3 W, internal to chipFB
1.4 V
ACS(FB) 2.5 Gain, VFB/VCS
VCS(OS), CS offset volts 0.4 V, typ value from data sheet
VPL, power limit 1.2 V, typical CS value during power limit
VPL - VCS(OS) 0.8 V, CS working range
VFB @ power limit 3 V, VPL X ACS(FB)
VFB at FFM boundary 2 V
fQR(max) clamp 130.0E+3 Hz
fQR(min) clamp 40.0E+3 Hz
IOVP(line) 450.0E-6 A, Line OVP typical value in data sheet
VOVP(on), ON state 0 V, typ VOVP OUT = HIGH
VOVP(load) 3.75 V, Load OVP typical value in data sheetPL(CS) OVPon),
gain during OUT = ON 0.5 150 mA/300 mA
VCS at DCM/FFM 0.4 V, (VFB/ACS(FB)) - VCS(OS)P P(max)
0.5
VCO gain, TS/VFB -28.8E-6
VCO offset, TS(VFB = 0) 65.4E-6 V
ISS(chg) 6.00E-06 A, SS charge current
Resulting Converter Features
VXFMR, reflect 119.432 V
VDS1(OS) 59.716 V
ZVS at VAC(min_valley)? FALSE
ZVS at VAC(max_pk)? FALSE
COSS @ VAC(min) 6.4E-12 F
CDS(total) @ VAC(min) 31.4E-12 F
COSS @ VAC(max) 5.2E-12 F
CDS(total) @ VAC(max) 30.2E-12 F
RLOAD, reflect to pri 114.112 W
tON / sqrt(L) 117.5E-6 s
tLEAKAGE / sqrt(L) 1.0E-6 s
tOFF / sqrt(L) 367.2E-6 s
tVALLEY / sqrt(L) 17.3E-6 s
min NPRI / NSEC 4.841 turns, N = VXFMR/(VOUT+VF)
min NPRI / NBIAS 5.989 turns, NBIAS = N*(VOUT/VBIAS)
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max L at VAC(max) 233.9E-6 H
LLEAKAGE(max) 3.5E-6 H
Total L input 237.4E-6 H
1+ROVP1/ROVP2 6.180
ROVP1 152.4E+3 W
ROVP2 29.4E+3 W
Ideal Design Using MIN NPRI / NSEC and MAX
Trial: the step numberfor the coresponding
input voltage test
condition
VBULK: the
voltage across
the bulk
capacitor,
iterations begin
at the minimum
valley voltage
VAC(equiv): the
corresponding AC input
voltage that
would result
in VBULK
ZVS ?: if
TRUE,
converter iszero voltage
switching, if
FALSE,
converter is
Valley switching
CDS, total:total drain to
source
capacitance
VBULK VAC(equiv) CDS, total
V V F
0 260.215 184.000 FALSE 37.8E-12
1 265.872 188.000 FALSE 37.6E-12
2 271.529 192.000 FALSE 37.5E-12
3 277.186 196.000 FALSE 37.3E-12
4 282.843 200.000 FALSE 37.2E-125 288.500 204.000 FALSE 37.0E-12
6 294.156 208.000 FALSE 36.9E-12
7 299.813 212.000 FALSE 36.8E-12
8 305.470 216.000 FALSE 36.7E-12
9 311.127 220.000 FALSE 36.6E-12
10 316.784 224.000 FALSE 36.5E-12
11 322.441 228.000 FALSE 36.3E-12
12 328.098 232.000 FALSE 36.2E-12
13 333.754 236.000 FALSE 36.1E-12
14 339.411 240.000 FALSE 36.0E-12
15 345.068 244.000 FALSE 35.9E-12
16 350.725 248.000 FALSE 35.8E-1217 356.382 252.000 FALSE 35.8E-12
18 362.039 256.000 FALSE 35.7E-12
19 367.696 260.000 FALSE 35.6E-12
20 373.352 264.000 FALSE 35.5E-12
At VAC(min) IP1 3.160A
Summary of Maxi
ZVS ?Trial
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ICS1 143E-6A
At VAC(max) IP2 2.876A
ICS2 205E-6A
RS and RPL Values to Achieve IP and ICS
RCS 0.210 W VRcs, peak 0.663
RPL
960.18E+0W
VRpl
, min line 0.137
Snubber Components and Parameters, Primary-Side Voltage Clamping
CSNUB 1.628E-9 F
TSNUB 169.02E-9 s
RSNUB1 11.63E+3 W PRsnub1 2.019
RSNUB2 46.423 W
Output Capacitor
COUT 2.78E-3 F
ESR, max 7.84E-3 W
IC(out), rms @ low line 5.165A
IC(out), rms @ high line 4.694A
Soft Start
always no-load start? FALSE
tSS, minimum 21.26E-3 s
CSS, minimum 63.77E-9 F
Summary of Ideal Converter Components
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Xfmr LPRI(terminal) 237.4E-6 H
LPRI(leakage) 3.5E-6 H
NPRI/NSEC 4.841 turns ratio
IPRI(rms) 1.006ARMS
IPRI(peak) 3.160APEAK
ISEC(rms) @ low
line7.189
ARMS, for non-
PFC design
ISEC(rms) @ high
line6.858
ARMS, for PFC
design
MOSFET VDS rating 650 V
VDS stress 552.5 V
ID(rms) 1.006A
Output capacitor COUT 2.8E-3 F
ESR, max 7.8E-3 Wrms current
rating @ low line5.165ARMS
rms current
rating @ high
line
4.694ARMS
Output Diode VF 0.67 V
IAVERAGE 5.000A
IRMS 7.189A
IPEAK 15.298A
PDISSIPATE 3.350 W
VBLOCK 101.120 V
R current sense RCS 209.8E-3 Wmaximum power 0.319 W
R power limit RPL 960.2E+0 W
R2CD snubber CSNUB 1.6E-9 F
RSNUB1 11.6E+3 W
PRsnub1 2.019 W
RSNUB2 46.423 W
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OVP ROVP1 152.4E+3 W
ROVP2 29.4E+3 W
Soft start CSS 63.8E-9 FtSS 21.3E-3 s
Minimum VDD
CapacitorCVDD 51.6E-6 F
Series resistor RVDD 11.13 W
Start up resistor RSU 10.4E+6 W
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W, VOUT2/POUT during SS
V, VAC(min)2
V, minus ripple
V, VAC(max)2
V, plus ripple
s
ALL CELLS WITH BLUE TEXT MUST BE VERI
UPDATED BY THE USER FOR EACH DES
- VBULK(ripple), %pp is the ripple voltage on the input voltage (enter the
peak to peak ripple voltage on the input bus in cell C16)
- VAC(max) shutdown margin % is the User programmable Line Over V
Protection limit (enter the percentage of margin that the line voltage ca
VAC(max) before initiating Line OVP, in cell C17)
- For systems that wish to utilize the full range of the controller, most
130E+3 (for the 130kHz max switching frequency of the UCC2860
C18; for designs that do not wish to use the full range of modes, enter
than 130kHz but greater than 40kHz (default value entered into cell
be 130E+3). Enter frequency, in Hertz, in cell C18.
- VOUT is the regulated output voltage of the converter (enter, in Volts, i
- VOUT(ripple), max pp is the maximum peak to peak output ripple of the
output, i.e. usually equal to 1% of the regulated output voltage (enter, i
C20)
- VOUT(shutdown) is the User programmable Output Over Voltage Protecti
in Volts, the maximum output voltage that will initiate Load OVP in cell
- Load step is the maximum output load transient, in Watts, i.e. no-loa
(enter, in Watts, in cell C22)
- max dVOUT due to Load step is the maximum output voltage deviati
transient or load step (enter, in Volts, in cell C23)
and the spreadsheet responds with the calculated red data.
Design Spreadsheet
- POUT(max) limit is maximum output power of converter (enter, in W, in
- POUT during SS, default: use POUT(max) if design will start into full load
into cell C11)
- efficiency ratio is the Expected converter efficiency (enter, in decim
C12)
- Resultant input power from User input (calculated by spreadsheet)
Comments on REQUIRED USER INPUTS:
- VAC(min) is the minimum AC line input voltage (enter, in VAC, in cell C- **For systems with a PFC front end, the VAC(max) value entered in
should be equivalent to the maximum regulated output voltage o
stage divided by SQRT(2), as calculated by the USER, otherwise,
that DO NOT have a PFC input stage, enter the maximum AC line
voltage. (enter, in VAC, in cell C15)
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V
- Leakage to magnetizing inductance % is the desired magnetizing i
the Flyback transformer (enter, as a percent, in cell C39)
- VF is the forward voltage drop of the User-selected output rectifier as
rectifier data sheet (enter, as a voltage, in cell C43)
- VDS derate % is the User chosen derating (for safety margin) of the
the FET (enter, as a percentage, in cell C31)
- Resultant maximum allowed voltage on switch due to User selected
- COSS is the output capacitance of the chosen MOSFET as stated in t
data sheet (enter, in Farads, in cell C33). VDS test V is the defined vol
the MOSFET data sheet, that the COSS specification is tested at (enter,
cell F33).
- CDS, stray is the estimated parasitic Drain to Source capacitance (e
Farads, in cell C35) ex.TO-220 tab to GND is about 25 pF
- Qg is the total gate charge of the chosen MOSFET as stated in the M
sheet (enter, in Cou;ombs, in cell C37).
- CISS is the input capacitance of the chosen MOSFET as stated in the
data sheet (enter, in Farads, in cell C36).
- VDS(max) rating is the chosen FET's drain to Source maximum voltag
as Volts, in cell C30)
- VBIAS is the output of the Aux winding of the Flyback Transformer, us
UCC28600 and, if used, also the PFC controller. VBIAS must be equal t
maximum UVLO stop threshold of the UCC28600 (equal to 9.3V) or th
start up voltage of the PFC controller, whichever is greater. (enter, inC25)
- Snubber overshoot % of reflected VOUT is used to determine the s
components. The percentage value entered in this cell will be used to
clamp voltage, taking into account the derated VDS of the switch, the m
voltage, and the reflected output voltage. Recommended 50% as defa
(enter, as a percentage, in cell C26)
- estimated fCO is the desired crossover frequency of the control loop,
between 2kHz and 3kHz (enter, in Hertz such as 3.0E+3, in cell C24)
The User selects a MOSFET for the design and inputs the FET's
characteristics:
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- calculated Drain-Source overshoot voltage
- TRUE only if VXFMR,reflect > VBULK(min_valley), FALSE = valley switchin
- TRUE only if VXFMR,reflect > VBULK(max_pk), FALSE = valley switching
- calaculated circuit capacitances
Note: RS and RPLand the snubber follow simulation because the result
their calculation.
- calculated allowable reflected output voltage
- The parameters within the blue box are internal to the UCC28600 an
programmable.
- min NPRI / NBIAS is the Minimum Turns Ratio for the Primary to Bi
Windings (this value is inverted and carried over to the Simulator pag
Internal IC
parameters
- calculated maximum load impedance based upon the reflected outpu
- calculated timing segments normalized with respect to the primary in
- min NPRI / NSEC is the Minimum Turns Ratio for the Primary to Se
Windings (this value is carried over to the Simulator page)
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over VAC Range @ MAX LoadIPEAK:
calculated
peak primary
current at
maximum load
taking into
account
operating
mode
TON:
calculated on
time at
maximum
load
TS: calculated
switching
period at
maximum
load
IPRI(rms): primary
side rms current
TDEMAG: time
required for the
inductor to
demagnetize at
maximum load
ISEC(rms):
secondary
side rms
current at
maximum load
IPEAK TON TS IPRI(rms) TDEMAG ISEC(rms)
A s s A, rms s A, rms
3.160 2.841E-6 9.344E-6 1.006 6.190E-6 7.19
3.140 2.763E-6 9.226E-6 0.992 6.151E-6 7.17
3.121 2.689E-6 9.114E-6 0.979 6.113E-6 7.14
3.103 2.619E-6 9.008E-6 0.966 6.077E-6 7.12
3.085 2.552E-6 8.906E-6 0.953 6.043E-6 7.103.068 2.488E-6 8.808E-6 0.941 6.010E-6 7.08
3.052 2.427E-6 8.715E-6 0.930 5.978E-6 7.06
3.036 2.369E-6 8.626E-6 0.919 5.947E-6 7.05
3.021 2.314E-6 8.541E-6 0.908 5.918E-6 7.03
3.007 2.261E-6 8.459E-6 0.897 5.889E-6 7.01
2.993 2.210E-6 8.381E-6 0.887 5.862E-6 7.00
2.979 2.162E-6 8.306E-6 0.877 5.836E-6 6.98
2.966 2.115E-6 8.233E-6 0.868 5.810E-6 6.96
2.954 2.070E-6 8.164E-6 0.859 5.785E-6 6.95
2.941 2.027E-6 8.097E-6 0.850 5.762E-6 6.94
2.930 1.986E-6 8.032E-6 0.841 5.739E-6 6.92
2.918 1.947E-6 7.970E-6 0.833 5.716E-6 6.912.907 1.908E-6 7.910E-6 0.825 5.695E-6 6.90
2.897 1.872E-6 7.852E-6 0.817 5.674E-6 6.88
2.886 1.836E-6 7.796E-6 0.809 5.654E-6 6.87
2.876 1.802E-6 7.742E-6 0.801 5.634E-6 6.86
- ROVP2 is the ideal value of the bottom resistor on the OVP pin (thi
adjusted for actual turns ratio and carried over to the Simulator page)
um Load at Minimum and Maximum Line
- ROVP1 is the ideal value of the top resistor on the OVP pin (this val
for actual turns ratio and carried over to the Simulator page)
- max L at VAC(max) is the Calculated Primary Inductance (this val
over to the Simulator page)
- LLEAKAGE(max) is the Allowable Leakage Inductance (this value is car
the Simulator page)
- IP1 is the peak primary current at low line, full load
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V PRcs 0.319 W
V VRpl
, max line 0.196 V
W
- Select a capacitor bank (COUT) to handle IC(out),rms at high line.
- CSS, minimum is the rewquired capacitor fo SS. Select astandard value close to this.
- tSS, minimum is the required soft start time
- Select a capacitor bank (COUT) to handle IC(out),rms at low line.
- COUT is the ideal value of the output capacitor. Select a standard value close to this.
- the ideal value of the Power Limit
(RPL), the peak voltage across it at
(VRpl, min line), and the peak volta
maximum line (VRpl, max line). RPfor actual turns ratio and carried ov
Simulator page where the User mu
standard value.
- IP2 is the peak primary current at high line, full load
- ICS2 is the power limit current that is sourceed at the CS pin at high line
- the ideal value of the Current Sen
(RCS), the peak voltage across it (V
and the power dissipated by it (PRc
adjusted for actual turns ratio and c
the QR Simulator page where the
select a standard value.
- RSNUB1 is the ideal value of the snubber resistor that is in parallel to CSNUB, PRsnub1 is
dissipation of RSNUB1. Select a standard value close to this.
- TSNUB is the period of the ringing frequency
- CSNUB is the ideal value of the primary side snubber capacitor. Select a standard val
this.
- ICS1 is the power limit current that is sourceed at the CS pin at low line
- RSNUB2 is the ideal value of the snubber resistor that is in series with CSNUB. Select a
value close to this.
- Select a capacitor bank (COUT) with a total ESR less than this.
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- LPRI(terminal) is the required primary inductance. LPRI is carried over to the QR Simulat
the User must select a standard value.
- LPRI(leakage) is the maximum allowable leakage inductance. LPRI(leakage) is carried over
Simulator page where the User must select a standard value.
- NPRI/NSEC is the ideal primary to secondary turns ratio. NPRI/NSEC is carried over to th
Simulator page where the User must enter the actual turns used.
- IPRI(rms)is the primary rms current at low line, maximum load
- VDSstress is the resultant maximum allowed voltage on switch due to User selected
- ISEC(rms)@high lineis the maximum secondary side rms current at high line for desig
front end
- ID(rms) is the maximum primary rms current
- ISEC(rms)@ low lineis the maximum secondary side rms current at low line for design
PFC front end
- VDS rating is the voltage rating on the User selected MOSFET
- IPRI(peak)is the peak primary current at low line, maximum load
- VBLOCK is the required reverse voltage rating of the diode
- RCS is the ideal value of the Current Sense resistor
- maximum poweris the calculated dissipated power across the current sense resist
- IRMS is the RMS output current
- ESR, max is the maximum allowable equivalent series resitance of the output capa
- rms current rating at low line is the required rms ripple current rating for low line o
designs that do not use a PFC front end
- rms current rating at high line is the required rms ripple current rating for low line
designs that use a PFC front end
- COUT is the ideal value of the output capacitor. Select a standard value close to this.
- VF is the forward voltage drop of the selected diode
- IAVERAGE is the average output current
- PDISSIPATE is the calculated power dissipation of the output diode
- IPEAK is the PEAK output current
- RSNUB1 is the ideal value of the snubber resistor that is in parallel to CSNUB, Select a
close to this.
- RSNUB2 is the ideal value of the snubber resistor that is in series with CSNUB. Select a
value close to this.
- PRsnub1 is the power dissipation of RSNUB1.
- RPL is the ideal value of the power limit resistor
- CSNUB is the ideal value of the primary side snubber capacitor. Select a standard valthis.
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- RSU is the start up resistor from the bulk input into VDD
- RVDD is the series resistor from the Bias windings into VDD
- tSS, minimum is the required soft start time
- ROVP1 is the ideal value of the top resistor on the OVP pin
- ROVP2 is the ideal value of the bottom resistor on the OVP pin
- CVDD is the minimum required value for the bulk capacitor on VDD
- CSS, minimum is the required capacitor fo SS. Select astandard value close to this.
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IED AND
IGN.
ercentage of
oltage
n exceed
esigns, enter
) into cell
a value less
C18 should
n cell C19)
converter
Volts, in cell
on limit (enter,
C21)
d to full load
n due to a
o cell C10)
(enter, in W,
l form, in cell
4)o cell C15
the PFC
or systems
input
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nductance of
found in the
DS voltage on
erating
e MOSFET
age, found in
in Volts, in
ter, in
OSFET data
MOSFET
rating (enter,
d to BIAS the
the
e maximum
olts, in cell
ubber
determine the
aximum input
lt value.
usually
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s are used in
are not User
s (AUX)
)
t voltage
uctance
ondary
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D: duty cycle
0.304
0.299
0.295
0.291
0.2870.282
0.278
0.275
0.271
0.267
0.264
0.260
0.257
0.254
0.250
0.247
0.2440.241
0.238
0.236
0.233
value is
D
ue is adjusted
e is carried
ried over to
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Resistor
minimum line
e across it at
is adjustedr to the QR
t select a
e resistor
Rcs, peak),
). RCS is
arried over to
ser must
the power
e close to
tandard
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r page where
to the QR
e QR
derating
ns with a PFC
without a
r
itor bank
peration of
peration of
tandard value
tandard
e close to
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Converter Requirements:POUT 120 W
POUT, during soft start 120 W RLOAD during SS 4.800
Efficiency ratio 0.96
PIN 125.000 W
VAC(min) 230 VAC VBULK(min_pk) 325.269
VAC(max) 264 VAC VBULK(min_valley) 260.215
VBULK(ripple), %pp 20 % VBULK(max_pk) 373.352
VAC(max) shutdown margin % 10 % VBULK(shutdown) 410.688
fS(max) 130.0E+3 Hz TS(min) 7.69E-06
VOUT 24 V
VOUT(ripple), max pp 0.12 V
VOUT, shut-down 28 V
Load step, Watts 100 W
max dVOUT due to load step 0.5 V
estimated fCO, Hz 3.0E+3 Hz
VBIAS at full load 19.4 V
Snubber overshoot % of reflectedVOUT
50 %
MOSFET Specifications:VDS(max) rating 650 V
VDS derate % 15 % Actual derating % 21.003
VDS(max) limit 552.5 V
COSS estimate, at VDS = 25 V 40.0E-12 F VDS test V 25
Co', F-sqrt(V) 200.0E-12 F
CDS, stray 25.0E-12 F
Diode Data:VF 0.670 V
Transformer Data
UCC28600 An
Design Simulation - type in the blueNote: The converter requirements and recommended component values have been c
TYPE IN STANDARD COMPONENT VALUES IN THE BLUE CEMOD
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Actual Leakage to magnetizing
inductance % (from magnetic
manufacturer's drawing spec)
2.5 %
Leakage to
magnetizing
inductance ratio
0.025
Actual LM (from magnetic
manufacturer's drawing spec).
The recommended primaryinductance is shown in cell E42,
carried over from the QR Design
page.
300.0E-6 H
Recommended LMcarried over from
QR Design page
and shown for theUser's
convenience in
cell E42
233.9E-6
LLEAKAGE 7.5E-6 H
Total L, primary 307.5E-6 H
NPRI/NSEC (from magnetic
manufacturer's drawing spec)5.680 turns ratio 4.841
VXFMR, reflect 140.126 VRecommended
VXFMR, reflect119.4
NPRI/NBIAS 4.000 5.989
Sense Resistors & Power Limit
Recommended values, carried over
from the QR Design Tool page andadjusted for the actual turns ratio are
shown in cells D54 through D57. The
User must insert the closest standard
value for each component in cells B54
through B57, iterating until the
recommended values no longer self-
adjust (usually 2-3 iterations are all
that are needed)
Input the actual Primary to Secondary Turns Ratio, from the magnetic manufacturer's drawing spec, into cell
B47. This value should very closely match the recommended turns ratio calculated on the QR Design Tool
sheet and shown for the User's convenience in cell E47 of this sheet.
Input the actual Primary to Bias Turns Ratio, from the magnetic manufacturer's drawing spec, into cell B50.
This value should very closely match the recommended turns ratio calculated on the QR Design Tool sheet
and shown, for the User's convenience, in cell E50 of this sheet.
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RCS, current sense 0.350 W 0.229 WRPL, power limit 1.40E+03 W 6.08E+02 WROVP1 133.0E+3 W 228.2E+3 WROVP2 29.4E+3 W 23.1E+3 W
UCC28600 Parameters
VFB, no load 4.87 V, = VREF in chip, @ no load
RFB 20.0E+3 W, internal to chipVFB at Burst/FFM boundary 1.4 V
ACS(FB) 2.5 Gain, VFB/VCSVCS OS , CS offset volts 0.4 V, typ value from data sheet
VPL, power limit 1.2 V, typical CS value during power limit
VPL - VCS(OS) 0.8 V, CS working range
VFB @ power limit 3 V, VPL X ACS(FB)
VFB at FFM boundary 2 V
fQR(max) clamp 130.0E+3 Hz
fQR(min) clamp 40.0E+3 Hz
IOVP(line) 450.0E-6 A, Line OVP typical value in data sheet
VOVP(on), ON state 0 V, typ VOVP OUT = HIGH
VOVP(load) 3.75 V, Load OVP typical value in data sheet
IPL(CS)/IOVPon), current gain during
OUT = ON state0.5 150 mA/300 mA
VCS at DCM/FFM 0.4 V, (VFB/ACS(FB)) - VCS(OS)IP/IP(max) at DCM/FFB boundary 0.5VCO gain, TS/VFB -28.8E-6
VCO offset, TS(VFB = 0) 65.4E-6 V
ISS(chg) 6.00E-06 A, SS charge current
VBULK VAC, equiv. IP, actual
V V A
Recommended with Turns ADJ 0 260.215 184.000 2.848
20 373.352 264.000 2.565
Actual with Real Values 0 260.215 184.000 2.8481 265.872 188.000 2.828
2 271.529 192.000 2.809
3 277.186 196.000 2.791
4 282.843 200.000 2.773
5 288.500 204.000 2.756
6 294.156 208.000 2.740
7 299.813 212.000 2.724
8 305.470 216.000 2.709
Operation Cha
Trial
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9 311.127 220.000 2.695
10 316.784 224.000 2.681
11 322.441 228.000 2.668
12 328.098 232.000 2.655
13 333.754 236.000 2.642
14 339.411 240.000 2.630
15 345.068 244.000 2.61816 350.725 248.000 2.607
17 356.382 252.000 2.596
18 362.039 256.000 2.585
19 367.696 260.000 2.575
20 373.352 264.000 2.565
Min line 260.215 184.000 2.848
Max line 373.352 264.000 2.565
VBULK(min) 260.215 V Vac, equiv
Pload PLINEW W
1 120 125.000 QR
0.95 114 118.750 QR
0.9 108 112.500 QR
0.85 102 106.250 QR
0.8 96 100.000 QR
0.75 90 93.750 DCM
0.7 84 87.500 DCM
0.65 78 81.250 DCM0.6 72 75.000 DCM
0.55 66 68.750 DCM
0.5 60 62.500 DCM
0.45 54 56.250 DCM
0.4 48 50.000 DCM
0.35 42 43.750 DCM
0.3 36 37.500 DCM
0.25 30 31.250 DCM
0.2 24 25.000 DCM
0.15 18 18.750 DCM
0.1 12 12.500 DCM
0.05 6 6.250 DCM0.01 1.2 1.250 DCM
VBULK(min) 373.3523805 V VAC, equiv
ModePLOAD/PRATED
Operation Characteristi
Operation Characteristi
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Pload PLINE
W W
1 120 125.000 QR
0.95 114 118.750 QR
0.9 108 112.500 DCM
0.85 102 106.250 DCM
0.8 96 100.000 DCM0.75 90 93.750 DCM
0.7 84 87.500 DCM
0.65 78 81.250 DCM
0.6 72 75.000 DCM
0.55 66 68.750 DCM
0.5 60 62.500 DCM
0.45 54 56.250 DCM
0.4 48 50.000 DCM
0.35 42 43.750 DCM
0.3 36 37.500 DCM
0.25 30 31.250 DCM
0.2 24 25.000 DCM0.15 18 18.750 DCM
0.1 12 12.500 DCM
0.05 6 6.250 DCM
0.01 1.2 1.250 FFB
VBULK fS PIN(limit)
V Hz W
0 260.215 209.1E+3 54.963
1 265.872 213.8E+3 54.379
2 271.529 218.6E+3 53.7703 277.186 223.4E+3 53.137
4 282.843 228.4E+3 52.482
5 288.500 233.5E+3 51.804
6 294.156 238.8E+3 51.105
7 299.813 244.1E+3 50.386
8 305.470 249.6E+3 49.648
9 311.127 255.3E+3 48.890
10 316.784 261.1E+3 48.115
11 322.441 267.1E+3 47.323
12 328.098 273.2E+3 46.514
13 333.754 279.6E+3 45.689
14 339.411 286.1E+3 44.849
15 345.068 292.9E+3 43.994
16 350.725 299.8E+3 43.124
17 356.382 307.0E+3 42.241
18 362.039 314.5E+3 41.345
19 367.696 322.2E+3 40.436
20 373.352 330.3E+3 39.514
Trial
PLOAD/PRATED Mode
Actual Power Limit, as Programmed by Actual RPL,
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W
V
V
V
V
s
%
V
lysis Spreadsheet
data and it responds with the red data.rried over from the QR Designer Tool page and are shown in RED. The U
LS FOR THE SIMULATOR TO GENERATE THE DESIGN SCHARTS
1.5
2.0
2.5
3.0
rimaryCurrent-A
Primary Current vs Switching Freq
0
20
40
60
80
100
120
140
0 20 40 60 80
PIN-InputPower
-W
fS - Switching Frequency - kHz
Input Power vs Switching Frequ
Input Low Line Input High Line
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H
Recommended
NPRI/NSEC turns
ratio
V
Recommended
NPRI/NBIAS turns
ratio
In regards to the above Mode Plots: The green shaded region represents th
where the controller applies packets of 40kHz pulses to the MOSFET gate.
the average switching frequency of the 40kHz packets of pulses while in thi
transition from Green mode into Frequency Foldback mode (FFM) at approxim
increasing load, the converter will either operate in Discontinuous Mode (DCM)
be fixed at 130kHz, or transition directly into Quasi-Resonant mode (QR) wh
with increasing load. Due to the limitaions of this QR Simulator spreadsh
0.0
0.5
1.0
0 20 40 60 80 1
IP-P
fS - Switching Frequency - kHz
Rated Power Input Low Line Input High Line
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0 20 40 60 80 1
V
FB-FeedbackVoltage-V
fS - Switching Frequency - kHz
Feedback Voltage vs Switching Frequ
Rated Power Input Low Line Inpu
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TS, actual TON, actual f S, actual VFB
s s Hz V
9.976E-6 3.365E-6 100.2E+3 FALSE 2.845
8.094E-6 2.113E-6 123.6E+3 FALSE 2.777
9.976E-6 3.365E-6 100.2E+3 TRUE 4.3489.837E-6 3.271E-6 101.7E+3 TRUE 4.349
9.705E-6 3.181E-6 103.0E+3 TRUE 4.351
9.579E-6 3.096E-6 104.4E+3 TRUE 4.354
9.459E-6 3.015E-6 105.7E+3 TRUE 4.357
9.344E-6 2.938E-6 107.0E+3 TRUE 4.361
9.235E-6 2.864E-6 108.3E+3 TRUE 4.365
9.130E-6 2.794E-6 109.5E+3 TRUE 4.370
9.030E-6 2.727E-6 110.7E+3 TRUE 4.376
acteristics of Design Using LM and LLEAK at Full Rated Power
accurately show the internal 40kHz clamp of Quasi-Resonant operation. As s
frequency hits the internal 40kHz minimum frequency clamp, the operating fre
increasing load, dependent upon line and load condi
Power Limit?
fsw FFM (VS)
fMAX
= Oscillator
Frequency
(130 kHz)
fQR_MIN
:
internally limited to
40 kHz.
QR Mode
(Valley
Switching)
Switching
Frequency
VFB
Feedback
Voltage
SS Mode
(fixed fSW
)
fSS
(40kHz)
f
DCM(maximum fs)
Hysteretic
transition into
Burst Mode.
IC Off Softstart Regular Operation Frequency Foldback
Load Shown is slightly less
than Over Current Threshold
Fixed Frequency
POUT
LoadPower
VSTATUS
Status,pulledup
toVDD
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8.934E-6 2.664E-6 111.9E+3 TRUE 4.382
8.842E-6 2.603E-6 113.1E+3 TRUE 4.388
8.753E-6 2.544E-6 114.2E+3 TRUE 4.395
8.668E-6 2.488E-6 115.4E+3 TRUE 4.402
8.587E-6 2.434E-6 116.5E+3 TRUE 4.410
8.508E-6 2.383E-6 117.5E+3 TRUE 4.418
8.433E-6 2.333E-6 118.6E+3 TRUE 4.4268.360E-6 2.286E-6 119.6E+3 TRUE 4.435
8.290E-6 2.240E-6 120.6E+3 TRUE 4.444
8.222E-6 2.196E-6 121.6E+3 TRUE 4.453
8.157E-6 2.154E-6 122.6E+3 TRUE 4.463
8.094E-6 2.113E-6 123.6E+3 TRUE 4.473
9.976E-6 3.365E-6 100.2E+3 TRUE 4.348
8.094E-6 2.113E-6 123.6E+3 TRUE 4.473
184 V
IP actual f S actual TON VCS VFBA Hz s V V
2.848 100.2E+3 3.365E-6 1.339 4.348
2.711 105.1E+3 3.203E-6 1.291 4.228
2.573 110.5E+3 3.041E-6 1.243 4.108
2.436 116.5E+3 2.878E-6 1.195 3.987
2.298 123.1E+3 2.716E-6 1.147 3.867
2.166 130.0E+3 2.559E-6 1.100 3.751
2.092 130.0E+3 2.473E-6 1.075 3.687
2.016 130.0E+3 2.383E-6 1.048 3.6201.937 130.0E+3 2.289E-6 1.020 3.551
1.855 130.0E+3 2.192E-6 0.992 3.479
1.768 130.0E+3 2.090E-6 0.961 3.403
1.678 130.0E+3 1.982E-6 0.930 3.324
1.582 130.0E+3 1.869E-6 0.896 3.240
1.479 130.0E+3 1.748E-6 0.860 3.151
1.370 130.0E+3 1.619E-6 0.822 3.054
1.250 130.0E+3 1.478E-6 0.780 2.950
1.118 130.0E+3 1.322E-6 0.734 2.835
0.969 130.0E+3 1.145E-6 0.681 2.703
0.791 130.0E+3 934.519E-9 0.619 2.548
0.559 130.0E+3 660.805E-9 0.538 2.3450.250 130.0E+3 295.521E-9 0.430 2.075
264 V
s of Design Using LM and LLEAK at High Line
s of Design using LM and LLEAK at Low Line
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IP actual f S actual TON VCS VFB
A Hz s V V
2.565 123.6E+3 2.113E-6 1.389 4.473
2.442 129.5E+3 2.012E-6 1.346 4.365
2.372 130.0E+3 1.954E-6 1.322 4.304
2.306 130.0E+3 1.899E-6 1.298 4.246
2.237 130.0E+3 1.842E-6 1.274 4.1852.166 130.0E+3 1.784E-6 1.249 4.123
2.092 130.0E+3 1.723E-6 1.224 4.059
2.016 130.0E+3 1.661E-6 1.197 3.992
1.937 130.0E+3 1.595E-6 1.169 3.923
1.855 130.0E+3 1.528E-6 1.140 3.851
1.768 130.0E+3 1.456E-6 1.110 3.775
1.678 130.0E+3 1.382E-6 1.078 3.696
1.582 130.0E+3 1.303E-6 1.045 3.612
1.479 130.0E+3 1.219E-6 1.009 3.523
1.370 130.0E+3 1.128E-6 0.971 3.427
1.250 130.0E+3 1.030E-6 0.929 3.322
1.118 130.0E+3 921.122E-9 0.883 3.2070.969 130.0E+3 797.715E-9 0.830 3.076
0.791 130.0E+3 651.331E-9 0.768 2.920
0.559 130.0E+3 460.561E-9 0.687 2.717
-0.261 119.6E+3 -214.737E-9 0.400 1.977
IPRI(rms) ISEC(rms)
ARMS ARMS
0.429 3.321
0.419 3.277
0.409 3.2310.399 3.185
0.389 3.138
0.379 3.090
0.370 3.042
0.360 2.993
0.351 2.944
0.342 2.894
0.333 2.843
0.324 2.792
0.315 2.741
0.307 2.689
0.298 2.636
0.290 2.584
0.282 2.530
0.273 2.477
0.265 2.422
0.257 2.368
0.249 2.313
OVP1 & ROVP2 Values
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SER MUST
PECIFIC
uency
100 120 140
ency
Power Limit
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fs, actual (kHz)
for Rated P
map 1, 2, 3
fs, actual (kHz) for
Input Low Line Map
1, 2, 3
fs, actual
(kHz) for
Input High
Line Map 1,
2, 3
e Green Mode area of operation
he frequency shown is actually
region. Ideally, a design will
ately 10% load. From FFM, with
at which point the frequency will
re the frequency will decrease
et. the Mode plots do NOT
00 120 140
Power Limit
00 120 140
ency
t High Line
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100 100 124
102 105 129
103 111 130
104 116 130
106 123 130
107 130 130
108 130 130
110 130 130
111 130 130
112 130 130
113 130 130
114 130 130
115 130 130
116 130 130
118 130 130
119 130 130
120 130 130
121 130 130
122 130 130
123 130 130
124 130 120
IPRI(rms) ISEC(rms) resonant leakage resonant
ARMS ARMS ZVS ? CDS, total time TL1=Tr / (2pi) f, reset, Hz
0.955 7.392 FALSE 3.792E-11 1.686E-08 1.474E+06
0.757 7.015 FALSE 3.555E-11 1.633E-08 1.522E+06
0.955 7.392 FALSE 3.792E-11 1.686E-08 1.474E+060.941 7.366 FALSE 3.775E-11 1.683E-08 1.477E+06
0.928 7.341 FALSE 3.760E-11 1.679E-08 1.480E+06
0.916 7.317 FALSE 3.745E-11 1.676E-08 1.483E+06
0.904 7.294 FALSE 3.730E-11 1.673E-08 1.486E+06
0.892 7.272 FALSE 3.716E-11 1.670E-08 1.489E+06
0.881 7.251 FALSE 3.703E-11 1.667E-08 1.491E+06
0.870 7.230 FALSE 3.690E-11 1.664E-08 1.494E+06
0.860 7.210 FALSE 3.678E-11 1.661E-08 1.497E+06
hown below, once the switching
uency will begin to increase with
itions.
Green Mode
t
t
GRMODE_MX
(40 kHz)
This mode applies bursts
of 40kHz soft-start pulses
to the power MOSFET
gate. The average fsw is
shown in this operating
mode.
Green Modet
t
Green Mode,PFC bias OFF
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0.850 7.191 FALSE 3.666E-11 1.658E-08 1.499E+06
0.840 7.172 FALSE 3.654E-11 1.655E-08 1.501E+06
0.830 7.154 FALSE 3.643E-11 1.653E-08 1.504E+06
0.821 7.137 FALSE 3.632E-11 1.650E-08 1.506E+06
0.812 7.120 FALSE 3.621E-11 1.648E-08 1.508E+06
0.804 7.104 FALSE 3.611E-11 1.646E-08 1.510E+06
0.795 7.088 FALSE 3.601E-11 1.643E-08 1.513E+060.787 7.072 FALSE 3.591E-11 1.641E-08 1.515E+06
0.779 7.058 FALSE 3.581E-11 1.639E-08 1.517E+06
0.771 7.043 FALSE 3.572E-11 1.637E-08 1.519E+06
0.764 7.029 FALSE 3.563E-11 1.635E-08 1.520E+06
0.757 7.015 FALSE 3.555E-11 1.633E-08 1.522E+06
0.955 7.392 FALSE 3.792E-11 1.686E-08 1.474E+06
0.757 7.015 FALSE 3.555E-11 1.633E-08 1.522E+06
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fs, actual (kHz) for
Power Limit Map
1, 2
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209
214
219
223
228
234
239
244
250
255
261
267
273
280
286
293
300
307
315
322
330
TR, dMAG(valley) residue dMAG(l) VV, valley VDS
seconds Amps Volts TZV IP1 TS1 TL2
3.392E-07 0.000E+00 1.201E+02 0.000E+00 2.745E+00 9.267E-06 5.530E-09
3.284E-07 0.000E+00 2.332E+02 0.000E+00 2.454E+00 7.406E-06 7.438E-09
3.392E-07 0.000E+00 1.201E+02 0.000E+00 2.745E+00 9.267E-06 5.530E-093.385E-07 0.000E+00 1.257E+02 0.000E+00 2.724E+00 9.130E-06 5.626E-09
3.378E-07 0.000E+00 1.314E+02 0.000E+00 2.705E+00 8.999E-06 5.722E-09
3.371E-07 0.000E+00 1.371E+02 0.000E+00 2.686E+00 8.874E-06 5.818E-09
3.365E-07 0.000E+00 1.427E+02 0.000E+00 2.668E+00 8.755E-06 5.914E-09
3.358E-07 0.000E+00 1.484E+02 0.000E+00 2.651E+00 8.642E-06 6.010E-09
3.352E-07 0.000E+00 1.540E+02 0.000E+00 2.634E+00 8.534E-06 6.105E-09
3.346E-07 0.000E+00 1.597E+02 0.000E+00 2.618E+00 8.430E-06 6.201E-09
3.341E-07 0.000E+00 1.653E+02 0.000E+00 2.603E+00 8.331E-06 6.297E-09
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3.335E-07 0.000E+00 1.710E+02 0.000E+00 2.588E+00 8.236E-06 6.392E-09
3.330E-07 0.000E+00 1.767E+02 0.000E+00 2.573E+00 8.145E-06 6.488E-09
3.325E-07 0.000E+00 1.823E+02 0.000E+00 2.559E+00 8.057E-06 6.583E-09
3.320E-07 0.000E+00 1.880E+02 0.000E+00 2.546E+00 7.974E-06 6.678E-09
3.315E-07 0.000E+00 1.936E+02 0.000E+00 2.533E+00 7.893E-06 6.774E-09
3.310E-07 0.000E+00 1.993E+02 0.000E+00 2.521E+00 7.815E-06 6.869E-09
3.306E-07 0.000E+00 2.049E+02 0.000E+00 2.509E+00 7.741E-06 6.964E-093.301E-07 0.000E+00 2.106E+02 0.000E+00 2.497E+00 7.669E-06 7.059E-09
3.297E-07 0.000E+00 2.163E+02 0.000E+00 2.486E+00 7.599E-06 7.154E-09
3.293E-07 0.000E+00 2.219E+02 0.000E+00 2.475E+00 7.532E-06 7.249E-09
3.288E-07 0.000E+00 2.276E+02 0.000E+00 2.464E+00 7.468E-06 7.344E-09
3.284E-07 0.000E+00 2.332E+02 0.000E+00 2.454E+00 7.406E-06 7.438E-09
3.392E-07 0.000E+00 1.201E+02 0.000E+00 2.745E+00 9.267E-06 5.530E-09
3.284E-07 0.000E+00 2.332E+02 0.000E+00 2.454E+00 7.406E-06 7.438E-09
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TE1 IP2 a b c d TD(mag) D1, actual
9.629E-06 2.923E+00 1.230E-06 -3.376E-06 -3.561E-07 -1.518E-08 6.250E-06 3.373E-01
7.758E-06 2.635E+00 1.230E-06 -3.018E-06 -3.448E-07 -1.825E-08 5.629E-06 2.610E-01
9.629E-06 2.923E+00 1.230E-06 -3.376E-06 -3.561E-07 -1.518E-08 6.250E-06 3.373E-019.491E-06 2.903E+00 1.230E-06 -3.351E-06 -3.553E-07 -1.533E-08 6.206E-06 3.325E-01
9.359E-06 2.883E+00 1.230E-06 -3.327E-06 -3.546E-07 -1.548E-08 6.164E-06 3.278E-01
9.234E-06 2.865E+00 1.230E-06 -3.304E-06 -3.539E-07 -1.563E-08 6.124E-06 3.232E-01
9.115E-06 2.847E+00 1.230E-06 -3.282E-06 -3.532E-07 -1.578E-08 6.086E-06 3.187E-01
9.001E-06 2.830E+00 1.230E-06 -3.260E-06 -3.525E-07 -1.593E-08 6.049E-06 3.144E-01
8.892E-06 2.813E+00 1.230E-06 -3.240E-06 -3.519E-07 -1.608E-08 6.013E-06 3.102E-01
8.788E-06 2.797E+00 1.230E-06 -3.220E-06 -3.513E-07 -1.623E-08 5.979E-06 3.061E-01
8.688E-06 2.782E+00 1.230E-06 -3.201E-06 -3.507E-07 -1.639E-08 5.946E-06 3.021E-01
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8.592E-06 2.767E+00 1.230E-06 -3.183E-06 -3.501E-07 -1.654E-08 5.914E-06 2.982E-01
8.501E-06 2.753E+00 1.230E-06 -3.165E-06 -3.496E-07 -1.669E-08 5.884E-06 2.943E-01
8.413E-06 2.739E+00 1.230E-06 -3.148E-06 -3.490E-07 -1.685E-08 5.854E-06 2.906E-01
8.329E-06 2.726E+00 1.230E-06 -3.132E-06 -3.485E-07 -1.700E-08 5.826E-06 2.870E-01
8.248E-06 2.713E+00 1.230E-06 -3.116E-06 -3.480E-07 -1.716E-08 5.798E-06 2.835E-01
8.170E-06 2.701E+00 1.230E-06 -3.100E-06 -3.475E-07 -1.731E-08 5.772E-06 2.801E-01
8.094E-06 2.689E+00 1.230E-06 -3.086E-06 -3.470E-07 -1.747E-08 5.746E-06 2.767E-018.022E-06 2.677E+00 1.230E-06 -3.071E-06 -3.465E-07 -1.763E-08 5.721E-06 2.734E-01
7.952E-06 2.666E+00 1.230E-06 -3.057E-06 -3.461E-07 -1.778E-08 5.697E-06 2.702E-01
7.885E-06 2.655E+00 1.230E-06 -3.044E-06 -3.456E-07 -1.794E-08 5.674E-06 2.671E-01
7.820E-06 2.645E+00 1.230E-06 -3.031E-06 -3.452E-07 -1.809E-08 5.651E-06 2.640E-01
7.758E-06 2.635E+00 1.230E-06 -3.018E-06 -3.448E-07 -1.825E-08 5.629E-06 2.610E-01
9.629E-06 2.923E+00 1.230E-06 -3.376E-06 -3.561E-07 -1.518E-08 6.250E-06 3.373E-01
7.758E-06 2.635E+00 1.230E-06 -3.018E-06 -3.448E-07 -1.825E-08 5.629E-06 2.610E-01
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ICS(pl) VCS(pk) PIN
1.426E-04 7.380E-01 1.250E+02
2.045E-04 7.110E-01 1.250E+02
2.446E-04 1.339E+00 1.250E+022.499E-04 1.340E+00 1.250E+02
2.552E-04 1.340E+00 1.250E+02
2.605E-04 1.341E+00 1.250E+02
2.658E-04 1.343E+00 1.250E+02
2.711E-04 1.344E+00 1.250E+02
2.765E-04 1.346E+00 1.250E+02
2.818E-04 1.348E+00 1.250E+02
2.871E-04 1.350E+00 1.250E+02
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2.924E-04 1.353E+00 1.250E+02
2.977E-04 1.355E+00 1.250E+02
3.030E-04 1.358E+00 1.250E+02
3.084E-04 1.361E+00 1.250E+02
3.137E-04 1.364E+00 1.250E+02
3.190E-04 1.367E+00 1.250E+02
3.243E-04 1.370E+00 1.250E+023.296E-04 1.374E+00 1.250E+02
3.349E-04 1.378E+00 1.250E+02
3.403E-04 1.381E+00 1.250E+02
3.456E-04 1.385E+00 1.250E+02
3.509E-04 1.389E+00 1.250E+02
2.446E-04 1.339E+00
3.509E-04 1.389E+00
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Topology:
Main Output Power: 120
Anticipated Overall Efficiency of the Converter: 0.96
Maximum Switching Frequency: 130.0E+3
Minimum Switching Frequency: Burst packets of 40kHz pulses at loads of 15% or less
Minimum Input Voltage: 260.22
Maximum Input Voltage: 373.35
Peak PRIMARY Current: 3.16
PRIMARY RMS Current: 1.01
Duty Cycle at Minimum Input Voltage, Maximum Load: 0.30
Duty Cycle at Maximum Input Voltage, Maximum Load: 0.23
SECONDARY Output Voltage: 24
SECONDARY Output Peak Current: 15.30
SECONDARY RMS Current: 7.189
BIAS Voltage: 19.4
Approximate RMS BIAS Current: 44.5E-3
Magnetizing Inductance: 233.9E-6
Maximum Leakage Inductance: 3.5E-6
PRIMARY to SECONDARY Turns Ratio (NPRI/NSEC): 4.841
PRIMARY to BIAS Turns Ratio (NPRI/NBIAS): 5.989
Isolation Requirement: 1500
INPUT:
INDUCTANCE AND TURNS RATIO:
OUTPUTS:
A
A
V
V
V
V
The flyback transformer plays a crucial role in the performance of the green mode controller.
Considerations must be given to adequate coupling for the bias windings, minimizing leakage
inductance, and minimizing audible noise. All of these criteria can easily be met with proper transformer
design from the start.
A
A
GENERAL:
A
H
H
Flyback Inductor Specification for the UCC28600 Greenmode
Quasi-Resonant Converter
SPECIAL NOTES REGARDING THE FLYBACK TRANSFORMER:
Quasi-Resonant Flyback with Bias Winding
W
Hz
1. The BIAS windings must be well coupled to the PRIMARY. Interleave BIAS ans SECONDARY windings
between the primary for equal coupling.
2. Use bundled stranded wire.
3. Encase the windings in as much Ferrite as possible; a round post core is a must to help reduce leakage.
4. Do not use tape barriers. Use triple insulated wire on the SECONDARY to meet the isolation requirement while
minimizing leakage inductance.
V
8. Wind the SECONDARY so that the non-dot end is the outer most layer.
5. Must be potted or heavily varnished to reduce audible noise. Also, fill the gap with flexible epoxy to reduce
audible noise.
6. Distribute the BIAS windings over the entire width of the bobbin.
7. Place the dot end of the PRIMARY winding as close to the core as possible to help shield the dv/dt noise.
Secondary,
Triple insulated
wire
Primary
Insulation tape