Three Degree of Freedom Robust Voltage Controller for Instantaneous Current Sharing Among Voltage Source Inverters in Parallel14

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010 3003

Three Degree of Freedom Robust Voltage Controllerfor Instantaneous Current Sharing Among Voltage

Source Inverters in ParallelShahil Shah and Partha Sarathi Sensarma, Member, IEEE

AbstractVoltage controlled voltage source inverters (VCVSI)are predominantly used as an interface between source and grid indistributed generation. Modularity of system is achieved by paral-lel operation of several VCVSI of reduced rating. In this paper, a3-DOF control scheme is proposed for parallel operation of threephase inverters to enable equal load sharing even during transientswhile tracking a common sinusoidal voltage reference. The voltagereference is either free running or derived from grid voltage andcan be used to synchronize a parallel inverter module with anyutility grid. The control algorithm for each inverter is identical,

and it is independent of terminal parameters of other inverters,granting N+1 modularity to the system. The proposed fast innervoltage loop with second-order controller and lead compensatorsenable stable operation at low switching frequencies. A voltage cor-rection is added to the reference to ensure sharing of higher orderload current harmonics among inverters. A method to estimate thesystem tolerance to parametric uncertainties and delays is devel-oped using-analysis and a method is presented to improve it. Theanalysis is validated with simulation and experimental results ontwo 110 Vac/2.5 kVA three-phase inverters, paralleled to form astand-alone grid and feeding a nonlinear load.

Index Terms-analysis, instantaneous current sharing, multi-inverter system, parallel operation.

I. INTRODUCTION

PARALLEL CONNECTED arrays of voltage controlled

voltage source inverters (VCVSI) have a wide range of

applications including modular uninterruptible power supply

systems and microgrids with renewable energy sources (RES).

However, parallel operation requires an effective control strat-

egy to avoid circulating currents and ensure commensurate shar-

ing of the total load current among the parallel VSIs, in propor-

tion to their ratings, both in steady-state anddynamic conditions.

Classical approaches for parallel operation of inverters in-

corporate droop characteristics, similar in principle to parallel

operation of alternators in power systems [1][10]. Althoughthese methods do not require control interconnection among

Manuscript received November 5, 2009; revised April 24, 2010; acceptedApril 28, 2010. Date of current version December 27, 2010. This work wassupported by the research grant under National Mission for Power ElectronicsTechnology initiative of Department of Information Technology, Governmentof India. Recommended for publication by Associate Editor F. Blaabjerg.

S. Shah is with the Accelerator and Pulsed Power Division, Bhabha AtomicResearch Centre, Mumbai 400085, India (e-mail: [email protected]).

P. S. Sensarma is with the Department of Electrical Engineering, IndianInstitute of Technology, Kanpur 208016, India (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2050150

inverters, they exhibit poor frequency and voltage regulation.

Though it is possible to share harmonics currents of nonlinear

loads by using harmonic droop coefficients [8], it requires the

use of extra droop coefficients for each harmonic and is limited

to lower order harmonics due to poor dynamics of the method.

Masterslave methods [11][14] employ one VCVSI acting as

a master and remaining (n-1) current controlled VSIs as slaves.However, the system has to be shut down in the event of failure

of master unit. Effects on circulating currents among inverterscaused by various factors, like dead-time effects [15] and com-

mon mode circulating currents due to common dc link [16],

have also been investigated.

Continuous improvement in device switching speeds has

enabled higher hardware bandwidth of VCVSIs, which has

inspired a series of instantaneous current sharing schemes

[17] [25]. These schemes are based on a control mechanism,

which requires information of current in every parallel unit. Al-

though the instantaneous current sharing ensures proportionate

sharing of load harmonic currents, the overall system bandwidth

is limited due to lower order controllers [17]. Controller design

is done using classical stability margins, although these are

multiloop control systems [17]. On one hand, this restricts theachievable closed-loop performance and, on theother, it does not

consider the cumulative effects of parametric and delay uncer-

tainties in various loops on relative stability of the system [26].

Also, in [17], the effects of uncertainties in parameters are an-

alyzed collectively by a single-disturbing current source. This

is an indirect approach and results in conservative design. A

common voltage controller for all paralleled inverters, instead

of individual voltage controllers for each inverter, has also been

proposed [19]. But this topology results in inadequate redun-

dancy since no inverter is allowed to operate as an independent

unit. Available methods for instantaneous current sharing dis-

cuss the design of outer current controller, considering only theaspect of system stability [17], [18]. Efficacy of the controllers

in reducing circulating currents and the corresponding dynamics

of current equalization among parallel units are crucial figures-

of-merit, which have been generally de-emphasized. Moreover,

despite the fact that resonating effects of long wiring cables are

discussed in literature [25], the critical consequences of delays

caused by sampling and transmission delays due to distant lo-

cation of loads have not been addressed. Such delays are crucial

for high-power inverter units operating at low switching fre-

quencies, where these loop delays make the operation of units

at low switching frequencies unstable. It is shown in this paper

that, in fact, the existing schemes are completely unsuitable at

low switching frequencies.

0885-8993/$26.00 2010 IEEE


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3004 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010

Fig. 1. Distributed generation configuration of parallel inverters.

In this paper, a novel perturbed plant model is proposed for

parallel inverters to segregate the perturbed plant and to ana-

lyze the effectiveness of the outer current controller in reducing

circulating currents and equalizing load currents from different

inverters. To realize the feature of instantaneous current sharing

while addressing the aforementioned issues, a -analysis-basedsecond-order unified voltage controller is proposed, whichquan-

titatively evaluates the effect of uncertainties on system stabil-

ity by modeling parametric uncertainty, using linear fractional

transformation (LFT) [27]. Structured singular value () is usedto determine the maximum tolerable parametric uncertainty and

the measure of relative stability. The voltage controller is de-

signed with higher bandwidth to simultaneously track a free-

running voltage reference and correction terms from an outer

current loop. Theouter current loop is commandedby the instan-

taneous weighted fraction of the load current. Specific compen-

sation schemes in the multiloop voltage controller are proposed

in this paper, which allows 3 DOF for compensation of switch-

ing and sampling lag. Compensator performance is evaluatedat different sampling frequencies using -analysis, which re-veals substantial improvement with the proposed scheme. This

allows stable operation at lower switching frequencies as well as

higher uncertainty in parameter values can be accommodated.

Also, the system remains stable even with higher transmission

lag. Stability analysis of the whole system, in presence of param-

eter variation, is done by superposing an equivalent perturbed

system on an ideal system, characterized by identical param-

eters for all inverters. Design issues for the proposed strategy

are discussed, and all analysis is supported by simulation and

experimental results.

II. SYSTEM CONFIGURATION AND MODELING

Fig. 1 shows the conceptual layout of n parallel invertersbeing fed from various RES modules. Modulation signals for

each three-phase inverter are generated through voltage control

scheme, consisting of stabilizing inner capacitor current loop

and output capacitor voltage feedback loop [17]. The voltage

control loop tracks the common synchronized reference vo

along with correction signal vp from outer current sharingloop to minimize current imbalance among parallel units, as

shown in Fig. 2, for the pth inverter. The common current ref-erence iav g is the averaged signal of output currents from all

inverters and ip is output current from the pth inverter. Devia-

TABLE INOMINAL PARAMETER VALUES FOR THREE-PHASE INVERTER AND

RIPPLE FILTER

tion of inverter output current from iav g drives the proportionalcurrent sharing controller to produce correction signal vp . Fil-ter inductor current il is sum of inverter output current ip andcapacitor current ic .

A. Modeling of Plant

The inverter with ripple filter forms the basic plant and each

phase of these second-order ripple filters is configured with a

tuned inductor (Lf

) and capacitor (Cf

) along with consideration

of parasitic resistance of inductor (Rf). Fig. 2 shows the mul-tiloop structure of voltage control scheme for inverter having

feedback loops, using filter capacitor current ic and the capaci-tor voltage vp . The switching harmonics of output voltage frominverter vi are filtered using LCfilter. Nominally, modeling theinverter as an algebraic gain (M) [17], the control and distur-bance transfer functions for the open-loop plant are derived from

Fig. 2 as in (1).

vp (s)

vi (s)= Gc (s) =

1 + Rc Cfs

LfCfs2 + (Rc + Rf)Cfs + 1

vp (s)

ip (s)

= Gd (s) = Rf + Lfs

LfCfs2 + (Rc + Rf)Cfs + 1 . (1)

Nominal parameter values used for design and hardware are

listed in Table I. Bode plots for nominal plant transfer func-

tion Gc (s) and disturbance transfer function Gd (s) are shownin Fig. 3. Although the forms of these functions are similar,

the difference in the bode plots is due to the positions of the

respective zeros.

B. Robust Voltage Controller

Inner loop voltage controller bandwidth is decided by the

highest order of harmonic in the load current. In usual nonlinear

loads, magnitude of current harmonics higher than 21st is suffi-

ciently small to pose any major challenge to stability. Additional

damping is provided by an inner capacitor current loop with gain

kc , which actively damps the system and imparts robustness to-ward external disturbances [28], [29]. Modified system transfer

functions in presence of active damping loop are as follows.

Gc (s) =vp (s)

vi (s)=

1 + Rc Cfs

LfCfs2 + (Rc + Rf + kc )Cfs + 1

Gd (s) =vp (s)

ip (s)=

(Rf + Lfs)

LfCfs2 + (Rc + Rf + kc )Cfs + 1.

(2)


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SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3005

Fig. 2. Per phase schematic of complete control loop for pth inverter.

Fig. 3. Bode plot of nominal plant and disturbance transfer function.

Fig. 4. Bode plot of nominal plant and disturbance transfer function withactive damping loop.

It is evident from (2) that the loop emulates the effect of an

additional resistance ofkc . Bode plots of plant and disturbancetransfer function in Fig. 4 illustrate the reduction in resonant

peaks.

1) LFT Model of Perturbed Plant: Parametric uncertainties

in filter parameters and delays in digitized feedback loops are

unavoidable, and their effects on performance and stability of

voltage control loop has to be analyzed. Fig. 5 shows the block

diagrammatic representation of plant transfer function Gc (s). Itis, however, obvious that the output impedance Gd (s) is spar-

ingly affected by parameter variations, especially in the low-

Fig. 5. Block diagram of plant.

frequency zone, and this effect is further lowered by the stable

closed loop.

Although the plant parameters Lf, Cf, and Rf exhibit certainvariations from their nominal values, it can be assumed that

their values lie within certain known intervals by anticipating

the worst-case perturbations. Mathematically,

Lf

= Lf

(1 +pL f

L f

) and Cf

= Cf

(1 +pCf

Cf

)(3)

where Lf and Cf are nominal values from Table I. Also, theterms pL f L f and pCf Cf in (3) represent the possible relativeperturbations on these two filter parameters. The uncertainty

interval is defined by assumingpL f = 0.3,pCf = 0.3, and 1 L f , Cf 1. Note that this represents up to 30% uncertaintyin filter inductance and filter capacitance. Perturbation in Rf isnot considered as it is evident from Fig. 5 that the uncertainty

in Rf will not affect the performance of system owing to thelarge fixed value of active damping constant kc compared to thesmall parasitic resistance.

Upper LFT (ULFT) is used to represent parametric uncer-

tainties in the block diagram to express the system equations inM- configuration [30]. The perturbed parameter, 1/x (x = Lfor Cf), can be represented in LFT in x as in (4).

1

x=

1

x

1

(1 +px x )=

1

x

pxx

x (1 +px x )1

=FU(Mx , x ) with Mx =

px

1x

px1x

. (4)

The system model of Fig. 5 as an LFT of the unknown, real per-

turbations L f and Cf with inputs and outputs of L f and Cfas yL f , yCf , and uL f , uCf , respectively, along with definition

of states is shown in Fig. 6.


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Fig. 6. Block diagram of plant with LFT model of uncertain parameters.

Fig. 7. Close-loop system structure.

Equation (5) describes the dynamic behavior of perturbed

plant of Fig. 6, using (4) with y (=x) as its output.

x

t

yL f

yCf

y

=

G L C

0 1Cf

0 pCf 0

1L f

R f +kc

L fpL f 0

1L f

1L f

R f +kc

L fpL f 0

1L f

0 1Cf

0 pCf 0

1 0 0 0 0

x

t

uL f

uCf

vi

uL fuCf

=

L f 0

0 Cf

yL fyCf

. (5)

The uncertain behavior of original plant of Fig. 5 is described

by an upper LFT representation (y = Fu (GL C, ) vi ) usingsystem matrix GL C and uncertainty matrix , as shown inshaded portion of Fig. 7. It also shows the close-loop control

topology with voltage controller and performance weighting

transfer function Wp .2) Controller Design: The capacitor voltage feedback con-

troller is designed to ensure required close-loop bandwidth

higher than 26th harmonic to minimize phase errors at the edgeof the target passband (21st harmonic). To achieve optimum

tracking performance and good disturbance rejection, sensitivity

function (S= 1/(1 + Gc H)) has to be minimized. Performanceobjectives are closely related to the sensitivity function [27],

and they are dictated by shaping sensitivity function using Wpby relation

| Wp (j)S(j) | 1 . (6)

Sensitivity function shows the additionalattenuation to the effect

of disturbing load current ip apart from Gd achieved throughfeedback controller. A first-order high-gain low-pass weighting

function tailors the performance requirements like bandwidth

Fig. 8. Inverse weighting function and closed-loop sensitivity functions fornominal and perturbed systems.

TABLE II

PARAMETER VALUES FOR VOLTAGE CONTROLLER

and load current disturbance attenuation in low frequency range,

as shown in Fig. 8.

From (6), it is obvious that the singular value plot of 1/Wpdetermines the upper bound for the sensitivity function. The

performancerequirement becomes less stringent with increasing

frequency, and it canbe seen fromFig. 8 that beyond therequired

bandwidth, the disturbance is no longer attenuated.

The -analysis-based controller design is more appealing be-cause it is capable of considering robust performance and robust

stability simultaneously and it takes into account the uncertain-

ties in different loops of the multiloop structure [26]. For stan-

dard M- configuration, value gives the measure of the small-est size of uncertainty that makes system M unstable and it isdefined such that

1 (M) is equal to the smallest of maximumsingular value of (()), which makes (I M(j)(j ))singular at some frequency [30]. Mathematically,

1 (M) := min

() : det(I M) = 0 for some

(7)

where is set of possible uncertainties matrices, . Hence, if (M(s)) < 1/, it implies that the structured uncertainty inthe system can be times higher than the stipulated bound ofpL f and pCf . This quantifies the robust stability of controllerH in dealing with structured uncertainty [30]. For the pro-posed -analysis-based second-order controller H(s), it is ofthe form shown in (8), which may be conceived as a cascaded

P-I controller with a phase-lead network.

H(s) =K(s + z1)(s + z2)

s(s +p). (8)

All relevant controller parameters are listed in Table II.


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Fig. 9. Robust stability analysis responses.

The structured singular value () lies within the following

bound

(M) (M) (M) (9)

where (M) is spectral radius and (M) is maximum singularvalue of system transfer function matrix M(s). The frequencyresponses of the upper and lower bounds of for closed loopare shown in Fig. 9, and it is clear that the close-loop system

achieves robust stability as is less than unity [27].The peak at resonant frequency signifies that the most desta-

bilizing effect of parametric uncertainties is in that frequency

range. Also, the peak value of of 0.4195 shows that the struc-tured perturbations with norm less than 1/ are permissible,

i.e., the voltage control loop remains stable for < 1/.The designed -analysis-based controller accommodates para-metric uncertainties of up to 71.5% (30 1/). Fig. 8 alsoshows the nominal closed-loop sensitivity function, which re-

mains below the inverse performance weighting function over

a large frequency range, thus assuring specified nominal track-

ing and disturbance rejection performances. Also, the sensitivity

function for perturbed systems remains below the 1/Wp plot forfrequency range of concern, as shown in Fig. 8, assuring robust

performance.

3) Modeling of Inner Loop: The nominal close-loop transfer

function Gcl p of the voltage control loop and the disturbancetransfer function in form of impedance Zo are stated as follows:

Gcl p =vpvp

=Gc H

1 + Gc HS= Gc HS

Zo =vpip

=Gd

1 + Gc H= Gd S. (10)

These two transfer functions are succinctly represented as

a controlled voltage source with gain Gcl p in series withimpedance Zo , as shown in Fig. 10.

4) Lead Compensation Scheme for Feedback Delays: The

distributed nature of sources and loads imply sensing of the

load currents at local feeders, which need to be transmitted over

some distance to the inverters for feedback. This results in de-

Fig. 10. Circuit representation of inverter and filter integrated with dampingand inner voltage loops.

Fig. 11. Voltage controller with ZOH and delay compensators in feedback

loops.

lays within the feedback loops with consequent degradation of

stability margins. Additionally, sampling of the feedback signals

introduces a linear phase delay, which further compromises rel-

ative stability as the sampling frequency s is reduced. Since salso largely decides the minimum inverter switching frequency,

obvious attempts to stabilize the system degrades efficiency and

cost-benefit of the inverter. Existing current sharing schemes

do not account for this fact and are generally unsuitable for

low-frequency (high power) applications.

Since it is difficult to analyze the effect of delays on relative

stability of a multiloop system using classical stability margins[26], -analysis is used here to quantify the delays, which it canaccommodate while maintaining performance and robustness.

It also provides a generalized platform to study the effect of

various compensation techniques, which can be used to alleviate

the degrading effects of any such delays.

Effect of sampling delay at different sampling frequency,

which is assumed to be same as switching frequency, is analyzed

here by introducing ZOH (zero-order hold) block in the inner

capacitor current and output voltage loops, as shown in Fig. 11.

First-order Pade approximation shown in (11) is used to model

ZOH.

ZOH = (1 e2s/ s

)(2s/s )

1

1 s/s1 + s/s

/(2s/s ) =

1

1 + s/s.

(11)

Fig. 12 shows the frequency responses for upper bound of forclose loop at different switching frequencies. It is evident that

the system loses stability and the instantaneous current sharing

is not possible at lower switching frequencies, where SSV is

beyond unity.

It is also observed that the instability caused due to sam-

pling delays lies mostly around the resonant frequency (r =


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Fig. 12. -responses versus switching frequency for inner voltage loop.

Fig. 13. -responses versus switching frequency with lead compensationincluded.

1/

LfCf), indicated by values exceeding unity. Samplinglag in feedback signals at the resonant frequency r is

la g (r ) =rs

radian. (12)

First order lead compensators L(s) with unity gain and phase

lead ofla g at r are proposed and included for compensationof sampling delays in active damping and voltage feedback loop

of inner-voltage controller, as shown in Fig. 11. Fig. 12 shows

the closed-loop frequency responses for upper bound of values

at different switching frequencies, and Fig. 13 shows the corre-sponding -responses after inclusion of lead compensation. Inboth cases, the sampling frequency is assumed to be same as the

switching frequency. The value is brought within unity evenfor lower switching frequencies and makes it possible to stably

operate the current sharing scheme at lower switching speeds.

The transmission delays, which are also deterministic in nature,

can be compensated in the same manner.

The peaks of, from Fig. 12 are plotted for different switch-ing frequencies in Fig. 14 for different control configurations,

namely, tuned P-I controller, using classical stability margins

[17], proposed -analysis-based second-order voltage controller

and combination of-analysis-based controller, and lead com-

Fig. 14. Peak values of SSV() versus switching frequency for different con-trol configurations.

Fig. 15. Block diagrammatic representation of multiinverter system with cur-rent sharing controller.

pensation for sampling delays. It shows that stable operation is

not possible for switching frequencies below 38 kHz with first-

order voltage controllers. Thus, it demonstrates the significant

benefits of the proposed scheme over reported methods, using

lower order voltage controllers designed based on classical sta-

bility margins.

C. Current Sharing Controller

Fig. 15 shows the schematic representation of multiple invert-

ers in parallel, feeding the local grid through their corresponding

transformers. Despite the voltage controller, imbalance in cur-

rents shared by different inverters is still perceptible at higher

frequencies due to unavoidable deviation in filter parameters.

An outer current loop is proposed here to improve transient

sharing of currents among the paralleled units.

The common current reference for all inverters is derived

from the instantaneous weighted average of the load current.

Specifically, current reference for the pth inverter is derived as


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Fig. 16. Equivalent circuit of multiparallel inverters.

follows.

ip =Spn

k = 1 SkiL (13)

where Sk is the VA rating of the kth inverter. In the present case,without loss of generality, all inverters are considered to be of

identical rating. Hence (13) reduces to

ip =iLn

= iav g . (14)

A proportional controller ensures adequate reference tracking,

as the effective plant comprises a first-order line admittance (RL). For the first inverter path, v1 is the control input and the gridvoltage vo acts as the disturbance input. This controller outputgenerates a correction voltage term (v), over the synchronizedvoltage reference, to track the current command, as shown in

Fig. 2. So, for the pth inverter

vp = kcorr {iav g ip } (15)

where kcorr is the gain of the proportional controller.1) Analysis of Current Sharing Controller: Fig. 10 shows the

circuit equivalent of the close-loop voltage controller, designed

in the previous section. Effect of the current sharing controller

is appended to this equivalent circuit by a dependent voltage

source in series. Consequently, the n-inverter model of Fig. 15

is updated to the circuit shown in Fig. 16.

In Fig. 15, all inverters would have shared the load current

equally if their filter, line, and control parameters were exactly

identical. But due to parameter mismatch, apart from average

current (iav g ), each inverter in general carries a perturbationcurrent (i

p). Each of these perturbation currents represent the

circulating current in that branch, which is the instantaneous

deviation of the total branch current from the ideal value of

iav g . So,

ip = iav g + ip . (16)

From Fig. 16, loop equation for the pth inverter and load is

Gcl p V

o + kcorrGcl p (iav g ip ) ip (Zo + Rl + Ll s)

= iL ZL = Vo . (17)

Defining the internal impedance (Zip ) of the pth branch as

Zip = Gcl p kcorr + Zop + Rl + Ll s (18)

Fig. 17. Equivalent circuit of perturbed portion of parallel inverters system.(a) Configuration 1. (b) Configuration 2.

(17) reduces to

Gcl p V

o iav g (Zo + Rl + Ll s) (ip )Zip = iL ZL = Vo .(19)

For the ideal systemwithout any mismatchall inverters

carry equal load current (iav g ) and all circulating currents reduceto zero. Hence,

Gcl V

o iav g (Zo + Rl + Ll s) = iL ZL = Vo (20)

where Gcl is the nominal closed-loop gain. Parameter variationwithin each inverter introduces slight variation in the closed-

loop gains Gcl p . Defining

Gcl p V

o = Gcl V

o + vp (21)

manipulation of (19), (20), and (21) yields the following equa-

tion of the perturbed system.

vp (ip )Zip = 0. (22)

It is obvious that, for the ideal plant, any investigation into the

current sharing is superfluous. Thus theeffect on the perturbed

plant is considered here in greater detail. Equation (22) repre-

sents the voltage equation for the pth branch of the perturbedplant, which is schematically shown in Fig. 17(a) and its Nor-

ton equivalent in Fig. 17(b). The excitation vp (ip ) representsinner-loop variations and disturbances in the pth inverter volt-age (current). The perturbed system is not affected by load

variations and describes the dynamic behavior of the circulating

currents.

Equation (18) represents the complex impedance Zip to thecirculating current ip of the pth branch whose poles can betuned by tuning the gain kcorr . The current controller (kcorr ) actsas a constant virtual impedance of high value added in series

with low valued Zo and line impedance, when Gcl p is approxi-mated as unity in the frequency range of concern due to faster

inner loop. This decreases the percentage deviance and abso-

lute value of admittance of branches of perturbed plant. Hence,

current controller not only equalizes the impedances of all in-

verters, but it also decreases the amount of circulating current to

a large extent by selectively increasing the impedance offered.

All inverters will share equal currents if all these currents (ip )

in the perturbed plant decay fast.


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Considering thepth branchin Fig. 17,the Thevenin equivalentof the remaining network is specified by

ZTh =1n

k =1 ,k =p(1/Zik )

and VTh =

n

k =1 ,k =p

ip

ZTh .

(23)

Obviously, both VT h and ZTh progressively decrease as thenumber of units (n) increases. Thus, branch current ip ischiefly decided by vp as

ip = Yp vp =1

Zip + ZThvp . (24)

For the ideal situation of identical parameters, the quantity Ypin (24) reduces to

Yp =n 1

nZi=

n 1

nYi

= Ytotal. (25)

where Zi (= 1/Yi ) is the nominal internal impedance function.

Asymptotic stability of admittance Ytotal (all poles in the lefthalf of s-plane) assures all circulating currents (i) decay ex-ponentially to zero and poles in the deep left half imply better

dynamic response. Equation (25) shows that the number of in-

verters (n) only affects the gain ofYtotal, but not the location ofitspoles (stability). As thenumber of parallel units increases, in a

real case, YTh approaches (n 1)Yi . Also, its stability dependsupon the stability of the admittance of single inverter Yi , becausethe denominator ofYTh is equal to the product of denominatorsof admittances of remaining network (n-1 inverters). Moreover,the stability ofYi in presence of worst parametric perturbationsproves the stability of admittances of all inverters and hence of

YTh .In low-frequency region, first term of (18) shadows the ef-fect of remaining terms due to chosen high value of kcorr. Thisdecreases and equalizes the admittances of individual inverters.

For nominal values of filter and line parameters, Yi is stable.The locus of its dominant poles is plotted in Fig. 18(a) and (b)

for perturbations in the filter parameters. Fig. 18(a) shows the

loci of poles with different kcorr values, which illustrates thecontrollability of pole locations by outer-loop controller gain.

The poles are observed to be somewhat less sensitive to varia-

tions in Cf than to variations in Lf. Fig. 18(c) shows the widevariation of poles of Ytotal with variation in the proportionalgain kcorr and its limiting value for stability. Hence, it is suf-

ficient, even for substantial variations in system parameters, toensure arbitrary pole placement. Thus it is possible to uniquely

decide relative stability ofYip , even in presence of deviations inparameter values.

Apart from ensuring stability under parameter variations, the

control scheme is supposed to ensure proper sharing of the

load current among the various units. The extent of mismatch

among the paralleled units may be visualized by the spread of

the internal complex impedance of all branches. To this end, the

effectiveness of each subsequent stage in the control scheme is

summarized in Fig. 19. Each trace corresponds to a filter param-

eter pair, within a 30% range of variation around the nominal

values. Fig. 19(a) shows the open-loop internal impedance (Gd ),

TABLE IIIPERTURBED PARAMETER VALUES OF TWO INVERTERS USED FOR SIMULATION

and Fig. 19(b) shows the frequency response ofGd . The admit-tance function 1/Zip is plotted in Fig. 19(c) for convenience. Itis to be noted that the admittances for all cases are equal in low

frequency range to the inverse of proportional gain of current

controller (20 log(1/kcorr) = 4.7 dB). Also, the significantreduction in the spread of both the phase and magnitude plots

demonstrates that strict current sharing is ensured among the

various parallel branches.

Current in thepth branch, as a fraction of the total load current,is defined by the sharing factor (p ) as follows.

p=

ipnk =1

ik

= Yipn

k = 1Yik

. (26)Equation (26) is applicable for the close-loop system. In open

loop, the sharing factor is still obtainable from (26) by replacing

Yi with Gd . Fig. 19(d) shows a comparison of the open- andclose-loop sharing factors for a two-inverter system. Filter pa-

rameters for the two inverters are at the two extreme bounds of

the range mentioned earlier. From (24), it follows that this is the

worst-case scenario, for which the sharing is observed to have

significantly improved.Since branch impedance Zip limits the circulating current

flow among paralleled units, a high value of line impedance

parameters simplifies the outer-loop design by reducing the re-

quired value ofkcorr .2) Simulation Results for Current Sharing Loop: Fig. 20

shows the simulated currents of each of the three phases of two

parallel inverters under different load transients. A step load of

80% is applied at t = 40 ms and thrown off at t = 60 ms. Filterparameters used in simulation of each of the two inverters are

given in Table III. It is observed that there is excellent sharing

of the load current in all phases of the two inverters.

III. EXPERIMENTAL RESULTS

The instantaneous current sharing loop and voltage controller

are implemented using two three-phase 110 V, 2.5 kVA, insu-

lated gate bipolar transistor inverters. The filter parameters are

same as listed in Table I. Switching frequency used in the exper-

imental studies is 20 kHz. The entire controller is realized on an

field-programmable gate array (FPGA) (ALTERA-Cyclone 2)-

based platform. Current feedback is obtained with Hall-effect

current transducers, while voltages are sensed using optical iso-

lation amplifiers. Sensor gains are tuned to optimum values to

utilize full resolution of A/D converters on FPGA card. All


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Fig. 18. Stability and tuning of Yt o t a l in presence of perturbations in system parameters. (a) Variation of location of Poles of Yi with 30% variation in Lf .(b) Variation of location of Poles of Yi with 30% variation in Cf . (c) Control on Location of Poles of Yi using kc o r r .

Fig. 19. Effect of control scheme on internal impedance and sharing factor. (a) Internal impedance (open-loop). (b) Internal impedance (with active damping).(c) Branch admittance. (d) Sharing factor with two units.

sensed signals to FPGA card are passed through clamp circuits

to protect A/D converter from spurious peaks. Apart from localparameters, each inverter also requires the information of the

total load current, iL . The load used was a three-phase dioderectifier feeding an RL circuit. Fig. 21 shows the experimen-tal setup of two inverters with their ripple filters and rectifier

load. To emulate the worst-case situation, experiments are per-

formed without line transformers, giving the lowest possible

line impedances.

Fig. 22 shows steady state responses of the voltage controller

and demonstrates the role of the damping loop. Fig. 22(a) and

22(b) shows the tracking performance in absence and presence,

respectively, of active damping. It is observed that oscillatorybe-

havior of filter severely hampers waveform quality, when damp-

ing is absent. Fig. 23 shows the transient responses of the inner

voltage controller. Fig. 23(a) shows the reference and actualvoltages during inverter start-up. Response of voltage controller

clearly demonstrates the increased relative stability due to active

damping. Fig. 23(b) shows the phase-A current in one inverter

and the common grid voltage after application of full load. It is

observed that higher bandwidth of inner loop has ensured volt-

age tracking even in presence of such severe transients. As the

oscilloscope bandwidth was set to observe the high frequency

components of load current, the load current response shows

probe noise which were not present.

Fig. 24(a) and (b) demonstrates the operation of the current

sharing controller with nonlinear loads. Fig. 24(a) shows the

phase-A currents of both inverters, during step application of


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Fig. 20. Output currents from all phases of two inverters superimposed; loadtransient applied at 0.04 s and 0.06 s.

Fig. 21. Experimental setup.

Fig. 22. Steady-state response of voltage controller. (a) vo with kc = 0. (b) vo(blue) and vo

(red) for kc = 3.

Fig. 23. Voltagecontroller results. (a) Step responseof voltage controller withinitial transients. (b) Transients at application of full load.

Fig. 24. Current sharing for phase-A. (a) Current sharing for phase-A duringswitching ON of rectifier load. (b) Current sharing for phase-A during increasein load.


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full load. It is observed that the load currents are shared equally

even during severe load transients. Fig. 24(b) shows the same

waveform for an intermediate load step.

IV. CONCLUSION

The use of three phase parallel inverters as an interfacing

link between grid and nonconventional energy sources havebeen presented in this paper. A unified 3-DOF robust voltage

control scheme for output voltage tracking and instantaneous

current sharing was introduced. Modeling of parametric uncer-

tainties of plant using LFT was presented and robustness of

-analysis-based designed controller against such perturbationswas analyzed. The effect of sampling delays in feedback loops

on stability was analyzed in terms of SSV(). The generalizedplatform to analyze different compensating schemes for various

kind of delays, which is crucial for distributed generation sys-

tems, was presented. Thelead compensators for sampling delays

were proposed, which allows the stable operation of inverters at

lower switching frequencies. The dynamics of circulating cur-

rents were studied using proposed perturbed plant model of the

system. It wasestablished that the current controller acts directly

as an impedance to circulating current, and it can be designed

to suit the specifications of instantaneous current sharing. The

stability of perturbed network was analyzed using branch ad-

mittance Yi in presence of parametric uncertainties. Followingconclusions were drawn from analysis.

1) The low-bandwidth controllers designed based on clas-

sical stability margins are not suitable for operation of

inverters at low switching frequencies. The -analysis-based controller takes into account the multiloop structure

and are robust toward uncertainties in filter parameters.

2) The destabilizing effect of delays in feedback loops canbe reduced substantially by proper inclusion of compen-

sators in loop. The performance of such system with mul-

tiple compensators can be evaluated in terms of structured

singular value ().3) The constant gain kcorr of outer-loop current controller

acts as high resistance to circulating currents, and it de-

creases and equalizes them resulting in truly instantaneous

current sharing.

The experimental validation of all analytical and simulation

studies comprehensively demonstrate the effectiveness and re-

alizability of the proposed scheme.

ACKNOWLEDGMENT

The authors would like to acknowledge Department of In-

formation Technology for their support and the nodal agency

CDAC, Thiruvananthapuram. They would also like to acknowl-

edge Mr. A. Basu and Mr. Nandkishor for their support toward

hardware development.

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Shahil Shah received the B.E. degree from the Gov-ernment Engineering College, Gandhinagar, India, in2006, and the M.Tech. degree from the Indian In-stitute of Technology (IIT), Kanpur, India, both inelectrical engineering.

In 2006, he was a Postgraduate student at the IIT,Kanpur, where he was engaged in research on micro-grid, using nonconventional energy sources. This in-cludes the parallel operation of uninterruptible powersupply to form a microgrid, using renewable energysources. The project was supported by Centre for De-

velopment of Advanced Computing, Trivandrum, India. He is currently a Sci-entific Officer at the Bhabha Atomic Research Centre, Mumbai, India, wherehe is engaged in research on high-voltage MARX generator systems and pulsemodulator supplies for linear induction accelerators.

Partha Sarathi Sensarma (M00) received theB.E.E. degree from Jadavpur University, Calcutta,India, in 1990, the M.Tech degree from the IndianInstitute of Technology (IIT), Kharagpur, India, in1992, and the Ph.D. degree from the Indian Instituteof Science, Bangalore, India, in 2001, all in electricalengineering.

He was with the Bharat Bijlee Ltd., Thane, In-dia, CESC Ltd., India, and ABB Corporate Research,Baden-Daettwil, Switzerland, where he was a StaffScientist with the Power Electronics Department.

Since 2002, he has been with the Department of Electrical Engineering, IIT,Kanpur, where he is currently an Associate Professor. He is actively involvedin research, design, and deployment of power electronic interfaces for windenergy-based power plants as well as grid-interactive and islanded solar pho-tovoltaic plants. His other research interests include power quality, flexible actransmission system devices, power supplies, and motor drives.

Three Degree of Freedom Robust Voltage Controller for Instantaneous Current Sharing Among Voltage Source Inverters in Parallel14

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