Thesis Presentation - engr.colostate.edu · Thesis Presentation Michael Steigerwald Spring 2007. Presentation Flow 1. Introduction To Soft Errors 2. Existing Works 3. Issues with

Thesis Presentation

Michael SteigerwaldSpring 2007

Presentation Flow

1. Introduction To Soft Errors2. Existing Works3. Issues with Existing Works4. Proposed Method5. Results6. Conclusion7. Future Work8. Questions

What is a soft error?• When a charged particle

from solar radiation (or any other radiation source) penetrates the pn junction of a transistor, it can create electron-hole pairs

• In the presence of an electric field, the strike can create a current pulse, which can in turn create a temporary voltage change at a node in a circuit

+n

substrate-p

+n

StrikeAlpha

_+

+ _

++_

_

++ _

++_

_

__+

When does a strike cause a soft error?

• Not all strikes have sufficient energy to create a soft error

• A soft error is defined to be an error that ends up being stored in some element in a circuit

• This means that the charged particle must have some minimum amount of energy to generate a soft error in a given circuit

Qcrit

• The minimum amount of charge required to cause a soft error at any given node is called Qcrit

• Any particle with less charge than Qcrit will not cause a soft error at that node, while any charge greater than Qcrit will always cause a soft error

Maskings

• There are three types of masking that occur:– Electrical Masking– Logical Masking– Latching Window Masking

Existing Work

• Previous Work:– Horowitz Propagation Method– Non-propagating Method– SEAT-LA Method– Reverse Propagation Method

Horowitz Propagating Method

• The Horowitz Method propagates a pulse based on the rise and fall times along with the gate delay

• Equations used by Horowitz Method:

Horowitz Propagating Method

• Problem Areas:– Do not take into account the logical masking

• On a small test circuit we see a 55-60% difference in the FIT for a given node

– Will show in later method that the propagation method does not have the required accuracy

Non-propagating Method• The Non-propagating method takes the worst case for

the path that is being evaluated.

• This method is also based on the delay of the gate.• Positive Areas:

– Takes into account Logical Masking and Timing Window Derating

– Limits the amount of SPICE simulations• Problem Areas:

– The assumption that was made in the calculation of timing derating

• Assume that the time of the glitch is set to hold time plus setup time• We saw a 38-45% difference with the TWD assumption

– The method of calculating the electrical masking

SEAT-LA Method

• This method uses a modified Horowitz delay model to calculate the electrical masking

SEAT-LA Method

SEAT-LA Method• Pre-characterization is completed on all blocks in the

circuit and results loaded into a lookup table• Positive Areas:

– Takes into account all of the maskings (logical, electrical, latching window)

– Limit SPICE in method• Problem Areas:

– Non-worst case for nodes on multiple paths• We saw a 14-37% difference when not considering worst case

– Accuracy of the modified Horowitz model• We saw a 0-24% difference vs. SPICE

Reverse Propagation Method• This method propagates a pulse from the input

of a latch, back to the node that is being characterized

Reverse Propagation Method• Pre-characterization is done to determine the factors for

the reverse propagation• Positive Areas:

– Takes into account internal nodes of gates– Limits the use of SPICE– Calculation of all three maskings

• Problem Areas:– Rail-to-Rail assumption (key to being able to propagate

backwards)– ATPG tool used for LM (we found this tool to give multiple

repeated patterns)– Inaccurate results vs. SPICE

• We saw a difference of 0-19% vs. SPICE

Reverse Propagating Method

Problems with Existing Work

• Large Circuit Simulation– None of the methods described have presented a

method that will be able to run on a large circuit• Logical Masking Calculation

– If the logical masking was calculated for any of these methods it was inaccurate or inefficient

• Electrical Masking Models– All of the methods presented electrical masking

models that do not provide the accuracy that is necessary for modern circuit designs

Proposed Method• 3 Parts:

– Calculate Qcrit– Calculate the Logical Masking– Calculate the FIT

• Diagram of the flow

Proposed Method

• Logical Masking Calculation– Logical Masking: Probability that a strike will

propagate to a particular output• By this definition, we have two logical masking values per

node per output, logical masking 0 (LM0) and logical masking 1 (LM1)

• For LM0 the node value must be 0 before the strike and for LM1 the node value must be 1

• Our methods then not only cover the probability of a strike being logically masked from the output but also the probability that this node will have an initial value of 1/0, thus making our approach much more accurate

Proposed Method

• 2 different methods– ATPG Tool Method– Monte Carlo Method

• The ATPG method is less accurate then the Monte Carlo method but the run time is much less and the memory usage is also less

Proposed Method

• Monte Carlo MethodStart

End

Get all the paths thatterminate in a latch

Extract all stageconnection

information from thepaths and create the

verilog netlist

Write the commandfile for VCS

Run VCS

Extract all the patterninformation from the

VCS result files

Calculate the logicalmaskings for each

node

Update the logicalmasking value stored

in each path head

patterns totalof #changesoutput of #

, =outputnodeLM

Proposed Method

Proposed Method

• ATPG MethodStart

End

Get all the paths foreach cone that

terminates in a latch(stages)

Extract all stageconnection

information from thepaths and create

verilog file

Write the commandfile for Tetramax

Run Tetramax

Extract all the patterninformation from theTetramax result files

Calculate the logicalmasking for each

node

Update the logicalmasking value stored

in each path head

LM = (2(# of don’t cares))/(2(# of inputs))

Proposed Method

• Qcrit Calculation– This is where the electrical masking is taken into

account– A binary search is done to find the Qcrit for each node

in the path

LL

I-V strike

V-V Propagation

?Determine if pulse latched

Proposed Method• Characterization

– Before the method can be implemented a characterization of each of the gates in the circuit must be completed.

– This characterization is broken into two different characterizations:

• I-V characterization– This is where the current strike is converted to a voltage strike– The output variables are WB, W50, H of the resultant pulse for the

inputs variables PulseWidth and node capacitance• V-V characterization

– This is where the pulse will transfer from a gates input to its output– The output variables are WB, W50, and H for the input variables of the

previous gates resultant WB, W50, H, and the node capacitance

Proposed Method

• Variable Definitions:

W50

H

WB

Proposed Method

• Interpolation is used to determine the correct value from the database

• I-V example below, the same kind of interpolation is also done from the V-V

PulseAmp Height

X

XA

C

BD

α

β

ε

δ

Proposed Method

• Latching Determination– Once a pulse is propagated to a latching

element, the next thing to look at is whether the pulse will be latched

– This is done by pre-characterizing each latch in the design

• This characterization is based on the incoming pulse’s W50 and WB

Proposed Method• Just as with the I-V propagation and the V-V propagation

the latching determination also uses a form of interpolation to determine if a pulse will latch

x1

x2x1

x2latched

not latched

X2 Latches in both cases above

Proposed Method

• The final section of the method is the calculation of the FIT

• This calculation takes into account 3 variables– Qcrit– Logical Masking– Timing Derating (Latching window masking)

• FIT calculation– Qcrit

• An equation is used to translate the Qcrit found in the previous section to FIT

• This equation is based on the process being used and the probability of a strike of the resultant charge needed to cause a soft error

– Logical Masking• This is a straight derating figure for the FIT

calculation

Proposed Method–Timing Derating

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

−−

<++

>+

=

otherwise ,

)( if ,1

)( if ,0

50

50

50

clock

holdsetuppulse

pulseclockholdsetup

pulseholdsetup

TttW

WTtt

Wtt

TWD

Proposed Method• FIT Equation

• There are two types of particle strikes that are taken into account Alpha and Neutron– The only difference is the equation that is used to

translate the Qcrit to FIT, the probability is different

TWDLMFITFIT strikeparticlestrike **,=

neutronneutronNeutron FITFITFIT ,01,10 >−>− +=alphaalphaAlpha FITFITFIT ,01,10 >−>− +=

Proposed Method

• Only the worst case for each node is used in the final calculation of the FIT for the entire circuit

• Then the FIT for each node is summed and this is the FIT number for the circuit

• By calculating the FIT in this manner you could easily find the FIT of a path or a cone– This information could be valuable if you wanted to

use a method such as shadow latching to detect soft error in control logic

Results

• Test circuits results

Results

• Logical Masking Results

Results

Summary• With continued scaling, the issue of soft errors in

control logic has become a major reliability concern

• The current published solutions to determining the susceptibility of nodes to a soft error are not as accurate as is required for the designers of today

• Our method has the accuracy that is needed without a major increase in the run-time

• Our results how that our method does work and also the difference in the accuracy of the two LM methods

Future Work

• Incorporate internal nodes of the gate into the calculation of the FIT

• Some improvements can be made to the calculation of the Timing Derating

• Determine if there is a way to improve the accuracy of the method while not increasing the run-time

Questions