Thesis presentation

1

“Design, Analysis and Simulations of a Si Schottky Diode Based Sampling Circuit

for 40 Gbps ETDM Demultiplexer Circuit“

Supervisors:Prof. Dr. techn. Peter RusserJung Han Choi, M.S.

Master Thesis:

Septiaji Eko Nugroho

Master of Science in Microwave Engineering (MSMWE) ProgramInstitute for High Frequency Engineering

2

Layout1. Sampling Circuit for Demultiplexer

Multiplexing Overview The Demultiplexer Circuit The Sampling Theory and The Undersampling Technique for

Demultiplexer Sampling Circuit for Demultiplexer

2. Driving Requirements and Components Driving Requirements The Components

3. Design, Analysis and Simulations The Rule of the Design Bandwidth Optimization: Analytic and Simulation Layout Design and Simulation Flip Chip Bonding Effect Effect of Oscillator Phase Difference

4. Conclusions and Future Works

3

1. Sampling Circuit for Demultiplexer

Multiplexing/Demultiplexing OverviewThe Demultiplexer Circuit in ETDM systemThe Sampling Theory and The Undersampling Technique for DemultiplexerSampling Circuit for Demultiplexer

4

Multiplexing/Demultiplexing Overview

Backgrounds:

•Optical fiber is able to transmit THz of signal

•The bit rate in the fiber was limited, caused by the speed of electronic components (i.e. 10 Gbps at 1995)

To increase the operation speed of the fiber : Multiplexing technique is introduced:

Time Division Multiplexing (TDM)

ETDM: Electronic TDM

OTDM: Optical TDM

Frequency Division Multiplexing (FDM)/Wavelength Division Multiplexing (WDM)


C hannel 1A G bps

M U X D E M U X

C hannel NA G bps

C hannel 2A G bps

C hannel 1A G bps

C hannel NA G bps

C hannel 2A G bps

Optical L inkN x A Gbps

5

The Demultiplexer Circuit for ETDM system


4-W ayP owerD iv ider

4 x A Gbps

D ecision C ircu it

D ecision C ircu it

D ecision C ircu it

D ecision C ircu it

A Gbpsunquantized data A Gbps

Digital Data

SamplingCircuit A GHz

Diagram of 4-Way Demultiplexer

Diagram of Optical Receiver

The Demultiplexer Circuit for ETDM system

P hotodiode A m plifierDemultiplexer

1:N

N x A Gbpsoptical signal

A Gbps

Channel 1

Channel 2

Channel 3

Channel N


n

ssinout nTtTtvtv )()()(

xvin (t) vout(t)

D iracDe lta

The Sampling Theory and The Undersampling Technique for Demultiplexer (1)

7

t im e

A m p litude

"1" "1"

P eriod o f the s igna lT

"1""1" "1" "1""1""0" "0""0" "0"

Input : Ideal NRZ signal

NRZ pulse:

001_ )

2(.)

2(.)(

nss

l

kkchout

TnTtT

TkTtgatv

Output of the first channel:

is “1” or “0”ka



otherwise

Ttfor

Ttfor

tg

,0

22

12

1

)(

8

For 1:2 Demultiplexer:Output of the first channel:

TTs 2

001_ )

22(.)

2(.)(

ns

l

kkchout

TnTtT

TkTtgatv

002_ )

2

32(.)

2(.)(

ns

l

kkchout

TnTtT

TkTtgatv

Output of the second channel:


(Undersampling Technique)


9

t im e

A m p litude

"1 " "1 "


"1 ""1 " "1 " "1 ""1 ""0 " "0 ""0 " "0 "

P eriod o f the sam p le r

T s

tim e

A m p litude

"1 " "1 ""1 " "0 " "0 "

Channel 1

t im e

A m p litude

"1 " "1 " "1 " "1 ""0 "

tim e

A m p litude

"1 " "1 "


"1 ""1 " "1 " "1 ""1 ""0 " "0 ""0 " "0 "

P eriod o f the sam p le r

T s

Channel 2

"0 "

Output



10

Sampling Circuit Topology:

-Based on Sampling Circuit of the Oscilloscope

-Using Double Diode Configuration

-Very Symmetric

The Sampling Circuit for Demultiplexer (1)


Zo =50 Oh m

In p u tS ig n al

Ch arg eAm p lifier

Ch arg eAm p lifier

Ou tp u tS ig n al

Vb ias

Vb ias

Stro b eG en erato r

S tro b eG en erato r

50Oh m

11

0

-0.2

0.4

0.5

DiodeVoltage

(V)

T im e (ps)

T S

Turn OnPoint

Zo=50 Ohm

InputSignal

ChargeAm plifier

ChargeAm plifier

OutputSignal

Vbias

Vbias

StrobeGenerator

StrobeGenerator

50Ohm

Chold

Chold

Basic operation:

-Vbias will charge Chold so that the diode will be in reverse bias

-The strobe turn on the diode in a very small span time

-In this span time, the charge will be transferred from the input into the Chold

The Sampling Circuit for Demultiplexer (2)


12

Driving RequirementsCircuit Components

2. Driving Requirements and Circuit Components

132. Circuit Requirements and Components

Driving Requirements

20 40 60 800 100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

freq, GHz

dB

(mag_fft_

vin

)

Broadband Characteristic is Important

Circuit bandwidth > 40 GHz is necessary

Spectrum of 40 Gbps NRZ signal PRBS 27-1


The Components in the Design

1. Infineon Schottky Diode Double Configuration

2. Oscillators 20 GHz max 1 Vpp

3. DC Bias

4. Alumina (Al2O3) Substrates

5. Hold Capacitors


General Properties:

-Using Flip-Chip Interconnections

-Cjo=30 fF, Rs=10 Ohm

-Max forward current = 25 mA

Modeled by Root Diode Model in the ADS:

•Large signal table based model

•Generated from measured DC and small signal S-Parameters

Infineon Schottky Diode Double Configuration


0.1 0.2 0.3 0.4 0.5 0.6 0.70.0 0.8

-05

10152025

-5

30

Vbias

IC.i,

mA

We define turn-on point of the diode is 480 mV

DC Characteristic of the Diode Model


Equivalent Model

)2(1

2

122o

sp

psres Z

LC

CLf

Resonance frequency *):

*)Chun-Long Wang and Ruey-Beei Wu, “A Locally matching Technique for Broadband Flip-chip Transition Design,” IEEE Trans. Microwave Theory Tech., pp. 1399, February 2002.

Using L=103 pH, C=45 fF, Zo=50 Ohm

fres=76.9 GHz

Height= 5 um

Diameter=50 um

Flip-Chip Bonding AuSn (1)


Equivalent Model*)

The double diode pad C=20 fF

Flip-Chip Bonding AuSn (2)

*)Jung Han Choi, C.-J. Weiske, G.R. Olbrich, P. Russer, “Flip-chip bonded Si Schottky Sampling Circuits for High Speed Demultiplexer”, Microwave Symposium Digest, 2003 IEEE MTT-S International, vol. 3, pp. 1515-1518, 8-13 June 2003.

19

The Rule of DesignBandwidth Optimization: Analytic and SimulationLayout Design and SimulationOperation in Lower SpeedFlip Chip Bonding EffectEffect of Oscillator Phase Difference

3. Design, Analysis and Simulation

20

V s(t)

-V s(t)

C hold

C hold

R b

R bV bias

-V bias

R in

R t

50 O hm

F LIP -C H IP B O N D IN G



Input 40 G bpsP R B S 2 7-1 O utput 20 G bps

R out

R out

•Oscillator is used

•Flip-chip bonding model is included

•Input Bit pattern is PRBS 27-1

Circuit Topology


21

3 .8 3 .93 .7 4 .0

3 0 0

3 5 0

4 0 0

4 5 0

5 0 0

2 5 0

5 5 0

time , nsecV

_dio

de, m

V

T urn O nP o in t

Proper operation

Turn-on point = 480 mV

Basic Operation : Turning On the Diode (1)

outbD

diodeosc

b

bias

diode

RRtZ

dttV

CddtV

CdRV

tV11

)(1

))(

()(

)(


22

Unproper operation:

•Diode voltage always above the turn on point: all bits will be passed

•Caused by too small Rbias (e.g. 15 Ohm)

3.8 3.93.7 4.0

590

600

610

620

630

580

640

time, nsec

V_dio

de, m

V

0.2 0.4 0.6 0.80.0 1.0

0

50

100

150

-50

200

time, nsec

vin, m

Vvo

ut, m

V

Basic Operation : Turning On the Diode (2)


23

Input 40 Gbps PRBS 27-1

Output Channel 1

Output Channel 2

Simulation Results


24

•Vertical Eye opening= 45 mV

Eye Diagram of the 20 Gbps Output Signal


0 20 40 60 80 100 120 140-20 160

-0.01

-0.00

0.01

0.02

0.03

0.04

-0.02

0.05

time, psec

eye_

vout

50 ps

45 mV

25

0)()(213111

DDtin

in

Z

VV

Z

VV

R

V

R

VV

Using KCL on all nodes:

0)()(1222

Dout

out

eq Z

VV

R

VV

Z

V

0)()(1333

Dout

out

eq Z

VV

R

VV

Z

V

050

32

Ohm

V

R

VV

R

VV out

out

out

out

out

b

beq CRj

RZ

1)(

•Flip-chip bonding is neglected

•Diodes are turned-on

Bandwidth Optimization (1) - Analytic


26

Rout

ZRRZ

RZR

RCRjRZRR

RinZV

V

DtinD

outD

out

b

boutDtinD

in

out

2

)(211

)(

21)(

150

)100(150

)100(

1

)(211

)(

2

2

Transfer function:

50

)100(.

)(

211)(

2)(

out

b

DtinD

RR

ZRRRinZ

A

Rb

ZRRZ

RRZB

DtinD

outoutD

.

)(

211)(

2)

100(

1001(

1

)(

11)(

2

Define :



27

Transfer function:

B

CRjB

AH

b

1

1)(

It has low pass characteristic, with cutoff frequency:

bdB CR

Bf

23 C

f dB

13 or



28

Bandwidth Optimization (4) – S-Parameter Simulation


29

Bandwidth Optimization (5) – Impulse Response


Chold (pF) FWHM (ps)

0.5 7.2

0.3 6.6

0.1 5.2

•Smaller Chold leads higher bandwidth

•Bigger Chold will reduce the fringing voltage

30

Bandwidth Optimization (6) – Comparison


0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

0.5 0.4 0.3 0.2 0.1

Chold (pF)

Fre

q (

GH

z) F3dB analytic(GHz)

f3dB simulation(GHz)

31

•Substrate Thickness : 10 mil

•Dielectric : 9.9

•Permeability : 1.0

•Metal conductivity : 4.1E+07

S/m ( Gold )

•Metal tangent loss : 0.00

•Metal thickness : 6 um

•Metal Roughness : 0.0

•Resistive layer : 40

Ohm/square

Alumina Substrate Properties

Layout Design (1)


32

Intrinsic Circuit:

•Brown-Conductor layer

•Green-Resistive layer

•Size 1700 x 1700 (um)

Layout Design (2)-SC_0609

InputSIgnal

OutputSIgnal

Vbias

Vbias

Capacitor andOscillator



33

Major Problem:

•Resonance at 38 GHz using Chold 0.1 pF, and 29 GHZ using Chold 0.2 pF

•Caused by the effect of the distance between capacitor and the diode (675 um)

•Then the distance must be reduced

-32-30-28-26-24-22-20-18-16

-34

-14

dB

(S(2

,1))

5 10 15 20 25 30 35 40 45 50 550 60

-150

-100

-50

0

50

100

150

-200

200

freq, GHz

phase(S

(2,1

))

ADS Co-simulation Result



34

1000 um x 1400 um.

Distance betwen capacitor and diode is 250 um


InputSIgnal

OutputSIgnal

Vbias

Vbias




35

5 10 15 20 25 30 35 40 45 50 550 60

-150

-100

-50

0

50

100

150

-200

200

freq, GHz

phase(S

(2,1

))

m3freq=3.000GHzdB(S(2,1))=-12.814

m4freq=55.00GHzdB(S(2,1))=-15.756

-17

-16

-15

-14

-13

-18

-12dB

(S(2

,1))

m3

m4

5 10 15 20 25 30 35 40 45 50 550 60

-150

-100

-50

0

50

100

150

-200

200

freq, GHz

phase(S

(2,1

))

55 GHz bandwidth with linear phase is achieved using Chold 0.1 pF.


ADS Co-simulation Result:


36

0 20 40 60 80 100 120 140-20 160

-0.01

0.00

0.01

0.02

0.03

-0.02

0.04

time, psec

eye_

vout

time, psec

eye_

vout

0 20 40 60 80 100 120 140 -20 160

-0.01

-0.00

0.01

0.02

0.03

0.04

-0.02

0.05

Infineon Schotkky Diode

•Output peak=32 mV

•Eye_opening=18 mV

•There is distortion

Ideal Diode

•Output peak=45 mV

•Eye_opening=30 mV

•The distortion is small

Output Eyewaveform


37

-0 50 100 150 200 250-50 300

0.00

0.01

0.02

0.03

0.04

-0.01

0.05

time, psec

eye

_vo

ut

-0 100 200 300 400 500-100 600

0.00

0.01

0.02

0.03

0.04

-0.01

0.05

time, psec

eye_vout

20 Gbps DEMUX 1:2

Chold=0.35 pF

10 Gbps DEMUX 1:2 Chold=0.65 pF

Operation in Lower Speed


38

Flip-Chip Bonding Effect (1)


39

0 20 40 60 80 100 120 140-20 160

0.00

0.02

0.04

0.06

0.08

-0.02

0.10

time, pseceye_w

ithout_

flip

chip

0 20 40 60 80 100 120 140-20 160

0.00

0.02

0.04

0.06

0.08

-0.02

0.10

time, psec

Eye_w

ith_flip

chip

Without flipchip

With flipchip

Flip-Chip Bonding Effect (2)-40 Gbps Input


40

Without flipchip

With flipchip

0 10 20 30 40 50 60 70-10 80

0.00

0.01

0.02

-0.01

0.03

time, psec

eye_

outp

ut

3 8 13 18 23 28 33-2 36

0.000.020.040.060.080.100.120.140.160.180.200.220.24

-0.02

0.26

time, psec

Vin

put

Input 86 Gbps RZ PRBS 27-1

Output Eyewavefor

m

Flip-Chip Bonding Effect (3)-86 Gbps Input

Flip-chip bonding highly affects the 86 Gbps performance.


41

Effect of Asymmetry: Oscillator Phase Difference (1)

Portion of the Oscillators on the output signal:

outoutcb

out

DDin

DD

in

in

c

ss

out

RRtZR

R

tZtZR

tZtZ

R

V

Z

VV

V21

)(

11

50

100

)(

1

)(

12

)(

1

)(

1

'

21

21

The phase difference will add sinusoidal signal as distortion in the output. The greater the phase difference, the greater the distortion

2sin

2cos2)sin(sin'

tAtAtAVV ss

2sin

2cos2

tA


42

0 20 40 60 80 100 120 140-20 160

-0.01

0.00

0.01

0.02

0.03

-0.02

0.04

time, psec

eye_

vout

0 20 40 60 80 100 120 140-20 160

-0.02

-0.01

-0.00

0.01

0.02

0.03

-0.03

0.04

time, psec

eye_vout

0 20 40 60 80 100 120 140-20 160

-0.02

-0.01

-0.00

0.01

0.02

0.03

-0.03

0.04

time, psec

eye_vout

10o phase difference5o phase difference

15o phase difference

Up to 5o difference can be tolerated

Effect of Asymmetry: Oscillator Phase Difference (2)


43

ConclusionsFuture Works


44

1. Sampling circuit for demultiplexer 1:2 with input ETDM 40 Gbps NRZ has been designed, analyzed and simulated.

2. The bandwidth analysis has excellent agreement with the simulation up to 50 GHz.

3. To avoid resonance in the desired passband, the distance between capacitor and the diode should be minimized.

4. With Chold 0.1 pF, cutoff frequency of 55 GHz with linear phase are achieved. (SC_0110)

5. The output amplitude of 32 mV and eye opening of 18 mV are achieved.

6. The sampling circuit works well in lower bit rate with excellent output eye diagram (20 Gbps and 10 Gbps input).

Conclusions (1)


45

7. The flip-chip bonding affects the bandwidth of the circuit above 50 GHz. It greatly affects the circuit with 86 Gbps input. But it doesn‘t contribute significant effect to the circuit with 40 Gbps input.

8. The oscillator phase difference of 5o can be tolerated in this circuit.

Conclusions (2)


46

Future Works

Choosing better diode, which has smaller zero bias junction capacitance, Cj0 lower than 10 fF is recommended for 40 Gbps operation.The real capacitor model with self resonance frequency (SRF) more than 50 GHz should be included, with its interconnectionCompensating the effect of the flip-chip bonding for operation above 40 GbpsExtending the circuit into the desired size of the complete circuit


47

Thank You!

Vielen Dank!

Terimakasih!

Maturnuwun!

Syukron!

Thesis presentation

Documents

demultiplexer sampling

circuit requirements

layout sampling circuit

sampling circuit topology

sampling theory

sampling circuitfor

components design

circuit topology oscillator