Thesis

ABSTRACT

SURI, RAHUL. Device Design of Sub‐100nm Fully‐depleted Silicon‐on‐Insulator (SOI) Devices Based on High‐k Epitaxial‐Buried Oxide. (Under the direction of Dr. Veena Misra).

The Integrated Circuit industry is driven by the continuously shrinking feature size of devices.

The era of planar bulk MOS transistor, however, is nearing its end. The performance of bulk MOS

transistor is severely degraded by short channel effects in the sub‐65nm regime. In such a

scenario, the Silicon‐on‐Insulator (SOI) technology looks set to become the next driver of CMOS

scaling. SOI has been proved capable of providing increased transistor speed, reduced power

consumption and enhanced device scalability as demanded by the 65nm and beyond technology

generations. The problems facing SOI include fabrication of thin silicon and buried oxide (BOX)

films and high manufacturing cost.

This thesis focuses on a novel approach to building a SOI substrate which uses an epitaxial oxide

as template to grow silicon on top. The novel ‘Floating Epitaxy SOI’ aims to guarantee thin silicon

films and low manufacturing cost. This research work involves modeling ultra‐thin body fully

depleted SOI devices from 60nm gate length down to 10nm gate length. The device uses

metal/high‐k gatestack and strained silicon as attractive features for better device performance.

The goal of this work is to re‐engineer the device structure and alter device design parameters at

every gate length such that device performance meets the semiconductor roadmap projections in

terms of off‐state leakage current and ratio of drive current to leakage current as specified by

International Technology Roadmap for Semiconductors. (ITRS)

A challenge to better device performance is the high permittivity of candidate epitaxial oxides. It

is well established that high permittivity buried oxide layer adds additional short channel effects.

This makes device design and control of short channel effects more difficult. The major findings

of this thesis are that ultra‐thin body SOI devices based on ‘Floating Epitaxy SOI’ meet ITRS

projections down to 10nm gate length. Moreover, for sub‐15nm devices that require ultra‐thin

BOX, high permittivity of BOX doesn’t hurt device performance but improves it slightly.

Device Design of Sub‐100nm Fully‐depleted Silicon‐on‐Insulator (SOI)

Devices Based on High‐k Epitaxial‐Buried Oxide

by

Rahul Suri

A thesis submitted to the Graduate Faculty of North Carolina State University

In partial fulfillment of the Requirements for the degree of

Master of Science

Electrical Engineering

Raleigh, North Carolina

2006

Approved By:

Dr. Carlton Osburn Dr. Jon-Paul Maria Dr. Veena Misra Chair of Advisory Committee

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To

Mom, Dad and Brother Excerpt from ‘The Wonder Years’: “Because that night, when my father let Karen go out, he let Karen go, and maybe thatʹs how it had to be.......Children leave...and parents stay behind. Still, some things are deeper than time and distance. And your father will always be your father...And he will always leave a light on for you.”

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BIOGRAPHY

Rahul Suri was born in New Delhi, India in October 1982. He received his Bachelor of Engineering

(B.E.) degree in Electronics and Communication from Netaji Subhas Institute of Technology, India, in

June 2004. In August 2004, he began his graduate studies in Electrical Engineering at North Carolina

State University. His focus has been on IC Fabrication and Nanotechnology. In Summer of 2005, he

interned with Qimonda NA (formerly Infineon Technologies NA), Cary, NC in the Memory Product

Design group. He worked on the layout of DRAM chip in 70nm technology. While working towards

his Masters degree, he worked on his thesis under the guidance of Dr. Veena Misra. He plans to

continue his graduate studies towards earning the doctorate degree. His research interests include

nanoscale device design, modeling and characterization. He is also interested in emerging, silicon

and non‐silicon based nanotechnologies.

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ACKNOWLEDGEMENTS

Above all, I thank my parents for the much needed motivation throughout the duration of graduate

studies and particularly thesis work. It was their love and support that helped me maintain sanity

during stressful times. Every time I felt I was losing track, they kindled strong hope and belief in me

that helped me to get going with positive approach and enthusiasm.

I sincerely thank my advisor, Dr. Veena Misra for giving me the opportunity to work on this thesis

project and guiding me from time to time with useful suggestions. I am indebted to her for the

knowledge that she has imparted to me through a couple of her courses‐Frontiers of Nanoelectronics

and Principles of MOS Transistor, which encouraged me to take up this field seriously and I believe

will form the foundation of my career.

I am grateful to Dr. Carlton Osburn for having taught the courses‐IC Technology and Fabrication and

Semiconductor Characterization both of which built the fundamentals and strengthened my

understanding of this field. The talks I have had with him have inspired me in ways more than one. I

thank him for agreeing to be on my thesis committee

I would like to thank Dr. Jon‐Paul Maria for agreeing to be on my thesis committee. I would also like

to thank Dr. Angus Kingon, Dan Lichtenwalner and Jennifer Hydrick who worked on the materials

issues of the thesis project and gave useful feedback based on experimental results and encouraged

me to come up with positive results.

I would like to thank my friends‐Vivek Mehta and Pranav with whom I spent most of my time, for

their support and encouragement. I thank Namrata for her understanding and supportive nature,

Dhaval Parekh for help and support, Deepak for inspiring me to work hard and Shoubhik Doss for

sharing jovial times and several food sessions. Special thanks to my roommates‐Arun, Vivek Jayadev,

Ajay and Nitin for making my stay memorable and for good south‐indian food. I also thank Ajit,

Kaushik and Ravi for useful discussions. Finally I thank, Muktabh, Jay, Neil and ‘The Vivek Hakim’

for providing awesome entertainment during the period of thesis writing.

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CONTENTS

List of Figures….……………………………………………………………………………….viii List of Tables………………………………………………………………………………………xi

1 Introduction 1

1.1 Silicon on Insulator and CMOS Scaling......................................................................................... 1 1.2 Silicon on Insulator Advantages..................................................................................................... 2 1.3 Silicon on Insulator Devices ............................................................................................................ 3 1.4 Silicon on Insulator Fabrication ...................................................................................................... 5

1.4.1 Bond and Etch Back (BESOI) .............................................................................................. 5 1.4.2 Separation by Implantation of Oxygen (SIMOX)............................................................. 5 1.4.3 Unibond or Smart‐CutTM ..................................................................................................... 6

1.5 Silicon on Insulator Challenges....................................................................................................... 6 1.6 References .......................................................................................................................................... 7

2 Floating Epitaxy SOI 8 2.1 Motivation for Research................................................................................................................... 8 2.2 Floating Epitaxy SOI – A Novel Approach ................................................................................... 9 2.3 Choice of Epitaxial Oxide .............................................................................................................. 10 2.4 Floating Epitaxy SOI Advantages ................................................................................................ 11 2.5 Thesis Goal....................................................................................................................................... 11 2.6 Thesis Organization........................................................................................................................ 12 2.7 References ........................................................................................................................................ 12

3 Device Modeling on Floating Epitaxy SOI 14 3.1 Introduction..................................................................................................................................... 14 3.2 UTB Device Structure..................................................................................................................... 14

3.2.1 Silicon Body......................................................................................................................... 14 3.2.2 Buried oxide ........................................................................................................................ 15 3.2.3 Silicon Substrate ................................................................................................................. 15 3.2.4 Gatestack ............................................................................................................................. 16

3.3 Modeling Setup............................................................................................................................... 16 3.4 Conclusion ....................................................................................................................................... 16

4 Strained Silicon and Device Performance 17 4.1 Need for strained silicon................................................................................................................ 17 4.2 Straining the Si Channel................................................................................................................. 18

4.2.1 Process‐induced strain....................................................................................................... 18 4.2.2 Substrate‐induced strain.................................................................................................... 18 4.2.3 Uniaxial Vs Biaxial Strain.................................................................................................. 20

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4.3 Mobility Enhancement ................................................................................................................... 20 4.4 Strained Silicon‐on‐Insulator......................................................................................................... 23 4.5 Modeling Strain in this work ........................................................................................................ 23 4.6 Simulation Results .......................................................................................................................... 24

4.6.1 Simulation Setup ................................................................................................................ 24 4.6.2 Strain and Drive Current................................................................................................... 25 4.6.2 Strain and Leakage Current .............................................................................................. 25 4.6.2 Strain and Threshold Voltage ........................................................................................... 25 4.6.3 Strain and Drain‐Induced barrier Lowering................................................................... 27

4.7 Conclusion ....................................................................................................................................... 27 4.8 References ........................................................................................................................................ 29

5 Initial Device Design 30 5.1 Introduction..................................................................................................................................... 31 5.2 Simulation Setup............................................................................................................................. 31 5.3 Simulation Results .......................................................................................................................... 33

5.2.1 Template Thickness Effect................................................................................................. 33 5.2.2 Channel Length Effect ....................................................................................................... 40 5.2.3 ITRS and Device Performance .......................................................................................... 40

5.4 Conclusion and Next...................................................................................................................... 40

6 Ground Plane Concept 44 6.1 Introduction..................................................................................................................................... 44 6.2 Ground Plane Concept................................................................................................................... 44 6.3 Ground Plane Vs Classical SOI ..................................................................................................... 46 6.4 Ground Plane Simulation Setup ................................................................................................... 49 6.5 Simulation Results .......................................................................................................................... 49

6.5.1 Potential in BOX and substrate......................................................................................... 49 6.5.2 Template Thickness Effect................................................................................................. 52 6.5.3 Continuous Ground‐plane Vs Ground‐plane under gate............................................. 52 6.5.4 Ground‐plane Device and ITRS ....................................................................................... 56

6.6 Conclusion and Next...................................................................................................................... 56 6.7 References...................................................................................................................58

7 Suppressing Short Channel Effects 59 7.1 Introduction..................................................................................................................................... 60 7.2 Silicon Channel Doping Effect ...................................................................................................... 60 7.3 Silicon Film Thickness Effect......................................................................................................... 61 7.4 Back‐gate Bias Effect....................................................................................................................... 63 7.5 Gate Workfunction Effect .............................................................................................................. 65 7.6 Simulation Setup and Results ....................................................................................................... 67

7.6.1 Varying the silicon film thickness .................................................................................... 67 7.6.2 Varying the back‐gate bias................................................................................................ 70 7.6.3 Relationship between silicon film thickness and back‐gate bias ................................. 70

7.7 Conclusion ....................................................................................................................................... 74 7.8 References ........................................................................................................................................ 74

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8 Buried Insulator Engineering 75 8.1 Introduction..................................................................................................................................... 76 8.2 BOX Thickness Scaling................................................................................................................... 76 8.3 BOX Permittivity Scaling ............................................................................................................... 79 8.4 Permittivity role at thick and thin BOX ....................................................................................... 79 8.5 Device Simulation of epi‐SOI device............................................................................................ 87

8.5.1 Varying Template Thickness ............................................................................................ 87 8.6 Conclusion ....................................................................................................................................... 89 8.7 References ........................................................................................................................................ 89

9 Device Design Optimization 90

9.1 Introduction..................................................................................................................................... 91 9.2 60nm Gate Length........................................................................................................................... 91 9.3 45nm Gate Length........................................................................................................................... 94 9.4 30nm Gate Length........................................................................................................................... 96 9.5 25nm Gate Length........................................................................................................................... 99 9.6 15nm Gate Length......................................................................................................................... 104 9.7 10nm Gate Length......................................................................................................................... 108 9.8 Meeting ITRS Ion/Ioff Specification ........................................................................................... 113 9.9 Conclusion ..................................................................................................................................... 115

10 Conclusion and Future Work 116

10.1 Conclusion ................................................................................................................................... 116 10.2 Future Work ................................................................................................................................ 117

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List of Figures Figure 1‐1 Cross‐section of an ultra thin body fully‐depleted SOI device....................................... 2 Figure 1‐2 Different gate configurations for SOI devices................................................................... 4 Figure 1‐3 Cross‐section of a FinFET ..................................................................................................... 4 Figure 2‐1 Cross‐section of Floating Epitaxy SOI substrate................................................................ 9 Figure 2‐2 Comparison of lattice parameter mismatch to silicon over a temperature range....... 10 Figure 3‐1 UTB SOI MOSFET based on Floating Epitaxy SOI.......................................................... 15 Figure 4‐1 TEM micrograph of 45nm p‐type and n‐type MOS ........................................................ 19 Figure 4‐2 Formation of SiGe alloy and growth of strained Si on top............................................. 19 Figure 4‐3 Mobility enhancement ratio for strained Si n‐MOSFETs ............................................... 19 Figure 4‐4 Strain induced conduction band splitting in silicon ....................................................... 22 Figure 4‐5 Energy alignment of the Si conduction band with and without the tensile strain ..... 22 Figure 4‐6 Simplified hole valence band structure for longitudinal in plane direction................ 22 Figure 4‐7 Id‐Vg curves for Lg =25nm with and without strain in Si channel................................ 26 Figure 4‐8 Id‐Vg curves for Lg =15nm with and without strain in Si channel................................ 26 Figure 4‐9 Ion and Ioff Vs channel length for device with and without strain in Si channel....... 28 Figure 4‐10 Vt and DIBL versus channel length for device with and without strain...................... 28 Figure 5‐1 Epitaxial‐oxide based SOI device (eSOI) .......................................................................... 32 Figure 5‐2 Standard SOI device or the ‘Core device’ ......................................................................... 32 Figure 5‐3 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................ 34 Figure 5‐4 Lg = 45nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................ 34 Figure 5‐5 Lg = 30nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................. 35 Figure 5‐6 Lg = 25nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................ 35 Figure 5‐7 Lg = 15nm a) Ioff c) Ion versus Template Thickness for core and new device ............ 36 Figure 5‐8 Lg = 10nm a) Ioff c) Ion versus Template Thickness for core and new device ............ 36 Figure 5‐9 Equipotential Contours in 30nm epi‐SOI device with 5nm thick template ................. 37 Figure 5‐10 a) Vt b) Off‐state current and c) on‐state current versus Template Thickness ............ 39 Figure 5‐11 a) Vt b) Off‐state current and c) on‐state current versus Channel Length................... 41 Figure 5‐12 a) Ioff b) Ion comparison with ITRS High Performance Logic Projections.................. 42 Figure 5‐13 Comparison of device Ion/Ioff ratio and ITRS HP Logic projections ........................... 42 Figure 6‐1 Schematic of fringing fields in SOI device........................................................................ 45 Figure 6‐2 Electrostatic Potential Contours in the BOX and substrate of a SOI device ................ 45 Figure 6‐3 Ground‐Plane structures..................................................................................................... 45 Figure 6‐4 Equipotential contours in a 0.1mm long device with Vg = 0V and Vd = 1.5V............. 47 Figure 6‐5 Vertical potential profile in the middle of a 80‐nm‐long SOI MOSFET ....................... 48 Figure 6‐6 Key processing steps of Ground Plane formation........................................................... 48 Figure 6‐7 a) Vt roll‐off and b) DIBL for device with and without ground plane ......................... 50 Figure 6‐8 Simulated vertical potential across center of silicon body for 25nm long device: ...... 50 Figure 6‐9 Simulated potential contours in 25nm long device with 5nm thick template............. 51 Figure 6‐10 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................. 53

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Figure 6‐11 Lg = 45nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................. 53 Figure 6‐12 Lg = 30nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................ 54 Figure 6‐13 Lg = 25nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness ................ 54 Figure 6‐14 Lg = 15nm a) Ioff c) Ion versus Template Thickness for core and new device ............ 55 Figure 6‐15 Lg = 10nm a) Ioff c) Ion versus Template Thickness for core and new device ............ 55 Figure 6‐16 Comparison of device Ioff values with ITRS HP Logic projections.............................. 57 Figure 6‐17 Comparison of device Ion/Ioff ratios with ITRS HP Logic projections ........................ 57 Figure 7‐1 Vt shift Vs TSi for different channel doping ..................................................................... 62 Figure 7‐2 MEDICI predicted TSi and channel doping requirements for FDSOI CMOS.............. 62 Figure 7‐3 Threshold voltage roll‐off for different channel doping ............................................... 62 Figure 7‐4 Threshold voltage versus channel length for mild and strong halo implants............ 64 Figure 7‐5 DIBL and subthreshold swing Vs channel length for different TSi .............................. 64 Figure 7‐6 Dependence of Vt and QM shift in Vt on TSi................................................................... 64 Figure 7‐7 Theoretical dependence of Vt on back‐gate voltage ...................................................... 66 Figure 7‐8 Dependence of Vt on back‐gate voltage .......................................................................... 66 Figure 7‐9 DIBL Vs TSi for different back‐gate voltages.................................................................... 66 Figure 7‐10 TSi dependence of the off‐state current of 50nm UTB device ....................................... 68 Figure 7‐11 Ratio of Ion/Ioff pf 50nm UTB device for different TSi and ΦM values ....................... 68 Figure 7‐12 Ratio of ΔVt/Vt versus TSi with different ΦM values ...................................................... 68 Figure 7‐13 DIBL Vs Lg for different TSi for device with ground‐plane and without ................... 69 Figure 7‐14 Vt roll‐off for TSi =5nm and 10nm for device with ground‐plane and without ......... 69 Figure 7‐15 Vt roll‐off for TSi =5nm and 10nm for device with ground‐plane and without.......... 69 Figure 7‐16 Sub‐Vt Swing Vs Lg for different TSi for device with and without ground‐plane. .... 69 Figure 7‐17 Ioff Vs Lg for different TSi for device with ground‐plane.............................................. 71 Figure 7‐18 Ratio Ion/Ioff Vs Lg for different TSi for device with ground‐plane ............................ 71 Figure 7‐19 Vt Vs Lg for ground‐plane device with TSi =7nm and different Vbg........................... 71 Figure 7‐20 DIBL Vs Lg for ground‐plane device with TSi =7nm and different Vbg ...................... 71 Figure 7‐21 Sub‐Vt Swing Vs Lg for ground‐plane device with TSi=7nm and different Vbg........ 72 Figure 7‐22 Ioff Vs Lg for ground‐plane device with TSi =7nm and different Vbg......................... 72 Figure 7‐23 Ratio Ion/Ioff Vs Lg for ground‐plane device with TSi=7nm and different Vbg......... 72 Figure 7‐24 Threshold voltage Vs Vbg for ground‐plane device with TSi=5nm and 10nm .......... 73 Figure 7‐25 Sub‐Vt Swing Vs Vbg for ground‐plane device with TSi=5nm and 10nm................... 73 Figure 7‐26 DIBL Vs Vbg for ground‐plane device with TSi=5nm and 10nm ................................. 73 Figure 8‐1 Simulated equipotential contours in ground‐plane device, TBox=200nm................... 78 Figure 8‐2 Simulated equipotential contours in ground‐plane device, TBox=10nm .................... 78 Figure 8‐3 DIBL Vs BOX thickness for ground‐plane device with Vbg=‐0.2V and ‐1V ................. 81 Figure 8‐4 DIBL Vs BOX thickness for ground‐plane and LD device with Vbg=‐0.2V and ‐1V.... 81 Figure 8‐5 DIBL versus BOX thickness for k=3.9 and k=5.0, Lg=30nm,TSi=7nm, Wf=4.7eV ......... 82 Figure 8‐6 Threshold Voltage Vs TBox for k=3.9 and k=5.0, Lg=30nm,TSi=7nm, Wf=4.7eV ......... 82 Figure 8‐7 Electrostatic potential along body/BOX interface at TBox =200nm and 10nm .............. 84 Figure 8‐8 Threshold voltage Vs Vbg for TBox =200nm, 25nm and 10nm for k=3.9 and k=5.0 ...... 84 Figure 8‐9 Subthreshold swing Vs BOX thickness for ground plane‐device ................................. 86 Figure 8‐10 Id‐Vg curves for ground‐plane device for Tbox=10nm and 100nm at BOX ................ 86 Figure 8‐11 DIBL Vs Lg for two template thicknesses for device with ground‐plane .................... 88 Figure 8‐12 Vt roll‐off Vs Lg for different template thicknesses for device with ground‐plane ... 88 Figure 8‐13 Vt roll‐off Vs Lg for 5nm and 2nm template thicknesses for ground‐plane device ... 88

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Figure 8‐14 Sub‐Vt Swing Vs Lg for different template thicknesses for ground‐plane device...... 88 Figure 9‐1 Id‐Vg plot for Lg=60nm for different template thicknesses. .......................................... 92 Figure 9‐2 Id‐Vg plot for Lg=45nm for different template thicknesses. .......................................... 95 Figure 9‐3 Id‐Vg plot for Lg=30nm for different template thicknesses. .......................................... 97 Figure 9‐4 Id‐Vg plot for Lg=30nm for 5nm and 4nm thick template, Tbox=15nm and 10nm....... 98 Figure 9‐5 Id‐Vg plot for Lg=25nm for different template thicknesses. ........................................ 100 Figure 9‐6 Id‐Vg plot for Lg=25nm for two device design parameters and TSi=7nm ................. 102 Figure 9‐7 Id‐Vg plot for Lg=25nm for 5nm and 4nm thick template at Tbox=15nm and 10nm. 103 Figure 9‐8 Id‐Vg plot for Lg=15nm for different template thicknesses. ........................................ 105 Figure 9‐9 Id‐Vg plot for Lg=15nm for 4nm thick template, TSi=5nm, TBox=6nm, ΦM=4.53eV. .. 107 Figure 9‐10 Id‐Vg plot for Lg=15nm with TSi=5nm, TBox=6nm, ΦM=4.53eV and Vbg=‐1V.............. 108 Figure 9‐11 Id‐Vg plot for Lg=10nm for different template thicknesses ......................................... 109 Figure 9‐12 Id‐Vg plot for Lg=10nm with TSi=5nm, TBox=5nm, Vbg=‐0.4V and variable ΦM. ........ 111 Figure 9‐13 ITRS expected and Simulated Ion/Ioff ratio versus channel length............................ 113 Figure 9‐14 ITRS expected and Simulated Ion/Ioff ratio versus channel length............................ 114

xi

List of Tables Table 9‐1 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 60nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 1E‐8A/um and 0.9mA/um ...................................................................... 93 Table 9‐2 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 45nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 3E‐8A/um and 0.98mA/um .................................................................... 95 Table 9‐3 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 30nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 5E‐8A/um and 1.09mA/um .................................................................... 97 Table 9‐4 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 25nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 1.7E‐7 A/um and 1.48mA/um .............................................................. 101 Table 9‐5 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 15nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 2.9E‐7 A/um and 2.03mA/um .............................................................. 105 Table 9‐6 Vt, Ioff, Ion, Subthreshold swing and DIBL values for 10nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 3.7E‐7 A/um and 2.18mA/um .............................................................. 110 Table 9‐7 Summary of device design parameters to meet ITRS HP Logic Ion/Ioff specification for different channel lengths. ....................................................................... 114

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Chapter 1 Introduction 1.1 Silicon on Insulator and CMOS Scaling The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. In the last

two decades, device feature size has decreased from 1μm down to 90nm. Scaling the physical device

dimensions (both lateral and transverse) has led to increased speed, higher packing density, and reduced

cost per good device built. The era of planar bulk MOS transistor, however, is nearing its end. The

performance of bulk MOS transistor is severely degraded by short channel effects in the sub-65nm regime.

Most important of short channel effects include the threshold voltage roll-off problem and drain-induced

barrier lowering (DIBL). The conventional MOSFET, thus, doesn’t look promising to meet the

requirements of 65nm and below technology nodes as specified by the International Technology Roadmap

for Semiconductors (ITRS). In such a scenario, the Silicon-on-Insulator (SOI) technology looks set to

become the next driver of CMOS scaling. SOI has been proved capable of providing increased transistor

speed, reduced power consumption and enhanced device scalability as demanded by the next technology

generations. Compared to similar circuits fabricated on bulk silicon wafers, CMOS circuits fabricated on

SOI wafers can run at 20-35% higher switching speeds than bulk CMOS, or 2 to 4 times lower power

requirements when operating at the same speed as bulk CMOS [1]. Research on SOI dates back to 1960s

when these devices were used for military and space applications because of their immunity to radiation-

induced ionization. Cost of manufacturing SOI wafers prevented their widespread growth and use. Today,

however, the ever increasing demand for higher speed and lesser power consumption makes the inherent

advantages of SOI, look all the more attractive. So much so that SOI has made its way into the

semiconductor roadmap and the ultra thin body SOI transistor is projected to be into manufacturing

mainstream by 2008. [2] According to France-based Soitec, which produces SOI wafers based on its

patented Smart Cut technology, SOI currently represents some 3-4% of the total wafer market, and this is

expected to rise to 10% by the end of the decade. [3] Almost all semiconductor companies have either

switched to SOI or are considering it for current and future devices. While IBM, AMD, Sony Group and

Toshiba have adopted SOI for the cell processor, Philips Semiconductors has been using SOI for high

voltage ICs. Freescale and STMicroelectronics have also begun to use to use SOI wafers. Several device

architectures based on SOI varying from single gate to multiple gate structures have evolved and are in the

stage of being researched. These include ground-plane SOI, Double-gate SOI, FINFET and so on. The

2

Moore’s law that drives scaling will continue to live on once the SOI technology hits the manufacturing

mainstream completely.

1.2 Silicon on Insulator Advantages The SOI substrate comprises of a silicon device layer usually tens of nanometers thick isolated from the

substrate by a relatively thick layer of insulating material, usually silicon dioxide, called buried oxide. The

cross-section of SOI device is shown in Figure 1-1. The major advantage of SOI comes from the fact that

the source and drain junctions end on the buried oxide layer, hence junction capacitances are minimized.

Also, because thin silicon film is employed, the junction depth is small and sub-surface leakage paths are

eliminated. In case of ultra thin body, the front gate has strong control over the channel and short channel

effects are suppressed. The reduction in source-drain parasitic capacitances makes switching operations

faster and enhances speed. It also leads to reduction in power consumption. IBM reported a 20% to 35%

increase in chip speed and 35% to 70% reduction in power consumption for their PowerPC chips [4]

Because, short channel effects are suppressed, SOI device has a steep subthreshold slope which translates

to a smaller off-state leakage current and larger drive current. The device is well isolated from substrate

both vertically by buried oxide and laterally by shallow trench or LOCOS grown oxide which has three

significant advantages. Firstly, any causes for latch-up in CMOS and cross-talk between devices in mixed

signal ICs are avoided. Secondly, soft errors from radiation effects usually in case of SRAMs are

minimized. And thirdly, different voltages may be used on different devices without the added processing

steps required for triple wells. As semiconductor process technologies move down the nanometer scale

from 90nm to 65nm and smaller, the benefits of silicon-on-insulator (SOI) wafers in reducing junction

capacitance, improving the short-channel effect, reducing leakage and decreasing soft error rates become

more and more attractive.

Figure 1-1 Cross-section of an ultra thin body fully-depleted SOI device (UTB SOI) [5]

3

1.3 Silicon on Insulator Devices Depending on the thickness of the silicon layer, SOI MOSFET will operate in fully depleted (FD)

or partially depleted (PD) regime. In PD regime, the silicon body is thick enough so that the

depletion region in the channel doesn’t extend up to the body‐BOX interface. A neutral region

exists and gives rise to floating‐body effects such as kink in Id‐Vd characteristics; latch and drain

current overshoot and undershoot. [6] The majority carriers, generated by impact ionization,

collect in the transistor body. This causes the body potential to rise, which lowers the threshold

voltage. This feedback gives rise to a kink in Id‐Vd characteristics, hysteresis and latch in log Id‐

Vg curves, and activation of the lateral bipolar transistor. [7] Proper design is needed to minimize

the detrimental aspects of the floating body and take advantage of the extra current available for

fabricating faster circuits. In FD MOSFETs, the depletion region covers the whole body and the

depletion charge is independent of the gate bias. A better coupling develops between gate

voltage and inversion charge, leading to enhanced drive current. In addition, the front‐ and back

surface potentials also become coupled. The coupling factor is roughly equal to the thickness

ratio between gate oxide and buried oxide. Due to interface coupling, the front‐gate threshold

voltage becomes a function of the back gate bias. The back‐gate bias gives additional control over

setting the threshold voltage of the device. The FD devices have several advantages compared to

the PD devices: free from kink effect [7], enhanced subthreshold swing [8], highest gains in circuit

speed, reduced power requirements and highest level of soft‐error immunity [9]. For sub‐100nm

channel length devices, FD SOI devices are the preferred choice.

Beyond the 65nm technology node, non‐classical CMOS devices based on SOI will take over from

bulk devices. The frontrunner is the ultra thin body (UTB) SOI MOSFET shown in Figure 1‐1.

Following it are multiple gate devices which have two or more surfaces along which inversion

occurs and current flows. These include double‐gate and triple‐gate structures such as the

quantum wire [10], the FinFET [11] and Δ‐channel SOI MOSFET [12], and quadruple‐gate devices

such as the gate all‐around (GAA) device [13], the DELTA transistor [14], vertical pillar MOSFETs

[15], and Pi‐gate SOI MOSFETs [16]. It is well known that the double‐gate (top and bottom gate)

silicon‐on‐insulator (SOI) MOSFET and the gate‐all‐around device are the most suitable device

structures for suppressing short‐channel effects such as DIBL and subthreshold slope

4

degradation [13], [17], [18]. Figure 1‐2 shows the existing gate configuration for thin‐film SOI

MOSFETs: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or GAA) and 5) pi‐gate.

Figure 1‐2 Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate; 5) Pi‐gate MOSFET [19] The FinFET, shown in Fig. 1‐2, has thin fins of Si etched into the top Si layer and gate electrodes

that are deposited and patterned on the sides of each fin. The inversion layer is formed on the

vertical edge of each fin, and the current flows from source to drain along these edges

Figure 1‐3 Cross‐section of a FinFET [5]

While 2D and 3D device simulation of mutilple gate devices show them to be the ultimate

devices with suppressed short channel effects and steep subthreshold slope, as required for sub‐

50nm devices, unfortunately the process proposed to fabricate these is incompatible with

standard CMOS or even SOI CMOS manufacturing. It is expected that by the time the need for

multiple gate structures becomes necessary, advancements in lithography, etching and wafer

processing techniques will occur to allow for easy fabrication of these devices.

5

1.4 Silicon on Insulator Fabrication Current methods of SOI fabrication include those based purely on wafer bonding, such as Bond

and Etch‐Back SOI (BESOI), those based purely on ion implantation, such as Separation by

Implantation of Oxygen (SIMOX), and those based on combination of wafer bonding and ion

implantation, such as Smart Cut™ by SOITEC.

1.4.1 Bond and Etch Back (BESOI)

BESOI wafers are made by bonding together two oxidized wafers, annealing, and etching or

grinding and polishing to achieve a thin silicon device layer. When placed together, the oxidized

wafers stick together with a weak hydrogen bond. An annealing step removes excess water from

the interface, and creates a continuous buried oxide (BOX) layer. Either etching or grinding and

polishing is employed to thin the silicon layer up to desired silicon body thickness. Etching

requires the use of an etch stop which is usually a buried layer of implanted boron. BESOI wafers

are typically made by the grind/polish method, as they are no longer considered useful for thin

film SOI. [20] These wafers result in thick silicon body and are used for high‐voltage, high‐power

devices or microelectromechanical systems. [21] The thick silicon associated with BESOI makes it

not appropriate for ultra‐thin body devices.

1.4.2 Separation by Implantation of Oxygen (SIMOX) A large dose of oxygen ions is implanted into a silicon wafer. A post‐implant anneal at about

1300°C follows for as long as 6 hours. Oxygen ions react with silicon to form silicon dioxide.

Annealing also repairs damage done to silicon device layer by implantation and restores its

crystalline quality. The implantation energy decides the location of silicon dioxide underneath

the surface and therefore controls the silicon body thickness. Implantation dose must be

controlled to ensure that there is sufficient oxygen to create a full SiO2 layer of the appropriate

thickness, and also that no silicon islands appear in the oxide film after annealing. [21] Lower

doses and higher annealing temperature anneals are used to minimize defect generation in the

silicon device layer. SIMOX wafers have good thickness uniformity, low defect density (except

threading dislocations: 104–106 cm−2), sharp Si–SiO2 interface, robust BOX, and high carrier

mobility. [22]

6

1.4.3 Unibond or Smart-CutTM Hydrogen ions are implanted into a thermally‐oxidized wafer. The depth of implant below the

oxide forms the silicon body thickness. It is therefore controlled by the implantation energy. This

wafer is then bonded to a silicon handle wafer, followed by a two step annealing process. [21]A

first anneal at 400‐600°C allows microcracks in the silicon in the implanted region that cause the

wafer to split, leaving a thin silicon device layer on top of the thermal oxide layer. A second

anneal at 1100°C for two hours removes silanol groups from the bonded interface, which leaves a

silicon/oxide interface of similar quality as that of a thermally grown oxide on silicon. [21]. Touch

polishing (removes tens of nanometers) of the surface silicon layer is done to complete the

processing of SOI wafer. The advantages of Unibond wafer include 1) no etch back step, 2) seed

wafers can be re‐used, 3) thickness control of oxide layer by oxidation time, 4) much better

thickness control of device layer and 5) only conventional equipment is needed for mass

production

1.5 Silicon on Insulator Challenges Although SOI technology is well established to provide high performance at low power, the

widespread adoption of SOI wafers still faces both real and perceived challenges. The main

barrier to the widespread adoption of SOI wafers for mainstream CMOS fabrication in the past

has been the uncertain silicon film or silicon dioxide layer quality and the high cost of SOI wafers.

The key materials quality issues are 1) the continuity and thickness uniformity of the BOX, 2)

thickness uniformity of silicon device layer and 3) level of defects in silicon layer. Important BOX

defects include voids and inclusions while defects in the silicon top layer include threading

dislocations and pits. Also, the interface charge trapped at the interface of the top silicon layer

and the BOX must be kept small since it tends to shift the threshold voltage from the desired

value and affects electrical behavior of the device. As the CMOS technology scales, the

requirement for thinner and thinner silicon films also becomes a concern and a challenge for

present SOI fabrication processes.

7

1.6 References [1] D. K. Sadana and M. Current, “Fabrication of Silicon‐On‐Insulator (SOI) Wafers Using Ion Implantation”, in Ion Implantation Science and Technology, Edited by J. F. Ziegler, Ion Implantation Technology Co., 2000, p. 341‐374. [2] International Technology Roadmap for Semiconductors 2005 Edition (http://www.itrs.net/Links/2005ITRS/Home2005.htm) [3] Chris Hall, “Soitec moves ahead in SOI,”DigiTimes.com, Taipei, Tuesday 13 September 2005 [4] http://www.ibm.com/developerworks/library/pa-pek/ [5] G. A. Brown, P. M. Zeitzoff, G. Bersuker, and H. R. Huff, “Scaling CMOS: materials and devices,” Materials Today, p. 20‐25, Jan 2004 [6] G.G. Shahidi et al, “A room temperature 0.1um CMOS on SOIʺ, IEEE Trans. Electron Devices 41 (1994) 2405. [7] S. Cristoloveanu and S.S. Li, Electrical Characterization of SOI Materials and Devices, Kluwer, Norwell (1995). [8] R. Berger, J. Burns, C‐L Chen, C. Chen, M. Fritze, P. Gouker, J. Knecht, A. Soares, V. Suntharalingam, P. Wyatt, D‐R Yost, Craig L. Keast, “Low power, high performance, fully depleted SOI CMOS technology,” DARPAJMTO AME Review, 31/8/1999 [9] M. I. Current, S. W. Bedell, I. J. Malik, L. M. Feng, F. J. Henley, “What is the future of sub‐100nm CMOS: Ultrashallow junctions or ultrathin SOI?” Solid State Technology, Vol. 43, September, 2000. [10] J. P. Colinge, X. Baie, V. Bayot, and E. Grivei, “A silicon‐on‐insulator quantum wire,” Solid State Electron., vol. 39, no. 1, pp. 49–51, 1996. [11] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. Hu, “Sub 50 nm FinFET: PMOS,” in IEDM Tech. Dig., 1999, pp. 67–70. [12] Z. Jiao and C. A. T. Salama, “A fully depleted‐channel SOI nMOSFET,” in Proc. Electrochem. Soc. 2001–3, 2001, pp. 403–408. [13] J. P. Colinge, M. H. Gao, A. Romano‐Rodriguez, H. Maes, and C. Claeys, “Silicon‐on‐insulator gate‐all‐around device,” in IEDM Tech. Dig., 1990, pp. 595–598. [14] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A fully depleted lean‐channel transist or (DELTA)‐a novel vertical ultra thin SOI MOSFET,” in IEDM Tech. Dig., 1989, pp. 833–836. [15] C. P. Auth and J. D. Plummer, “A simple model for threshold voltage of surrounding‐gate MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 2381–2383, Nov. 1998. [16] J. T. Park, J. P. Colinge, and C. H. Diaz, “Pi‐gate SOI MOSFET,” IEEE Electron Device Lett., vol. 22, pp. 405–406, Aug. 2001. [17] H.‐S. P. Wong, K. K. Chan, and Y. Taur, “Self‐align (top and bottom) double‐gate MOSFET with a 25 nm thick silicon channel,” in IEDMTech. Dig., 1997, pp. 427–430. [18] J. P. Denton and G. W. Neudeck, “Fully depleted dual‐gated thin‐film SOI P‐MOSFET’s fabricated in SOI islands with an isolated buried polysilicon back gate,” IEEE Electron Device Lett., vol. 17, pp. 509–511, Nov. 1996. [19] J.‐T. Park and J.‐P. Colinge, “Multiple‐gate SOI MOSFETs: Device design guidelines,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222‐2229, Dec. 2002. [20] R.A.McKee, F.J.Walker, and M.Chisholm, Phys. Rev. Lett. 81 (1998) 3014. [21] J.Lettieri, J.H.Haeni, and D.G.Schlom, J. Vac. Sci. Technol. A 20(4) (2002) 1332‐1340. [22] S. Cristoloveanu, A review of the electrical properties of SIMOX substrates and their impact on device performance. J Electrochem Soc 138 (1991), p. 3131

8

Chapter 2 Floating Epitaxy SOI 2.1 Motivation for Research In order to meet the ever increasing demand for high speed and low power consumption, devices

continue to shrink in physical dimensions. As devices scale below 100nm gate length, silicon

body needs to be thinner and thinner. Two dimensional device simulations in [1] show that, the

relationship Lg/TSi ≈5 between gate length, Lg and silicon body thickness, TSi is needed for FDSOI

devices to suppress short channel effects (SCEs). This means, for sub‐50nm devices, silicon body

needs to be less than 10nm thick. The buried oxide (BOX) thickness needs to scale as well to give

more options for controlling the SCEs and improve subthreshold slope. [2] For substantive

reduction of SCEs, BOX thickness needs to be less than 25nm. [3][4] Thus, from device

performance perspective, thin silicon film and BOX thickness are required. At the same time, the

silicon film needs to be a single crystal film of good quality and free from defects. This creates a

challenge to the present day SOI fabrication processes. Ibis Technology Corporation reports that

typical SOI parameters for SIMOX wafers are 10‐145nm silicon film thickness and a 145nm thick

buried oxide. [5] SOITEC, the manufacturer of Smart Cut™ wafers, currently produces SOI wafer

with silicon thickness of 50nm‐100nm and uniformity of +/‐5nm, and buried oxide thickness of

50nm‐145nm +/‐5nm. [6] Neither of the two meets the specifications for silicon film and BOX

thickness for this year, set by International Technology Roadmap for Semiconductors. [7] Thus,

current SOI manufacturing processes based on wafer bonding and ion implantation do not

guarantee continued silicon layer thinning and appropriate thickness control. Besides, there are

material issues and problems. Shallow implantation to produce thin silicon films results in

defects in silicon. The disadvantage with SIMOX technique is that implanted oxygen ions cause

damage to silicon device layer. In order to repair the damage, a high temperature anneal is

necessary which increases processing steps. A low dose of oxygen guarantees a thin BOX but

quality of oxide degrades. Wafer bonding techniques have the difficulty of appropriate thickness

9

control. Annealing is required for bonded wafers, to allow wafer splitting, and the distribution of

hydrogen atoms can result in uneven splitting and a need for wafer polishing. The combination

of implantation, annealing, and polishing steps required to make SOI wafers by current SOI

manufacturing processes renders the manufacturing very expensive. According to [8] SOI

manufacturing invloves per 300mm wafer cost of ~$1200, compared to the bulk silicon wafer cost

of $200‐$250. The need of today is a SOI fabrication process that is capable of producing defect‐

free and thin silicon films and at the same time allows a lower cost of production thereby

promoting the use of SOI in the semiconductor industry.

2.2 Floating Epitaxy SOI – A Novel Approach “Floating Epitaxy” SOI is a novel approach proposed by Angus Kingon, Jon‐Paul Maria, and

Veena Misra to achieve good quality thin silicon film, designed so as to allow SOI to meet the

long‐term ITRS specifications and make SOI technology advantageous from device performance

and cost of production perspectives. The concept is illustrated in Figure 2‐1. An epitaxial oxide is

grown on silicon substrate and is used as a template to deposit epitaxial silicon on top. Epitaxial

deposition of silicon will make possible to produce thin films with good thickness control, less

defects and negate the need for post‐processing anneal or polishing.

Figure 2-1 Cross-section of Floating Epitaxy SOI substrate [9]

A thin layer of epitaxial oxide, which is crystalline in nature and closely lattice‐matched to

silicon, is deposited on silicon substrate by molecular beam epitaxy process. This layer is rather

thin to keep the layer commensurate and avoid misfit dislocations and relaxation as much as is

feasible. The structure is heated in presence of oxygen, to allow oxygen to diffuse through the

template oxide and form SiO2 at the silicon interface, effectively “floating” the still‐epitaxial

template oxide on top of an amorphous insulating layer. Once the insulating layer is sufficiently

10

thick, silicon is deposited under UHV conditions on the template layer, completing the SOI

substrate structure. By this process, it is easier to produce thin rather than thick layers of silicon

and buried oxide, making Floating Epitaxy SOI an especially viable solution for the future

technology generations requiring thin SOI films for better device performance

2.3 Choice of Epitaxial Oxide Good progress has been made in the processing of epitaxial oxides on silicon. Materials studied

include complex oxides deposited with an alkaline earth oxide template, or direct deposition of

oxides such as Y2O3, Pr2O3, Gd2O3, CeO2, MgO and simple solid solution such as (LaxY1‐x)2O3.

[10][11][12] However, for the floating epitaxy SOI, the choice of epitaxial oxide depends largely

on the lattice parameter. The oxide should be as closely lattice‐matched to silicon as possible for it

to act as a template for growing silicon on top. However, the final choice of oxide will depend on

experimental growth and temperature stability results. A graph comparing the lattice parameter

of several candidate oxides with that of silicon over the temperature range of interest is shown in

Figure 2‐2. For graphing purposes, an average of the a‐ and b‐lattice parameters is used.

Figure 2-2 Comparison of lattice parameter mismatch to silicon over a temperature range [9]

11

Several crystal structures are considered: cubic rock‐salt structures (BaO, SrO), cubic and

pseudocubic perovskites (SrTiO3, CaTiO3, LaAlO3), and bixbyite structures (Sm2O3, Ho2O3,

Dy2O3). While pure oxides may not lattice‐match with silicon very well, the solid‐solution

combination of these pure oxides yields a lattice parameter rather close to silicon, for a given

temperature‐for example Ba0.64Sr0.36O, a solid solution of BaO and SrO. Out of several explored

template oxides, LaAlO3, SrTiO3 or a stack of LaAlO3 over SrTiO3 is found useful for Floating

Epitaxy SOI.

2.4 Floating Epitaxy SOI Advantages The most important advantage of floating epitaxy process is the possibility of making ultra thin

silcon films on top of thin buried oxide. This is a very attractive feature to the scaling needs of

coming technology generations. Epitaxial deposition of silicon also assures a good quality device

layer. Moreover, the need for post‐processing annealing or polishing is avoided. With fewer

fabrication steps involved, the novel process also guarantees a cost reduction in SOI

manufacturing. If it comes through successfully, Floating Epitaxy will supersede the SIMOX and

Smart‐Cut techniques and become the prime SOI manufacturing process.

2.5 Thesis Goal The work in this thesis involves modeling ultra thin body fully‐depleted MOSFET based on

Floating Epitaxy SOI and determining the viability of this novel substrate in terms of device

electrical performance. Since, UTB SOI MOSFET is the device of choice for sub‐100nm MOSFETs;

it is of interest to investigate the device performance based on Floating Epitaxy SOI. A concern

from device performance perspective is that most of the candidate epitaxial oxides are high‐k

oxides. While SrO has k=13, BaO has k=34. While LaAlO3 has k=26, SrTiO3has k=300.

Traditionally, it has been shown that a high permittivity of buried oxide degrades device

performance by introducing additional short channel effects. The aim of this work is to

determine if the Floating Epitaxy based UTB SOI device, irrespective of high‐k buried oxide, is

capable of meeting the ITRS specifications in terms of the off‐state leakage current, Ioff and more

importantly Ion/Ioff ratio where Ion is the drive current. The goal of thesis is to study the impact

of device design parameters on performance of UTB SOI device at different gate‐lengths and to

re‐engineer the device structure and parameters so as to meet the ITRS projections down to 10nm

12

gate length. UTB SOI device is the focus of this work as against multiple‐gate device because of

the challenges associated with fabrication of the latter. This work explores the device design

issues related with sub‐100nm SOI devices.

2.6 Thesis Organization

Chapter 3 describes device modeling of UTB FDSOI device based on Floating Epitaxy SOI. The

device design parameters are discussed. Chapter 4 describes how strain in silicon channel is

modeled in device simulations and the impact of strain on device performance. Chapter 5

describes initial device simulation and defines the problem. Chapter 6 discusses in detail the

concept of ground‐plane in suppressing short channel effects. Chapter 7 discusses other

alternatives such as silicon body thinning, back‐gate bias effect and gate workfunction

engineering and their role in controlling short channel effects and setting the threshold voltage.

Chapter 8 discusses buried layer engineering and its role in suppressing short channel effects. It

also highlights interesting facts about the role of buried oxide permittivity at thick and thin BOX.

Chapter 9 deals with device design optimization and highlights separately the device design

parameters at which the ITRS Ion/Ioff specification is met for every gate length. I conclude my

work finally with Chapter 10 describing future work that can be done to demonstrate the

functionality and advantages of UTB SOI device based on novel Floating Epitaxy approach.

2.7 References [1] V. P. Trivedi and J. G. Fossum, “Scaling fully depleted SOI CMOS,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2095–2103, Oct. 2003. [2] T. Numata, K. Uchida, J. Koga, and S. Takagi, “Device design for subthreshold slope and threshold‐voltage control in sub‐100 nm fully‐depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 2161‐2167, Dec. 2004 [3] A.Vandooren, D. Jovanovic, S. Egley, M. Sadd, B.‐Y. Nguyen, B. White, M. Orlowski, and J. Mogab, “Scaling assessment of fully‐depleted SOI technology at the 30 nm gate length generation,” in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 25–26. [4] V. P. Trivedi and J. G. Fossum, “Nanoscale FD/SOI CMOS: Thick or thin BOX,” IEEE Electron Device Lett., vol. 26, no. 1, pp. 26–28, Jan. 2005 [5] R.Dolan et al. 16th International Conference on Ion Implantation Technology 6/11‐13/06 (http://www.ibis.com/assets/pdf/iit‐2006‐characterization‐paper.pdf), accessed 7/13/06 [6] SOITEC Products Website (Ultra‐thin UNIBOND 1) [7] International Technology Roadmap for Semiconductors, 2005 Edition (http://www.itrs.net/Links/2005ITRS/Home2005.htm) [8] J.R.Sims, Jr. and R.N.Blumenthal. High Temperature Science 8 (1976) 99‐110.

13

[9] Jennifer Hydrick, PhD Thesis, Materials Science Engineering, NCSU, 2006 [10] J. Lettieri, J.H. Haeni and D.G. Schlom, J. Vac. Sci. Technol. A 20 (4), Jul/Aug 2002, pp. 1332‐1340 [11] V. Narayanan et al, Applied Physics letters, vol. 81, No. 22, 2002, pp. 4183‐4185 [12] J. Kwo et al, Applied Physics letters, vol. 77, No. 1, 2000, pp. 130‐132

14

Chapter 3 Device Modeling on Floating Epitaxy SOI 3.1 Introduction The advantages of Floating Epitaxy SOI are attractive from the perspective of producing thin

silicon and buried oxide films and reducing the processing steps involves thereby easing

manufacturing costs. However, it needs be investigated if the devices based on this novel

substrate will meet the electrical device performance expectations as specified by the

semiconductor roadmap. This chapter describes the device structure modeled on Floating

Epitaxy SOI, physical parameters for materials used and other device design features.

3.2 UTB Device Structure Figure 3‐1 shows cross‐section of a fully‐depleted UTB MOSFET based on Floating Epitaxy SOI.

Silicon body is thin and rests on top of template oxide. The insulator underneath silicon body

comprises of a thin layer of template oxide with SiO2 underneath. The device geometry and

features are discussed in following sections.

3.2.1 Silicon Body Silicon body thickness is 7nm or less. The choice of TSi<10nm is dictated by suppression of short

channel effects point of view as discussed in chapter 1. The silicon channel is doped 1E11cm‐3 that

is, it is virtually undoped. An advantage of SOI is that it permits device scaling with undoped

silicon body. High channel doping results in mobility degradation (which results in reduced

drive current) and dopant induced threshold voltage fluctuation. In order to avoid the above

problems, it is best to scale with undoped body to as small gate‐length dimension as possible.

15

Figure 3-1 UTB SOI MOSFET based on Floating Epitaxy SOI 3.2.2 Buried oxide The buried oxide comprises of a stack of thin template oxide over SiO2. The template thickness is

varied between 2nm and 5nm in accordance with results from experimental growth. The

template oxide is modeled with physical parameters corresponding to that of LaAlO3/SrTiO3

stack. Since LaAlO3 has permittivity, k=26, and SrTiO3 has k=300, the permittivity of stack would

vary between k=26 and k=300 depending upon the thickness of each layer. For modeling

purposes, the template oxide is assumed to have a permittivity value of k=28. The bandgap is

5eV. The SiO2 underneath has a permittivity, k =3.9. The total insulator thickness is at most 15nm

thick. The advantage of floating Epitaxy technique is that it is easier to fabricate thin buried oxide

films than thick.

3.2.3 Silicon Substrate The silicon substrate is p‐type and lowly doped 1E15cm‐3. A low substrate doping keeps body

effect low and also minimizes parasitic source/drain to substrate capacitances. On the other hand,

a high substrate doping is required to prevent latch up issues. A compromise between low and

high substrate doping is considered as an alternative to reduce short channel effects in chapter 6.

The back‐gate bias is varied and its effect on device performance and suppression of SCEs is

discussed in detail in chapter 7.

16

3.2.4 Gatestack The gate‐stack comprises of metal/high‐k. The gate oxide is HfO2 with permittivity, k=24. 5. The

thickness is 5.54A° which corresponds to an Equivalent Oxide Thickness (EOT) of 9A° as

projected by semiconductor roadmap for sub‐100nm devices. A high‐k gate dielectric is chosen as

it allows the gate oxide to be physically thicker for the sane gate oxide capacitance thereby

reducing the gate leakage current due to quantum mechanical tunneling. A metal/high‐k stack is

preferred over poly‐Si/high‐k stack because of higher resulting channel mobility. Moreover, a

metal gate solves the problem of poly‐silicon depletion associated with poly‐Si gate electrode. A

metal gate also allows for tuning the threshold voltage by gate‐workfunction engineering. The

workfunction is varied between 4.53eV and 5.45eV. For devices to scale with undoped silicon

body, metal workfunction engineering is needed to set the right threshold voltage to suppress

SCEs.

3.3 Modeling Setup The device structure is built using ‘MDRAW’ from Synopsys TCAD. Analytical profiles are used

to create n+ source/drain junctions. The dopant for source/drain diffusion is Arsenic and junction

doping is 1E21cm‐3. For channel and substrate, constant doping profile and boron dopant is used.

A commercial device simulator, Sentaurus Device (version X‐2005.10) from Synopsys (formerly

ISE‐TCAD) is used to perform two dimensional device simulations based on drift‐diffusion

transport mechanism. The ‘density gradient’ model is included which takes quantum effects into

consideration. For Id‐Vg simulations, gate voltage is swept from 0V to 1V. The drain is biased at a

maximum or power supply voltage of 1V. The models for mobility used for simulations have not

been calibrated with experimental results and are only as good as the TCAD software claims.

3.4 Conclusion The UTB SOI device structure based on Floating Epitaxy SOI was described. Before we simulate

devices of varying gate lengths and compare Ion, Ioff and Ion/Ioff ratio to ITRS projections,

another device modeling feature incorporated for all simulations needs to be discussed. That

feature is the addition of biaxial tensile strain to silicon channel in order to improve drive current.

Next chapter discusses strain and its effect on device performance in detail.

17

Chapter 4 Strained Silicon and Device Performance 4.1 Need for strained silicon As devices scale to nanoscale dimensions, alternatives in device design are being sought for to

suppress the short channel effects. Most of these come at the cost of reduced transistor

performance. According to Dennard’s principles for constant field scaling [1], the vertical

dimensions (gate oxide thickness, junction depth, depletion width) must scale along with lateral

dimensions (channel length). Sub‐100 nm devices therefore operate under very high transverse

electric field. Which is further expected to increase as scaling continues. The increase in the

vertical electric field severely degrades silicon channel mobility. [2] Mobility degradation leads to

reduction in Ion and undermines the much benefits of scaling. Another issue with short channel

devices is the requirement for a shallow junction depth or reduced silicon body thickness. For

45nm technology node, silicon body needs to be as thin as 10nm to suppress DIBL through it. A

thinner body adds to the series resistance of source and drain which hurts Ion and hence, device

performance. [3] A reduction in Ion translates to reduced operating speed. Therefore, as scaling

continues, innovations in device design are required to keep up the device performance. In this

regard, strained silicon is an attractive feature which boosts device performance. Under suitable

conditions, strain in silicon channel causes an increase in carrier mobility which not only results

in a larger Ion and speed but improves the otherwise unscalable subthreshold slope. Strain

improves both electron and hole mobility. The integration of strained silicon materials into the IC

manufacturing process is not very challenging. Most semiconductor companies like Intel and

Texas Instruments have switched to strained silicon based devices. In fact, at the present moment,

Silicon on Insulator (SOI) and Strained Silicon are the two key drivers of CMOS scaling. While

the former suppresses short channel effects and reduces leakage currents by means of reduced

parasitic capacitances, the latter enhances device performance.

18

4.2 Straining the Si Channel

Strain in silicon channel can be introduced either during processing known as process‐induced

strain or from the bottom by growing silicon on top of a crystalline template typically silicon with

20% or more germanium content, known as substrate‐induced strain.

4.2.1 Process-induced strain In process‐induced strain, stresses are created by films and structures that surround the

transistor. Stress can be induced during growth of oxides and silicides, etching and depositing

layers, and introducing dopants into the silicon. Stress can be beneficial or detrimental to the

nmos and pmos devices, depending on the stress pattern. In general, tensile stress improves

electron mobility and compressive stress improves hole mobility, so tensile stress is used for

nmos and compressive for pmos devices. Sources of stress include a nitride film on top of the

device [4] [5], the oxide in the nearby shallow trench isolation structure [6] [7], silicides and the

interlayer dielectric. For example, stress resulting from the standard shallow‐trench isolation

(STI) is known to enhance pmos performance by up to 20% while simultaneously degrading

nmos performance by about 15%. [8] The use of Si1‐xGex in the source/drain creates significant

uniaxial compression in the pmos channel whereas longitudinal uniaxial tensile strain is

introduced into the nmos channel by a silicon nitride‐capping layer as shown in Figure 4‐1 [5] [9]

[10].

4.2.2 Substrate-induced strain

In substrate‐induced strain, the most effective way to introduce high tensile strain to the channel

is to epitaxially grow strained silicon on a relaxed silicon germanium (SiGe) layer. Bulk silicon

and bulk germanium have different lattice constants, 5.43A and 5.65A respectively. The lattice

constant in the alloy Si1‐xGex is between that of Si and Ge and varies with Ge concentration as a(x)

= aSi + (1‐x) a Ge. If a thin silicon film is grown on top of Si1‐xGex, up to a critical thickness, Si lattice

follows the lattice of underlying substrate and gets stretched (or strained) in the plane of the

interface. This results in biaxial tensile strain in the channel as shown in Figure 4‐2. [11]

19

Figure 4-1 TEM micrograph of 45nm p-type and n-type MOS [10]

Figure 4-2 Formation of SiGe alloy and growth of strained Si on top [11]

Figure 4-3 Mobility enhancement ratio for strained Si n-MOSFETs [15]

20

The first strained Si n‐MOSFETs were fabricated on relaxed Si1‐xGex substrates with 30% Ge

content and provided about 70% electron mobility enhancement with a vertical effective electric

field up to 0.6 MV/cm [13]. At a lower gate bias, the current drive improvement over the

unstrained silicon MOSFETs is as large as 50%, while at a gate bias of 0.8 V, the current drive of a

strained Si device is about 35 % higher [14]. Figure 4‐3 shows both the experimental data and the

theoretical values of the phonon limited electron mobility enhancement versus the substrate Ge

content. [15] With the Ge content above 20 %, the mobility enhancement factor saturates near 1.8,

in agreement with calculations of the impact of strain on the mobility. Experiments also indicate

that for electrons, the strain induced mobility enhancement factor is relatively constant with

vertical electric field.

4.2.3 Uniaxial Vs Biaxial Strain

Unlike, process‐induced strain which is uniaxial, biaxial tensile strain enhances both electron and

hole mobilities. This is a major reason for commercialization of wafers based on strained silicon

on top of Si1‐xGex layer despite process complexities and huge cost. This is opposed to process

induced strain where both electron and hole mobilities respond oppositely to uniaxial tensile

strain. However, it has been observed that for most PMOSFETs, biaxially stressed Si

demonstrates near‐zero hole mobility improvement at large vertical electric fields [11] where

commercial MOSFETs operate. Fischetti et al. showed that the loss in hole mobility enhancement

at higher fields was due to reduction in the separation between the light hole and heavy hole

bands (ΔLH‐HH) [16]. Based on the experimental data, it was speculated that this was due to the

confining surface potential operating against the applied biaxial stress and trying to reduce the

separation between the LH and HH bands. [16] On the other hand uniaxially stressed

PMOSFETs, however, do not suffer from this performance problem. [10] The use of uniaxial

stress for CMOS technology is not without its own complexities and so trade‐off exists as the

strained‐silicon technology evolves.

4.3 Mobility Enhancement The theory of mobility enhancement in strained silicon is still evolving. The most commonly

accepted explanation is that under the biaxial tensile strain, the six‐fold degenerate valleys in Si

are split into two groups. The group with the lower energy is two fold degenerate (labeled as Δ2

21

in Figure 4‐4), which is the primary contributor to carrier transport at low fields. The in‐plane

effective mass of the electrons occupying these bands is approximately equal to the Si transverse

effective mass (mt* =0.19m0). On the other hand, the effective mass perpendicular to the transport

plane is equal to the longitudinal effective mass (ml* =0.92m0). The schematic representation of

the energy ellipses is shown in Figure 4‐4. The energy of the conduction‐band minima of the four

valleys on the in‐plane <100> axes rises with respect to the energy of the two valleys on the <100>

axes perpendicular to the plane [17], as shown in Figure 4‐5 (a) [18]. The energy between the two‐

fold degenerate and the four‐fold degenerate valleys, ΔEstrain, is given by ΔEstrain = 0.67x eV, where

x is the Ge content of the relaxed Si1‐xGex substrate [19]. It should be noted that even in an

unstrained Si MOS inversion layer there is band splitting between the sub‐band energies in the

two and the four‐fold valleys due to quantization in the inversion layer. In a strained Si MOS

inversion layer, the band splitting of the conduction band ΔEstrain is superimposed on this

quantization, as schematically shown in Figure 4‐5 (b) [18]. The electrons populate the lower Δ2

valleys with lighter effective mass, which results in the reduction of the average conductivity

effective mass.

The other mechanism of mobility enhancement proposed by Takagi et al. [18] is the suppression

of intervalley phonon scattering due to the energy splitting between the two fold and the four

fold valleys. In unstrained material, the valence band maximum is composed of three bands: the

degenerate heavy‐hole (HH) and light‐hole (LH) bands at k=0, and the split‐off (SO) band which

is slightly lower in energy, as shown in Figure 4‐6 [20]. The biaxial stress can be resolved into a

hydrostatic and a uniaxial stress component. The hydrostatic stress equally shifts all three

valence bands, while the uniaxial stress lifts the degeneracy between LH and HH bands by lifting

the LH band higher than HH. The SO band is also lowered with respect to the other two bands.

This leads to the population of holes in the energetically favorable LH like band. Application of

stress also changes the shape of the bands as shown in Figure 4‐6 (b). Therefore, due to the band

deformation, the in‐plane transport mass becomes smaller and the interband scattering is also

suppressed. Thus the hole mobility is improved.

The main difference between the effects on electron and hole mobilities is that the mobility of

holes can be enhanced only at lower electric fields while the enhancement can be achieved at

higher vertical electric fields for electrons. Fischetti et al. showed that the loss in hole mobility

22

Figure 4-4 Strain induced conduction band splitting in silicon [11]

Figure 4-5 Energy alignment of the Si conduction band with and without the tensile strain [18]

Figure 4-6 Simplified hole valence band structure for longitudinal in plane direction [20]

23

enhancement at higher fields was due to reduction in the separation between the light hole and heavy hole bands (ΔLH‐HH) [16].

4.4 Strained Silicon-on-Insulator Strained Si‐on‐insulator MOSFETs can be fabricated from strained silicon grown on relaxed Si1‐

xGex ‐on insulator (SGOI) substrates [20]. SGOI can be achieved via several approaches such as

“etch‐back” and “smart‐cut” processes [20], SIMOX technology [21] and Ge condensation

techniques. [22] The presence of the SiGe layer in strained‐silicon substrate leads to several

challenges related to materials and integration, such as a high density of defects in strained

silicon on relaxed SiGe induced by the strain relaxation in SiGe and a substantial difference in

doping diffusion property in SiGe. (Boron diffusion is retarded, whereas arsenic diffusion is

enhanced as compared with the diffusion in silicon.) Such challenges require additional efforts in

junction engineering to control SCEs and to set the device threshold voltage to the desired value.

Substantial device self‐heating is also observed in strained silicon/SiGe devices because of the

lower thermal conductivity in SiGe. Recently, Rim et al. [23] demonstrated transistors using ultra

thin strained silicon directly on insulator (SSDOI) structures that eliminate the SiGe layer before

transistor fabrication, thereby providing higher mobility while mitigating the SiGe‐induced

material and process integration problems. An SSDOI structure is fabricated by a layer‐transfer

or ʺwafer‐bondingʺ technique. First, an ultra thin layer of strained silicon is formed epitaxially on

a relaxed SiGe layer, and an oxide layer is formed on top. After hydrogen is implanted into the

SiGe layer, the wafer is flipped and bonded to a handle substrate. A high‐temperature process

splits away most of the original wafer and leaves the strained‐silicon and SiGe layers on top of

the oxide layer. The SiGe is then selectively removed and transistors are fabricated on the

remaining ultra thin strained‐silicon. A fabricated SSDOI device structure is shown in Fig. 3 A.

Both electron and hole mobility enhancement have been observed, which indicates that strain is

retained after the device‐processing steps have been completed [23].

4.5 Modeling Strain in this work The crystalline oxide used as template for growing silicon on top is closely lattice matched to

silicon. While LaAlO3 has a lattice parameter of 3.8Aº, SrTiO3 has lattice parameter of 3.9Aº as

opposed to 5.43Aº of silicon. There is evidence that when SrTiO3 and LaAlO3 are grown on Si,

24

then the SrTiO3 or LaAlO3 cube rotates 45° with respect to the Si cube, so the ʺeffectiveʺ lattice

mismatch with Si is small. This is because the effective lattice parameter will now be sqrt (2) times

the actual value. For this reason when Si is grown on top of SrTiO3 it will see a lattice parameter

of 5.5Aº which is larger than 5.43A and therefore if the template is relaxed, silicon will get tensile‐

strained. The strain component would be similar to one that results when silicon is grown on top

of relaxed SiGe. Strain in this novel substrate will be advantageous over that in SiGe based

substrates since much of the problems associated with SiGe buffer layer will be eliminated.

The silicon body is therefore modeled to be under biaxial tensile strain. Modeling is done using

Sentaurus Device from Synopsys. A material called ‘StrainedSilicon’ is used for the silicon body

and a corresponding parameter file ‘strainedsilicon.par’ is used. The amount of strain added to

silicon channel is same as that would result in silicon grown over SiGe alloy with 20% Ge content.

The strain is assumed to be constant irrespective of the template layer thickness. Also the strain

has not been calibrated with experimental results. The strain‐dependent mobility model used is

only as good as claimed by the TCAD software. The device simulations therefore will

characterize a strained‐silicon on insulator device. In order, to see the effect of modeled strain on

device performance, simulations are performed and discussed in next section.

4.6 Simulation Results In this section, the strain modeled in the silicon channel is characterized. In order to establish the

effect of strain on the device performance, simulations are done with and without strain in the

silicon channel and the pros and cons of adding strain are analyzed.

4.6.1 Simulation Setup

The device structure is same as discussed in Chapter 3. The silicon body is 7nm thick and

undoped. The gate‐stack consists of metal‐gate/HfO2. The metal workfunction is 4.53eV. EOT for

gate oxide is 9Aº. The template is 5nm thick with a dielectric constant of k=28. The SiO2

underneath is 15nm thick. The source and drain are n+ doped with concentration 1E20 cm‐3. The

substrate is p‐type and lowly doped 1E15cm‐3. The source and substrate are tied to ground. Drain

is connected to supply voltage of 1V.

25

4.6.2 Strain and Drive Current

Figure 4‐7 shows the Id‐Vg curves for a 25nm gate‐length device. On‐state current, Ion, for a

device with strained channel is 1.87mA/um compared to 1.69mA/um for the device without

strain in channel. At this gate length, strain results in 11% increase in drive current. Figure 4‐8

shows the Id‐Vg curves for a 15nm gate‐length device. On‐state current, Ion, for a device with

strained channel is 3.16mA/um compared to 2.59mA/um for the device without strain in channel.

At this gate length, strain results in 22% increase in drive current. Figure 4‐9a plots the drive

current for different channel lengths. Since, Ion is inversely proportional to gate length; it

increases as channel length decreases. The benefit of adding strain is visible at every gate length

as a higher value of Ion.

4.6.2 Strain and Leakage Current

From Figure 4‐7 and Figure 4‐8, it can be seen that off‐state leakage current defined as the drain

current at zero bias is also significantly larger for the device with channel under strain. For 25nm

device, while Ioff for device with strained silicon is 1.03E‐4A/um, it is 5.06E‐5A/um for device

without strained channel. For 15nm gate length, Ioff is 8.97E‐4A/um for device with strained

silicon and 5.73E‐4A/um for device without strained silicon. Thus, the enhancement in drive

current with strain in channel comes at the cost of increased leakage current. Figure 4‐9b plots the

Ioff versus gate length. As channel length decreases, Ioff increases because of increased proximity

of source and drain and added short channel effects such as drain‐induced barrier lowering

(DIBL). Device with strain in silicon channel results in a larger Ioff at every gate length compared

to device without strained channel.

4.6.2 Strain and Threshold Voltage

The increase in the Ioff by adding strain to silicon channel can be explained by a decrease in the

threshold voltage. Figure 4‐10a plots the saturation threshold voltage of the device with and

without strain in silicon channel versus the gate length. As can be seen, strain results in a

decrease in threshold voltage. Since Ioff varies exponentially with threshold voltage, Ioff

increases as channel length decreases. The smaller Vt of devices with strain is a major concern for

device design. Since, it requires more stringent conditions for to set the threshold voltages to a

level desired and thereby mitigate short channel effects.

26

a) b)

Figure 4-7 Id-Vg curves for Lg =25nm with and without strain in Si channel a) linear b) log scale

a) b)

Figure 4-8 Id-Vg curves for Lg =15nm with and without strain in Si channel a) linear b) log scale

27

The threshold voltage is lower for strained Si due to its smaller bandgap (commonly assumed),

electron affinity change and band offset between SS and SiGe. The narrowing of bandgap is given

by,

ΔEg (SS) = Eg (Si) – Eg (SS) = 0.4x (eV) [24][25]

The shift in Vt of a NMOS device due to strain is given as [26],

ΔVt (SS) = ‐ΔEc – (m‐1) ΔEg (SS) + (m‐1) (kT/q) ln (Nv‐Si / Nv‐SS )

where –ΔEc = χSi – χSS represents conduction band lowering in the SS and m is the body‐effect

coefficient with value between 1.3 and 1.4 for nanoscale devices

4.6.3 Strain and Drain-Induced barrier Lowering

Figure 4‐10b plots drain‐induced barrier lowering (DIBL) versus the channel length. DIBL is

measured as the difference in measured threshold voltage at drain bias of 0.1V and 1V. As can be

seen, strain doesn’t affect DIBL. Even though strain lowers the threshold voltage, it doesn’t

impact DIBL. It has been shown in [27] that strain doesn’t worsen the short channel effects. What

causes a lower DIBL in strained‐Si on SiGe substrates is the difference in permittivity of silicon

and SiGe. However, if SiGe is assumed to have same permittivity as that of Si, the two devices

with and without strain would result in same DIBL which is inline with what Figure 4‐10b

suggests.

4.7 Conclusion

From performance perspective, strained silicon channel is advantageous as it results in an

increased drive current. However, because of band splitting that occurs, threshold voltage is

lowered. This results in an increase in the off‐state leakage current. Threshold voltage is an

important device parameter and its control becomes more critical for strained silicon based

devices. Generally an increase in threshold voltage is needed to bring the down the off‐state

current to a level desired. Since, Vt of strained‐silicon devices is lower, more stringent control of

Vt is required. It has been shown that strain doesn’t affect DIBL. However, when it comes to

achieving an ITRS projected leakage current value; a lower Vt does pose a greater device design

challenge.

28

a) b)

Figure 4-9 a) Ion and b) Ioff versus channel length for device with and without strain in Si channel

a) b)

Figure 4-10 a) Threshold voltage and b) Drain induced barrier lowering (DIBL) versus channel length for device with and without strain in Si channel

Ion Vs Channel Length

0

1

2

3

4

5

6

10nm 15nm 25nm 30nm 45nm 60nm

Channel Length

Ion

(mA

/um

) unstrained Si

strained Si

Ioff Vs Channel Length

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02


Channel Length

Ioff

(A/u

m)

strained Si

unstrained Si

Threshold Voltage Roll Of Trend

0

0.1

0.2

0.3

0.4

0.5

0.6

0 20 40 60 80

Channel length (nm)

Thre

shol

d Vo

ltage

(V)

unstrained Sistrained Si

DIBL Effect

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

10 100 1000

Channel Length (nm)

Vt s

hift

(V) unstrained Si

strained Si

29

4.8 References [1] H.‐S. Wong, D. Frank, and P. Solomon, “Device design considerations for double‐gate, ground‐plane, and single‐gated ultra‐thin SOI MOSFETʹs at the 25 nm channel length generation,” Proc. Int. Electron Devices Meeting, pp. 407, 1998. [2] L. Ge, J. G. Fossum, and B. Liu, “Physical compact modeling and analyses of velocity overshoot in extremely scaled CMOS devices and circuits,” IEEE Trans. Electron Devices, vol. 48, pp. 2074–2080, Sept. 2001. [3] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion‐implanted MOSFETʹs with very small physical dimensions,” IEEE J. Solid‐State Circuits, vol. SC‐9, pp. 256, 1974. [4] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoch, and T. Horiuchi, “Mechanical stress effect of etch‐stop nitride and its impact on deep submicron transistor design,” in IEDM Tech. Dig., 2000, pp. 247–250. [5] A. Shimizu, K. Hachimin, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical‐stress control (LMC): A new technique for CMOS,” in IEDM Tech. Dig., 2001, pp. 19.4.1–19.4.4 [6] R. Bianchi et al., “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” IEDM Tech. Dig., 2003, pp.117‐120 [7] Moroz et al., “The Impact of Layout on Stress‐Enhanced Transistor Performance,” Int. Conf. SISPAD, 2005, pp. 143‐146 [8] Moroz et al., “Analyzing strained‐silicon options for stress‐engineering transistors,” Solid State Technology, Jul2004, Vol. 47 Issue 7, p49‐52 [9] T. Ghani, et al., ʺA 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,ʺ Proc. IEDM, pp. 978–980, 2003. [10] S.E. Thompson, et al., ʺA Logic Nanotechnology Featuring Strained‐silicon,ʺ IEEE Electron Dev. Lett., Vol. 25, No. 4, pp. 191–193, 2004. [11] K. K. Rim, J. L. Hoyt, and J. F. Gibbons, ʺFabrication and analysis of deep submicron strained‐Si N‐MOSFETʹs,ʺ IEEE Transactions on Electron Devices, vol. 47, pp. 1406‐1415, 2000. [12] L. Geppert, “The Amazing Vanishing Transistor Act,” IEEE Spectrum, pp. 28‐33, vol. 39, no. 10, 2002. [13] J. Welser, J. L. Hoyt, and J. F. Gibbons, ʺNMOS and PMOS transistors fabricated in strained silicon/relaxed silicon‐germanium structures,ʺ Electron Devices Meeting, 1992. Technical Digest., International [14] H. S. P. Wong, ʺBeyond the conventional transistor,ʺ IBM Journal of Research and Development, vol. 46, pp. 133‐168, 2002 [15] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, ʺStrained silicon MOSFET technology,ʺ presented at Electron Devices Meeting, 2002. IEDM ʹ02. Digest. International, 2002. [16] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, ʺSix‐band k center dot p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness,ʺ Journal of Applied Physics, vol. 94, pp. 1079‐1095, 2003 [17] R. People, ʺPhysics and Applications of GexSi1‐X/Si Strained‐Layer Heterostructures,ʺ IEEE Journal of Quantum Electronics, vol. 22, pp. 1696‐ 1710, 1986. [18] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, ʺComparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal‐oxide‐semiconductor field‐effect transistors,ʺ Journal of Applied Physics, vol. 80, pp. 1567‐1577, 1996.

30

[19] T. Vogelsang and K. R. Hofmann, ʺElectron‐Transport in Strained Si Layers on Si1‐XGex Substrates,ʺ Applied Physics Letters, vol. 63, pp. 186‐188, 1993. [20] S. Takagi, N. Sugiyama, T. Mizuno, T. Tezuka, and A. Kurobe, ʺDevice structure and electrical characteristics of strained‐Si‐on‐insulator (strained‐SOI) MOSFETs,ʺ Materials Science and Engineering B‐Solid State Materials for Advanced Technology, vol. 89, pp. 426‐434, 2002. [21] D. Hisamoto, T. Kaga, Y. Kawarnoto, E. Takeda, IEDM Tech. Dig. 1989. [22] X. Huang et al., IEDM Tech. Dig. 1999, 67 (1999) [23] K. Rim et al., IEDM Tech. Dig. 2003, 49, (2003). [24] G. Armstrong and C.Maiti, “Strained‐Si channel heterojunction P‐MOSFETs,” Solid‐State Electron., vol. 42, pp. 487–498, Apr. 1998. [25] T. Numata et al., “Control of threshold voltage and short channel effects in ultra‐thin strained‐SOI CMOS,” in Proc. IEEE Int. SOI Conf., Sep. 2003, pp. 119–121. [26] W. Zhang and J. Fossum, “On the threshold voltage of strained‐Si‐Si1‐xGex MOSFETs,” IEEE Trans. Electron. Devices, vol. 52, no. 2, pp. 263‐268, 2005.

31

Chapter 5 Initial Device Design 5.1 Introduction This chapter describes the results of initial simulation of device based on Floating Epitaxy SOI or

epitaxial buried oxide. The goal of the simulation is to evaluate the device performance and to

know how far off the performance is from corresponding ITRS projection, for different channel

lengths. Also it is desirable to know how the device performs compared to the standard SOI

device. The chapter also helps to understand the effect of template layer thickness and channel

length on device performance. Accordingly, device parameters would be re‐modeled to suppress

short channel effects and achieve ITRS projected values.

5.2 Simulation Setup Figure 5‐1 shows the device based on the epitaxial buried oxide which is simulated. The template

thickness is varied from 5nm down to 2nm. The permittivity of template is assumed to be 28.0.

The thickness of SiO2 underneath the template is such that the total insulator thickness is constant

at 15nm. Since, the short channel effects are a function of buried oxide thickness, it’s best to keep

it constant so that the effect of template material and thickness becomes clear. The substrate is p‐

type and lowly doped with concentration 1E15cm‐3. The silicon body is 7nm thick and undoped.

The gate stack comprises of metal/HfO2. Metal Workfunction is set at 4.53eV. The silicon channel

is assumed to be under biaxial tensile strain as discussed in Chapter 4. For simulation, the source

and substrate are connected to ground. Drain is biased at 1V. The gate voltage is swept from 0V

to 1V and device parameters such as threshold voltage, off‐state current and on‐state current are

extracted from Id‐Vg plots. The channel length is varied from 60nm down to 10nm. The

performance of the epitaxial oxide based device (epi‐SOI) at every channel length is compared

with that of standard SOI device in Figure 5‐2. The standard SOI device has a uniform 15nm thick

SiO2 as buried oxide. Also, the silicon body is assumed to be under no added biaxial tensile

32

Figure 5-1 Epitaxial-oxide based SOI device (eSOI)

Figure 5-2 Standard SOI device or the ‘Core device’

33

strain. Other than this, the device architecture is the same. The device in Figure 5‐2 is referred to

as ‘core device’.

5.3 Simulation Results

Figure 5‐3 through Figure 5‐8 plot the threshold voltage, off‐state current (Ioff0 and on–state

current (Ion) as a function of template thickness for a range of channel length from 60nm to

10nm. The results are discussed in the following sections.

5.2.1 Template Thickness Effect The effect of template thickness on device performance is summarized below. 1. For all channel lengths, the threshold voltage increases as template thickness decreases. As

template thickness decreases, the thickness of SiO2 beneath increases. This is because total buried

oxide (BOX) thickness is a constant 15nm. Because SiO2 now comprises of a greater fraction of

BOX thickness the effective dielectric constant of the BOX is lowered. A lower permittivity

(lower‐k) BOX reduces the coupling of field lines from drain to channel via the BOX, thereby,

reducing the short channel effects. Consequently threshold voltage is higher. Figure 5‐9 shows

the potential contours in the buried oxide of a 30nm and 10nm epi‐SOI device with 5nm thick

template. As can be seen, the equipotential contours in the BOX are not parallel to body/BOX

interface and couple drain to channel. This bring back interface between the body and BOX

under conduction worsening DIBL. Reducing the BOX permittivity reduces this coupling and

improves short channel effects. More will be discussed on this in Chapter 8.

2. For all channel lengths, the off‐state current decreases as template is made thinner. This is due

to reduced short channel effects mainly DIBL through BOX and resulting increase in threshold

voltage.

3. The on‐state current decreases as template thickness decreases. This is because a larger Vtt

results in smaller Ion since Ion depends on Vt as (Vgs‐Vt)2

34

0.5

0.53

0.56

5nm 4nm 3nm 2nm

Template Thickness (nm)

Thre

shol

d Vo

ltage

(V)

epi-SOI

Core Vt = 0.551

1.0E-11

1.0E-10

1.0E-09

1.0E-085nm 4nm 3nm 2nm


Ioff

(A/u

m)

epi-SOI

Core Ioff = 7.48E-11A

0.85

0.88

0.91

0.94

0.97

5nm 4nm 3nm 2nmTemplate Thickness (nm)

Ion

(mA

) epi-SOICore Ion = 0.88mA

Figure 5-3 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for core and new device

0.47

0.49

0.51

0.53

0.55

5nm 4nm 3nm 2nm


Thre

shol

d V

olta

ge (V

)

epi-SOICore Vt=0.526

1.0E-10

1.0E-09

1.0E-08

1.0E-07



Ioff

(A/u

m)

epi-SOICore Ioff = 5.3E-10A

1.03

1.07

1.11

1.15

1.19


Ion

(mA) epi-SOI

Core Ion = 1.05mA


35

0.35

0.4

0.45

0.5


Thre

shol

d Vo

ltage

(V)

epi-SOICore Vt=0.474

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04



Ioff

(A/u

m)

epi-SOICore Ioff = 9.5E-8A

1.2

1.3

1.4

1.5

1.6

1.7

1.8


Ion

(mA)

epi-SOICore Ion = 1.34mA


0.25

0.33

0.41

0.49


Thre

shol

d V

olta

ge (V

)

epi-SOICore Vt=0.43

1.0E-06

1.0E-05

1.0E-04



Ioff

(A/u

m)

epi-SOI

Core Ioff = 1.87uA

1.4

1.5

1.6

1.7

1.8

1.9

2


Ion

(mA

)

epi-SOI

Core Ion = 1.51mA


36

2.9

3.6

4.3

5

5.7


Ion

(mA) epi-SOI

Core Ion = 3.71mA

2

2.4

2.8

3.2


Ion

(mA

) epi-SOICore Ion = 2.3mA

Figure 5-7 Lg = 15nm a) Ioff c) Ion versus Template Thickness for core and new device


1.0E-04

1.0E-03



Ioff

(A/u

m)

epi-SOI

Core Ioff = 0.27mA

1.0E-04

1.0E-03



Ioff

(mA

/um

)

epi-SOI

Core Ioff = 1.24mA

37

Figure 5-9a Equipotential Contours in 30nm epi-SOI device with 5nm thick template

Figure 5-9b Equipotential Contours in 10nm epi-SOI device with 5nm thick template

38

4. For any template thickness, the core device results in a larger threshold voltage and therefore a smaller

off‐state current and a larger on‐state current. Since the core device has SiO22 as buried oxide, the lower

permittivity of SiO2 results in lesser DIBL through Box and reduced short channel effects imply a higher

threshold voltage. The effect of BOX permittivity will be discussed in Chapter 8.

Figure 5‐10a plots threshold voltage versus template thickness for a whole range of channel lengths.

Figure 5‐10b and Figure 5‐10c do the same for Ioff and Ion respectively. Some key observations from

these plots are,

1. Vt increases almost linearly, for any channel length, as template is made thinner. The increase in Vt as

template thickness decreases from 5nm to 2nm, is more for short channel devices (Lg = 25nm and 30nm)

and lesser for longer devices (Lg=45nm and 60nm)

2. For a device with same template thickness, Vt is more for long channel devices and falls as channel

length decreases. For a device with same template thickness, say 5nm, the decrease in Vt as Lg reduces

from 60nm to 45nm is much smaller than the decrease in Vt as channel length reduces by the same

amount, 15nm from 45nm to 30nm. This is attributed to the threshold voltage roll‐off effect.

3. The decrease in Ioff with decreasing template thickness from 5nm to2nm, is more for long channel

devices (Lg = 45nm and 60nm) and lesser for shorter devices (Lg=25nm and 30nm). This is because Vt

falls rapidly for shorter devices therefore Ioff increases less rapidly. The fact that Ioff is nearly constant for all template thicknesses for 10nm and 15nm channel length devices shows that Vt changes more

rapidly with template thickness for these lengths.

4. For a device with same template thickness, say 5nm, Ioff increases as channel length reduces. The

increase per 5nm decrease in channel length is larger for longer channel devices and smaller for short

channel devices. Since Vt fall more rapidly for short channel length devices, Ioff increases slowly for short

channel devices and rapidly for longer channel devices. For this reason, the increase in Ioff as channel

length decreases from 30nm to 25nm is more as compared to the increase as channel length decreases fall

from 15nm to 10nm.

39

0.25

0.3

0.35

0.4

0.45

0.5

0.55

5nm 4nm 3nm 2nm

Template Thickness

Thre

shol

d Vo

ltage

(V)

Lg = 60nmLg = 45nmLg = 30nmLg = 25nm

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1.0E+005nm 4nm 3nm 2nm


Ioff

(A/u

m) Lg = 60nm

Lg = 45nmLg = 30nmLg = 25nmLg = 15nmLg = 10nm

a) b)

0

1

2

3

4

5

6

5nm 4nm 3nm 2nm


Ion

(mA

)

Lg = 60nmLg = 45nmLg = 30nmLg = 25nmLg = 15nmLg = 10nm

c)

Figure 5-10 a) Threshold Voltage b) Off-state current and c) on-state current versus Template Thickness

40

5.2.2 Channel Length Effect

Figure 5‐11 plots the variation of threshold voltage, off‐state current and on state current

respectively with channel length. Threshold voltage falls more rapidly at short channel lengths

because of Vt‐roll off effect. The difference between Vt for different template thicknesses becomes

more for short channel devices. For this reason, the off‐state current doesn’t change much with

template thickness for 10n and 15nm devices. Both Ioff and Ion increase as channel length

decreases. The change in Ion with change in template thickness is very small. The change in Ioff

with change in template thickness becomes small only at small channel lengths.

5.2.3 ITRS and Device Performance

Figure 5‐12 plots Ioff and Ion for different channel lengths and compares it with ITRS High

Performance Logic projected values. The parameter on x‐axis is the device physical gate length

and for long channel devices older versions of ITRS were used to obtain the performance

projections. The ultimate goal is to achieve ITRS projections for all channel lengths and engineer

the device accordingly. Instead of Ion or Ioff, Ion/Ioff ratio is a better metric for evaluating device

performance. The Ion/Ioff ratio is plotted in Figure 5‐13s. The key observation is that for 60nm

and longer channel length devices, the epitaxial oxide based device under investigation meets the

ITRS requirements for Ion/Ioff ratio irrespective of the template thickness. For 45nm channel

length, ITRS projections are met except for 5nm thick template. However, as channel length scales

below 45nm, device performance is off from ITRS projection by a big margin for all template

thicknesses. The device below 45nm therefore, needs to be re‐engineered to meet ITRS

projections.

5.4 Conclusion and Next

A thinner template yields a smaller Ioff and is better suited to meet ITRS requirements. However,

for very small channel lengths, 15nm and below, the effect of template thickness becomes less

and performance for different template thicknesses becomes comparable. The epitaxial‐oxide

based device performs worse than standard SOI device because of a larger thickness and smaller

permittivity of SiO2. The device under investigation meets the ITRS projections for 60nm channel

41

0.05

0.15

0.25

0.35

0.45

0.55

15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

Thre

shol

d Vo

ltage

(V)

5nm4nm3nm

2nmCore Device

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-0210nm 15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

Ioff

(A)

5nm4nm3nm2nmCore Device

a) b)

0

1

2

3

4

5

6


Channel Length (nm)

Ion

(mA

)

5nm4nm3nm2nmCore Device

c)

Figure 5-11 a) Threshold Voltage b) Off-state current and c) on-state current versus Channel Length

42

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-0210nm 15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

Ioff

(A/u

m)

5nm4nm3nm2nmITRS HP

0

1

2

3

4

5

6


Channel Length (nm)

Ion

(mA)

5nm4nm3nm2nmITRS HP

Figure 5-12 a) Ioff b) Ion comparison with ITRS High Performance Logic Projections

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07


Channel Length (nm)

Ion/

Ioff

5nm4nm3nm2nmITRS HP

Figure 5-13 Comparison of device Ion/Ioff ratio and ITRS High Performance Logic projections

43

length device however below 45nm regime; there is a big offset from projections for any template

thickness. Thus, device design parameters such as silicon body thickness, buried oxide thickness,

gate workfunction and others must be re‐engineered to suppress short channel effects and meet

ITRS requirements for sub‐45nm channel length devices. In the following chapters, device

alterations to reduce short channel effects will be investigated.

44

Chapter 6

Ground Plane Concept 6.1 Introduction From previous chapter we have seen that for SOI device to scale below 45nm gate length, short

channel effects need to be suppressed. The ultimate SOI device would be a double‐gate or

multiple‐gate device. However because of the processing issues involved, these devices are hard

to fabricate. A ground‐plane device is a compromise between the single‐gate and double‐gate

device and effective in suppressing short channel effects. This chapter describes the concept and

advantages of ground‐plane device. The ground‐plane device is simulated for the whole range of

channel length and reduction in off‐state leakage current and improvement in Ion/Ioff ratios is

highlighted.

6.2 Ground Plane Concept A major cause of short channel effects in sub‐100nm fully depleted SOI devices is attributed to

the fringing electric field lines in the buried oxide and substrate (Figure 6‐1). [1] The biasing of

drain causes field lines emanating from drain. While the channel is shielded from these field lines

at the top by the gate electrode, the field lines penetrate laterally through the body and from

underneath through the buried oxide and underlying substrate. The field lines through the

buried oxide and substrate couple the drain to body potential and cause parasitic back‐channel

conduction. There occurs a peak in the potential at body/BOX interface and a potential rise in

substrate as well. [1][2] The back channel is driven from depletion to weak inversion and due to

interface coupling the threshold voltage is lowered. This degrades subthreshold slope and results

in severe drain‐induced barrier lowering. According to [2] the effect is referred to as ‘drain

induced virtual substrate biasing’ where drain acts a positively biased back‐gate. Figure 6‐2

shows fringing field lines in the buried oxide, which are highly deformed and not parallel to the

body/BOX interface. It is indicative of the fact that the back channel potential is governed by the

45

Figure 6-1 Schematic of fringing fields in SOI device [3]

Figure 6-2 Electrostatic Potential Contours in the BOX and substrate of a SOI device [4]

Figure 6-3 Ground-Plane structures [1] [3] [6]

46

drain rather than the substrate. In other words, the 2D drain/source to body capacitances

dominates over the 1D body‐substrate capacitance. The drain influence on body potential can be

reduced by BOX thickness scaling or reducing the BOX permittivity. Both these effects will be

discussed in chapter 8 however the effect of both of them is enhanced by employing a ground‐

plane.

Ground‐plane has been proved effective in suppressing short channel effects [4] [5]. It refers to a

conducting surface beneath the buried oxide. Typically a single p+ implant located in the buried

oxide aligned with the gate‐oxide or two p+ implants located under the source and drain serve as

ground‐plane structures (Figure 6‐3). The doping in ground‐plane electrode is at least 1E18cm‐3.

A highly conducting surface acts as an electric field stop and shields the fringing field lines from

drain from coupling to channel. When the substrate is lowly doped, depletion region in substrate

is large and adds to the effective buried oxide thickness. Employing a ground plane suppresses

substrate depletion and prevents drain‐induced conduction of back channel.

6.3 Ground Plane Vs Classical SOI Figure 6‐4 shows potential contours in fully depleted SOI device‐ classical SOI and ground‐plane

SOI device. The ground plane is located under the gate and results in reduced electric field

penetration in the buried oxide and sunstrate. Figure 6‐5 shows the electrostatic potential

variation along the vertical axis for 80nm SOI device with 20nm thick silicon film with and

without ground plane. The peak in potential in BOX and raise in potential in substrate occurs due

to fringing fields from drain. The peak is lowered and substrate potential is reduced by

employing a ground plane. Figure 6‐5b suggests that a combination of ground plane and thin

buried oxide completely suppresses the peak in potential and almost completely suppresses

DIBL through BOX. The first ground‐plane FDSOI [7] was fabricated on a 140nm long device

with 150nm thick BOX and 80nm thick silicon film. The substrate concentration was 1E15cm‐3 and

ground plane was doped 5E18cm‐3. The key processing steps are shown in Figure 6‐6. After

forming the shallow trench isolation a dummy nitride gate is formed and PSG is deposited. CMP

is used to form an inverse print of the gate. The nitride is etched and boron is implanted to form

the self‐aligned ground plane. The nitride is removed and polysilicon deposition and CMP are

47

used to form the gate. The PSG is removed finally to allow for source and drain formation. Figure

6‐7

a)

b)

Figure 6-4 Equipotential contours in a 0.1mm long device with Vg = 0V and Vd = 1.5V. a) Device

without ground plane b) Device with ground plane in substrate under the gate [3]

48

Figure 6-5 Vertical potential profile in the middle of a 80-nm-long SOI MOSFET with conventional and GP configuration. BOX thickness is (a) 380 nm, (b) 50 nm. Si Film thickness is 20 nm [4]

Figure 6-6 Key processing steps: A: Nitride patterning, B: PSG Deposition and CMP, C: Nitride etch and Boron implant, D: Gate-Oxide growth, polysilicon deposition and CMP [7]

49

compares threshold voltage roll‐off and DIBL trend for the device with and without ground

plane implant. Figure 6‐7 shows the threshold voltage roll‐off and DIBL behavior for device with

and without ground plane implant. Significant reduction in DIBL is observed in case of the

ground plane device.

6.4 Ground Plane Simulation Setup Figure 6‐7 shows the device structure with ground‐plane implant in the BOX under the gate. The

device parameters are the same as in last chapter. Silicon body is 7nm thick and undoped. The

front gate EOT is 9A°. Gate stack consists of Metal/HfO2. The total buried oxide thickness is 15nm

and template thickness is varied. The ground‐plane is p+ doped to concentration 5E18cm‐3.

Substrate is lowly doped 1E15cm‐3 and connected to ground. Id‐Vg simulations are done with

drain biased at 1V. 6.5 Simulation Results

Figure 6‐8 plots vertical electrostatic potential across the center of silicon body for 25nm gate

length device with and without the ground plane. Figure 6‐9 plots the potential contours in Box

and substrate. Figure 6‐10 through Figure 6‐15 plot the threshold voltage, off‐state current (Ioff)

and on–state current (Ion) as a function of template thickness for a range of channel length from

60nm to 10nm. Three device designs are compared‐one without ground‐plane, other with

ground‐plane under the gate and third one with continuous ground –plane or a uniformly doped

substrate of p‐type concentration 5E18cm‐3. The results are discussed in the following sections.

6.5.1 Potential in BOX and substrate In Figure 6‐8, we see that, for the low doped device i.e. device without ground plane, there occurs

a peak in the potential at the body/BOX interface. This rise in potential in the BOX and also in the

substrate is attributed to the drain‐induced conduction of back channel. Figure 6‐9a shows

potential contours in the BOX. The potential lines in the BOX are not parallel to the body/BOX

interface but highly deformed suggesting the coupling of drain to back channel. In other words,

the electric field vector points from drain to channel via the BOX. This also means that 2D drain

50

a) b)

Figure 6-7 a) Vt roll-off and b) DIBL for device with and without ground plane [7]

Figure 6-8 Simulated vertical potential along the center of silicon body for 25nm long device: low-doped (uniform substrate 1E15cm-3) and ground-plane device. The scale on y-axis is in volts and x-

axis in um

51

a)

b)

Figure 6-9 Simulated potential contours in 25nm long device with 5nm thick template. Drain is biased at 1V and back-gate at 0V a) Device without ground-plane (epi-SOI) b) Device with

ground plane (GP epi-SOI)

52

to body capacitance dominates. On the other hand, for the case of ground‐plane, the peak in

potential is lowered though not completely suppressed. The potential in the substrate is also

lowered. Moreover, in Figure 6‐9b, the potential contours in the BOX are flat and parallel to

body/BOX interface at least in the SiO2 layer. This suggests that the drain has lost some control

over the back channel reducing the DIBL. However, for complete suppression of DIBL, the BOX

thickness needs to be scaled.

6.5.2 Template Thickness Effect From Figure 6‐10 through Figure 6‐15, we see that, the ground‐plane improves device

performance. ‘Epi‐SOI’ refers to the device without ground plane. ‘GP epi‐SOI’ refers to device

with ground plane aligned with the gate and ‘GP con epi‐SOI’ refers to device with continuous

ground plane or uniform substrate of high doping ’. For all channel lengths, ground‐plane results

in a higher threshold voltage as compared to the device without ground‐plane. This is because of

the reduced short channel effects. Consequently, the off‐state current is lower for the ground

plane device. So is the on‐state current though the decrease in Ion is small compared to decrease

in Ioff. As for the device without ground‐plane, the threshold voltage for ground‐plane increases

as template thickness decreases. Therefore, Ioff and Ion both decrease with decreasing template

thickness. For 60nm to 25nm channel length devices, the reduction in Ioff caused by ground

plane is almost an order of magnitude. However for 15nm and 10nm long devices, the reduction

is not significant. This means that ground‐plane is more effective for long devices. And as

channel length shrinks, additional device alterations such as BOX thickness scaling need to be

adopted to further suppress the short channel effects. 6.5.3 Continuous Ground-plane Vs Ground-plane under gate Continuous ground plane refers to a uniform substrate of doping 5E18cm‐3. To employ a

continuous ground plane would mean to start with a highly conducting substrate and no mask

set would required for defining the ground‐plane under the gate. However, the ease of

fabrication comes at the cost of performance. As can be observed from Figures 6‐10 through

Figures 6‐15, continuous ground plane results in a larger Ioff values compared to the ground‐

plane under the gate. The reason is that very high substrate doping increases the parasitic

capacitances between the source/drain and substrate undermining the benefits of using SOI

53

0.5

0.53

0.56

0.59

0.62

5nm 4nm 3nm 2nm


Thre

shol

d Vo

ltage

(V)

epi-SOIGP epi-SOIGP Con epi-SOI

1.0E-12

1.0E-11

1.0E-10

1.0E-09



Ioff

(A/u

m)

epi-SOIGP epi-SOIGP con epi-SOI

0.72

0.77

0.82

0.87

0.92

0.97


Ion

(mA)


Figure 6-10 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for device with and without ground-plane

0.47

0.49

0.51

0.53

0.55

0.57

0.59

5nm 4nm 3nm 2nm


Thre

shol

d V

olta

ge (V

)


1.0E-10

1.0E-09

1.0E-08

1.0E-07



Ioff

(A/u

m)


0.9

0.94

0.98

1.02

1.06

1.1

1.14

1.18


Ion

(mA)



54

0.35

0.4

0.45

0.5


Thre

shol

d V

olta

ge (V

)


1.0E-07

1.0E-06

1.0E-05

1.0E-04



Ioff

(A/u

m)


1.2

1.3

1.4

1.5

1.6

1.7

1.8


Ion

(mA)



0.25

0.33

0.41

0.49


Thre

shol

d V

olta

ge (V

)


1.0E-06

1.0E-05

1.0E-04



Ioff

(A/u

m)


1.4

1.5

1.6

1.7

1.8

1.9

2


Ion

(mA)



55

1.0E-04

1.0E-03



Ioff

(A/u

m)


2.2

2.6

3

3.4


Ion

(mA)

epi-SOIGP epi-SOiGP con epi-SOI


1.0E-03



Ioff

(mA

/um

) epi-SOIGP epi-SOIGP con epi-SOI

4

4.5

5

5.5


Ion

(mA)



56

material. [7]. Also very high substrate doping increases body effect. The increased parasitic

capacitances lead to greater off‐sate current and reduced speed. For this reason, it is preferred to

have a ground‐plane structure in the BOX underneath the gate and keep the substrate as lowly

doped. A low doping concentration would keep parasitic capacitances to minimum.

6.5.4 Ground-plane Device and ITRS

Figure 6‐16 shows the Ioff values versus channel length for the device with and without ground‐

plane and how they compare with ITRS projections. The template thickness sis 5nm is all cases.

Figure 6‐17 does the same for Ion/Ioff ratios. It is to note that the ground‐plane greatly improves

Ioff and Ion/Ioff ratios down to 25nm channel length. For 15nm and 10nm length devices,

improvement with ground plane is small. The device with continuous ground‐plane performs

only slightly worse than device with ground‐plane under gate. While the ITRS projection for

45nm device was not met earlier, it is easily met with ground plane device.

6.6 Conclusion and Next

The ground‐plane in the substrate underneath the gate reduces fringing field lines in the

substrate from the drain. It causes drain to lose control over back channel thereby lowering the

potential in Box and substrate. The result is a reduction in short channel effects mainly DIBL

through BOX. Simulations show that employing ground plane can help meet ITRS requirement

with more ease. Thus, from this point on, device with ground‐plane will be considered. The goal

from now on would be to understand other measures for reducing short channel effects and

altering device design parameters accordingly to meet the ITRS specification at all gate length

levels.

57

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-0210nm 15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

Ioff

(A/u

m)

5nm epi-SOI5nm GP epi-SOI5nm GP con epi-SOIITRS HP

Figure 6-16 Comparison of device Ioff values with ITRS High Performance Logic projections for device with and without ground-plane and 5nm thick template

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

10nm 15nm 25nm 30nm 45nm 60nmChannel Length (nm)

Ion/

Ioff

5nm epi-SOI5nm GP epi-SOI5nm GP con epi-SOIITRS HP

Figure 6-17 Comparison of device Ion/Ioff ratios with ITRS High Performance Logic projections for device with and without ground-plane and 5nm thick template

58

6.7 References [1] T. Ernst and S. Cristoloveanu, “The ground‐plane concept for the reduction of short‐channel effects in fully depleted SOI devices”, Electrochemical Society Proceedings, pp. 329‐334, 1999. [2] Ernst T, Cristoloveanu S. Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture. IEEE Int SOI Conf 1999; 38–9. [3] J.P. Colinge, J.T. Park and C.A. Colinge, “SOI Devices for Sub‐0.1um gate lengths,” Proc. Int. Conf. Microelectronics, 12‐15 May, 2002, pp. 109‐113 [4] T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, “Fringing field in sub‐0.1 um fully depleted SOI MOSFETs: Optimization of the device architecture,” Solid State Electron., vol. 46, pp. 373‐378, 2002. [5] W. Xiong and J.P. Colinge, Self‐aligned implanted ground‐plane fully depleted SOI MOSFET, Electronics Letters, Vol. 35, No. 23, IEE, pp. 2059‐60, 1999 [6] Y. Omura, Silicon‐on‐insulator (SOI) MOSFET structure for sub‐50‐nm channel regime , in Silicon‐on‐Insulator technology and Devices X, Ed. by S. Cristoloveanu, P.L.F. Hemment, K. Izumi, G.K. Celler, F. Assaderaghi and Y.W. Kim, Electrochemical Society Proceedings, Vol. 2001‐3, pp.205‐210, 2001 [7] Xiong W, Ramkumar K, Jang SJ, Park J‐T, Colinge J‐P., “ Self‐aligned ground‐plane FDSOI MOSFET” In: Proc IEEE Int SOI Conf, 2002. p. 23.

60

Chapter 7 Suppressing Short Channel Effects 7.1 Introduction Lowering of the threshold voltage as channel length scales is referred to as short channel effects.

Threshold voltage is reduced by charge sharing and drain‐induced barrier lowering (DIBL) in the

silicon film. An extra component of DIBL results from the fringing fields from drain into the

buried oxide and underlying substrate. Charge sharing occurs when the charge on the gate is

balanced not only by the semiconductor charge under the gate but also by charge in the source

and drain depletion regions. Charge sharing is visible in short channel devices even at low drain

voltages. DIBL on the other hand is attributed to the electrostatic influence of drain on the source

to channel barrier height. A high positive bias on the drain causes field lines from drain to

electrostatically couple to the channel, lowering the barrier at source side. This results in greater

flow of electrons from source thereby reducing the threshold voltage. Short channel effects in

fully depleted SOI MOSFET therefore are influenced by silicon body thickness, silicon film

doping, buried oxide material and thickness, substrate doping and back‐gate bias. As devices

scale to sub‐100nm regime, several design options need to be considered to effectively control the

threshold voltage and ensure short channel effects to minimum. In order to scale with an

undoped silicon body, the gate workfunction engineering needs to be adopted. This chapter

discusses several aspects of the FDSOI device that control the threshold voltage.

7.2 Silicon Channel Doping Effect Doping the silicon channel reduces depletion width under the gate and increases threshold

voltage. It shields the channel from electric field lines from drain via the silicon body which

would otherwise lower the barrier for electrons to flow from source to channel. High silicon

channel doping is an effective way of suppressing short channel effects for both bulk and SOI

device. In fact, for bulk devices, it is the last alternative to continue scaling. However, very high

61

doping of concentration of the order of 1E19 cm‐3 is required. Even for short channel FDSOI

devices, high channel doping is advantageous. High channel doping also implies thin silicon

body to ensure full depletion. Figure 7‐1 shows shift in threshold voltage for a 100nm long SOI

device with 5nm thick gate oxide and 360nm thick buried oxide for different channel doping

densities. [1] When the silicon film is thick, device is partially depleted (PD) and below a critical

thickness, full‐depletion occurs. While in PD mode, high doping results in reduced DIBL, in FD

mode, DIBL is smaller with lighter film doping. The advantage of a thin film SOI device is that

the channel can be undoped. However, for very small FDSOI devices, channel doping becomes

necessary for threshold voltage control. Figure 7‐2 shows channel doping requirements for

FDSOI that are needed to achieve a threshold voltage of 0.25V and DIBL of about 100mV/V. [2]

The results are based on 2D device simulations using MEDICI. For Leff=28nm, extremely high

doping of ~1019cm‐3 with silicon film thickness, TSi<6nm is needed. The doping requirement

reaches 6.5E19cm‐3 for Leff=9nm with TSi=3nm. Recently Lu et al, [3] revised the scaling theory for

ultra‐thin body SOI MOSEFET. Figure 7‐3 from [3] shows threshold voltage roll‐off for different

channel doping. It indicates that minimum channel length set by DIBL of 100mV/V is 25%

improved with the channel doping concentration raised to 1.4E19 cm−3 from lowly doped

3.9E15cm‐3. Using Halo implants while keeping the channel undoped is another option for

suppressing short channel effects. Simulations in [4] show that strong halo implants results in less

DIBl than mild halo implants. Figure 7‐4 from [4] shows suppressed threshold voltage roll‐off for

stronger halo implants. Despite the advantages of high channel doping, utilizing this option is

not viable. Firstly, high channel doping results in reduced carrier mobility. The mobility

reduction at high field is attributed mainly to dopant induced scattering. [5] Reduction in

mobility results in reduced current drive. Secondly, high doping causes increased threshold

voltage fluctuation due to random dopant placement effects. [6] Band‐to‐band tunneling

associated with strong drain‐halo also causes a considerable off‐state leakage current. Apart from

above, doping the channel to such high impurity levels in ultra‐thin silicon films is also quite a

challenge.

7.3 Silicon Film Thickness Effect Both Figure 7‐1 and Figure 7‐2 indicate that reducing the silicon film thickness greatly reduces

short channel effects. This is the primary advantage of ultra thin body SOI. A thin silicon body

ensures no path in channel is far away from the gate which has full control over the channel. In

62

Figure 7-1 Vt shift Vs TSi for different channel doping [1]

Figure 7-2 MEDICI predicted TSi and channel doping requirements for FDSOI CMOS. Noted front oxide thickness values track SIA ITRS 2001 [2]

Figure 7-3 Threshold voltage roll-off for different channel doping [3]

63

other words, sub‐surface leakage paths are eliminated. A thin silicon body also allows for

undoped channel and thus avoids much of the above mentioned prolems associated with high

channel doping. Figure 7‐5 shows reduced DIBL and improved subthreshold slope for thinner TSi

devices. [2] As TSi scales from 10nm to 5nm, DIBL is reduced from 140mV/V to 40mV/V and

subthreshold swing from 83 to 66mV/decade for Lg=40nm. According scaling theory in [3], two‐

dimensional device simulation shows that for a thin gate insulator, the minimum channel length

can be expressed as,

( )( )min 4.5 /Si Si I IL T Tε ε≈ +

where TSi is the silicon thickness, and εI and TI are the permittivity and thickness of the gate

insulator. This reduces to Lmin≈TSi/4 for SiO2 as gate‐oxide and Lmin≈TSi/5 for high‐k gate

dielectric. 2D simulations in [2] also predict Lmin≈TSi/5 for conventional thick‐BOX FDSOI device.

There exists a limit for silicon film thickness scaling. When the silicon film is too thin, structural

as well as electric field induced confinement leads to carrier‐energy quantization. [7] The Vt shift

due to quantum mechanical (QM) confinement increases quadratically with silicon film thickness

for a given film thickness control. [8] The threshold voltage uncertainty makes it impossible to

design the device in this regime. In Figure 7‐6, dotted lines show the Vt shift due to QM

confinement of thin silicon channel. This sets a lower limit of TSi=4nm on silicon channel

thickness. Also, a high series resistance of thin silicon channel results in smaller drive current. [7]

In addition to these quantization effects, it has been observed that carrier mobility decreases with

decreasing TSi and is attributed to higher phonon scattering rates for spatially confined carriers

and also increases surface‐roughness scattering. [9] These effects limit silicon film thickness

scaling to about 4nm.

7.4 Back-gate Bias Effect In FDSOI transistor, because silicon body is thin, there exists electrical coupling between surface

potentials at the front and the back interfaces. [10] As a result of this interface coupling, the

threshold voltage is modulated by the back‐gate bias. [11] Several analytical models for threshold

voltage dependence on back‐gate bias have been proposed. [12][13][14]. Figure 7‐7 shows the

theoretical dependence of front gate threshold voltage on back‐gate bias for NMOS device. [12] If

64

Figure 7-4 Threshold voltage versus channel length for mild and strong halo implants [3]

Figure 7-5 DIBL and subthreshold swing Vs channel length for different TSi [2]

Figure 7-6 Dependence of Vt and QM shift in Vt on TSi. On right axis is sensitivity of Vt to TSi [8]

65

the back‐gate voltage is negative and less than VAGb the back surface is accumulated and back

surface potential is independent of back gate voltage as is the threshold voltage. For VGb between

VAGb and VIGb, the back surface is depleted and threshold voltage decreases linearly as back gate

voltage increases. For VGb> VIGb, the back surface is inverted and back surface potential is

virtually invariant so is the threshold voltage. Figure 7‐8 shows experimental results for

threshold voltage variation with back gate voltage for 0.25um and 80nm devices with 20nm thick

silicon film. [14] The linear decrease of Vt with back‐gate bias VG2 is modeled as,

( ) ( )21 1 2 2

1 2 2

dep acc accSi oxT T G G

ox ox Si it

C CV V V VC C C C

= − −+ +

Where Cox1,2 are front and back‐gate oxide capacitances, CSi=εSi/TSi is the depleted film

capacitance, Cit2=qDit2 is the back interface trap capacitance, VaccT1 is the front gate threshold

voltage for back channel accumulation, and VaccG2 is the bias below which the back channel will

always be in accumulation irrespective of VG1. The slope of linear region is named body factor ‘n’

and depends on BOX thickness. In Figure 7‐8 change in slope occurs at slightly positive back‐gate

bias when the back surface is driven from depletion to weak inversion. This leads to degradation

in subthreshold slope. [8] Figure 7‐9 shows that a more negative back‐gate bias results in reduced

DIBL. Thus, back‐gate bias is an effective way of tuning the threshold voltage and thereby

reducing short channel effects. 7.5 Gate Workfunction Effect A simplified expression for threshold voltage of a FDSOI device is [15],

2 SOI SOIth FB F

OX

qN tV VC

φ= + +

As devices scale, the silicon body thickness scales as well. With the use of high‐k gate dielectrics,

the gate‐oxide capacitance increases. It becomes difficult to control the threshold voltage by

changing the impurity concentration of the channel. In fact, in order to avoid the problems

66

Figure 7-7 Theoretical dependence of Vt on back-gate voltage [12]

Figure 7-8 Dependence of Vt on back-gate voltage [14]

Figure 7-9 DIBL Vs TSi for different back-gate voltages [8]

67

associated it with high channel doping it is preferable to keep the channel undoped. In such a

case, gate‐workfunction engineering gives an option for controlling the threshold voltage.

[16][17] Figure 7‐10 shows the variation of off‐state leakage current for 50nm FDSOI MOSFET for

different gate‐workfunction values. [17] The body is lightly doped 1E15cm‐3. The dotted and

solid lines mark the targets of ITRS for High performance (HP) and Low Operating Power (LOP)

applications. AS gate‐workfunction increases, both Ion and Ioff decrease due to increase in

threshold voltage. For gate materials with higher workfunctions, Ioff decreases more rapidly with

body thickness while Ion decreases slowly. The ratio Ion/Ioff is plotted in Figure 7‐11. It is

observed that for same body thickness, higher workfunction yields greater Ion/Ioff ratio. Thus, a

larger workfunction is more suited to meet ITRS requirements. Figure 7‐12 shows that increasing

workfunction suppressing short channel effects. Here, ΔVt is measures as different in threshold

voltage at drain bias of 0.05V and 1.2V. The Vt of devices with larger workfunctions is higher

which results in smaller DIBL or, ΔVt/Vt.

7.6 Simulation Setup and Results Two dimensional simulations were performed on the epitaxial oxide based device employing the

ground plane implant in the substrate under the gate to study the effects of above discussed

parameters for controlling threshold voltage and suppressing short channel effects. 7.6.1 Varying the silicon film thickness Two device structures are simulated. The ‘soi’ device is the epitaxial oxide based device without

ground‐plane and uniformly doped substrate of concentration 1E15cm‐3. The other is the ground‐

plane device with a back‐gate bias of Vbg=‐0.2V. The template is 5nm thick and the silicon film

thickness is varied. The metal workfunction is 4.7eV. DIBL is measured as the difference in

threshold voltage at drain bias of 0.1V and 1V. Figure 7‐13 plots DIBL versus channel length for

three different silicon film thicknesses. Evidently, thinner silicon film results in lesser DIBL. Also,

DIBL for device with ground‐plane is lesser than that without ground‐plane. Thus, both reducing

the silicon film thickness and employing ground‐plane are effective in suppressing short channel

effects. Figure 7‐14 and Figure 7‐15 plot threshold voltage roll‐off trend. Delta‐Vt is measured as

deviation of threshold voltage from its value for a 1um long device. Roll‐off is worse for thicker

silicon film and improves with ground‐plane. Figure 7‐16 plots subthreshold swing versus

68

Figure 7-10 TSi dependence of the off-state current of 50nm UTB device for different ΦM values [17]

Figure 7-11 Ratio of Ion/Ioff pf 50nm UTB device for different TSi and ΦM values [17]

Figure 7-12 Ratio of ΔVt/Vt versus TSi with different ΦM values [17]

69

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

10 100

Channel Length (nm)

DIB

L (D

elta

Vt)

(v)

tsi = 5nm GPtsi = 10nm GPtsi = 15nm GPtsi=5nm soitsi=10nm soitsi=15nm soi

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

10 100 1000

Channel Length (nm)

Del

ta V

t (V)

tsi = 5nm gptsi = 10nm gptsi = 5nm soitsi = 10nm soi

Figure 7-13 DIBL Vs Lg for different TSi for device Figure 7-14 Vt roll-off for TSi =5nm and 10nm for with ground-plane (GP, Vbg=-0.2V) and without device with ground-plane (GP, Vbg=-0.2V) and (soi). Template thickness is 5nm without (soi). Template thickness is 5nm

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

10 100 1000

Channel Length (nm)

Del

ta V

t (V)

tsi = 5nm gptsi = 15nm gptsi = 5nm soitsi = 15nm soi

0

200

400

600

800

1000

1200

1400

1600

1800

10 100

Channel Length (nm)

Subt

hres

hold

Sw

ing

(mV/

dec)

tsi = 5nm gptsi = 10nm gptsi = 15nm gptsi = 5nm soitsi = 10nm soitsi = 15nm soi

Figure 7-15 Vt roll-off for TSi =5nm and 10nm for device Figure 7-16 Subthreshold Swing Vs Lg for different with ground-plane (GP, Vbg=-0.2V) and without (soi). TSi for device with and without ground-plane. Template thickness is 5nm Template thickness is 5nm

70

channel length. A thinner Si film results in a better subthreshold slope. The value is about

70mV/decade for ground‐plane device for TSi=5nm and begins to degrade substantially as

channel length scales below 20nm. Ground‐plane device though provides a better subthreshold

characteristic than the device without it. Figure 7‐17 plots off‐state leakage current for different

silicon film thicknesses. As channel length scales, Ioff increases. A thinner silicon body thickness

results in a smaller leakage current. Consequently, Ion/Ioff ratio is larger for thinner Si film as

shown in Figure 7‐18.

7.6.2 Varying the back-gate bias Figure 7‐19 plots threshold voltage roll‐off for TSi=7nm and Vbg=‐0.2V, ‐0.6V and ‐1V. Metal

workfunction is 4.7eV. A negative bias on the back‐gate drives the channel towards accumulation

and cause the threshold voltage to increase. The back‐gate bias is limited by the magnitude of the

power supply voltage on the negative end and on the positive end by a value that drives the back

channel into inversion and leads to degradation in subthreshold slope. Figure 7‐20 plots DIBL

versus channel length. Since, Vbg=‐1V results in a larger threshold voltage, it results in the

smallest value of DIBL for any gate length. A more negative bias on the back‐gate also improves

subthreshold swing as shown in Figure 7‐21. The swing degrades however for sub‐20nm devices.

Figure 7‐22 and Figure 7‐23 plot variation of Ioff and Ion/Ioff ratio with channel length. A larger

negative bias results in a smaller Ioff and larger Ion/Ioff value. For 15nm and 10nm gate length

devices, Ioff and Ion/Ioff values don’t change much with change in back‐gate bias. 7.6.3 Relationship between silicon film thickness and back-gate bias Figure 7‐24 plots threshold voltage versus back‐gate bias for TSi=5nm and 10nm. Vt decreases

linearly as back‐gate bias increases. At around Vbg=0.2V, there occurs a change in slope when the

back channel is driven into weak inversion. Beyond this point, the subthreshold swing also

degrades substantially as shown in Figure 7‐25. Thus, the value of back‐gate bias must lie in the

range that ensures that the back channel is under depletion. Figure 7‐26 plots DIBL versus back‐

gate voltage. As discussed before, a thinner silicon film and a more negative back‐gate bias result

in lesser DIBL. Thus, back‐gate bias is an essential feature for controlling the threshold voltage

and suppressing short channel effects in sub‐100nm FDSOI devices.

71

Ioff Vs Channel length

1.0E-17

1.0E-15

1.0E-13

1.0E-11

1.0E-09

1.0E-07

1.0E-05

1.0E-03

1.0E-0110 100

Channel Length (nm)

Ioff

(A/u

m)

tsi = 5nmtsi = 10nmtsi = 15nm

Ion / Ioff Ratio

1.0E+02

1.0E+04

1.0E+06

1.0E+08

1.0E+10

1.0E+12

1.0E+14

1.0E+16

10 100Channel Length (nm)

Ion

/ Iof

f (A

/A)


Figure 7-17 Ioff Vs Lg for different TSi for device with Figure 7-18 Ratio Ion/Ioff Vs Lg for different TSi for ground-plane, Vbg=-0.2V and 5nm thick template device with ground-plane, Vbg=-0.2V and 5nm thick template

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

10 100 1000

Channel Length (nm)

Thre

shol

d Vo

ltage

(V)

vbg = -1Vvbg = -0.6Vvbg = -0.2V

-0.80

-0.70

-0.60

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

0 20 40 60 80 100

Channel Length (nm)

Del

ta V

t (V)

vbg = -1Vvbg = -0.6Vvbg = -0.2V

Figure 7-19 Vt Vs Lg for ground-plane device with TSi Figure 7-20 DIBL Vs Lg for ground-plane device =7nm and different back-gate voltages. Template is with TSi 7nm and different back-gate voltages. 5nm thick Template is 5nm thick

72

60

260

460

660

860


Subt

hres

hold

Sw

ing

(mV/

deca

de)

vbg = -1Vvbg = -0.6Vvbg = -0.2v

1.0E-15

1.0E-13

1.0E-11

1.0E-09

1.0E-07

1.0E-05

1.0E-03

10 100

Channel Length (nm)

Ioff

(A/u

m)

vbg = -1Vvbg = -0.6Vvbg = -0.2V

Figure 7-21 Subthreshold Swing Vs Lg for ground Figure 7-22 Ioff Vs Lg for ground-plane device with Plane device with TSi=7nm and different back-gate TSi=7nm and different back-gate voltages. Template is voltages. Template is 5nm thick. 5nm thick.

1.0E+02

1.0E+04

1.0E+06

1.0E+08

1.0E+10

1.0E+12

1.0E+14

1.0E+16

10 100

Channel Length (nm)

Ion

/ Iof

f (A

/A)

vbg = -1Vvbg = -0.6Vvbg = -0.2V

Figure 7-23 Ratio Ion/Ioff Vs Lg for ground-plane device with TSi=7nm and different back-gate voltages. Template is 5nm thick

73

0.4

0.45

0.5

0.55

0.6

0.65

0.7

-1 -0.6 -0.2 0.2Back-gate Voltage (V)

Thre

shol

d vo

ltage

(V)

tsi = 5nmtsi = 10nm

100110120130140150160170180190200

-1 -0.6 -0.2 0.2

Back-gate Voltage (V)

S-fa

ctor

(mv/

deca

de)

tsi = 5nmtsi = 10nm

Figure 7-24 Threshold Voltage Vs Back-gate voltage for Figure 7-25 Subthrehsold Swing Vs Back-gate ground-plane device with TSi=5nm and 10nm and 5nm voltage for ground-plane device with TSi=5nm and template thickness 10nm and 5nm template thickness

-0.45

-0.4

-0.35

-0.3

-0.25

-0.2

-0.15

-1 -0.6 -0.2 0.2 0.6

Back-gate Voltage, Vbg (V)

Del

ta V

t (V)


Figure 7-26 DIBL Vs Back-gate voltage for ground-plane device with TSi=5nm and 10nm and 5nm template thickness

74

7.7 Conclusion Two dimensional device simulations show that ground‐plane is effective in reducing short

channel effects. Sub‐100nm FDSOI devices will employ ground‐plane along with a thin silicon

film. Silicon film thickness needs to be below 10nm for substantive reduction of SCEs. Moreover,

in order to scale with undoped body, both workfunction engineering and back‐gate control need

to be exercised. A larger workfunction and a negative back‐gate bias result in a larger threshold

voltage and lesser SCEs. The role of silicon body thickness, body doping, gate‐workfunction and

back‐gate bias in controlling the SCEs was discussed comprehensively. However, there remains

another important device feature that can be used to suppress SCEs. This is the buried oxide

material and thickness. This forms the discussion of next chapter. 7.8 References [1] L. T. Su, J. B. Jacobs, J. Chung, and D. A. Antoniadis, “Deepsubmicrometer channel design in silicon‐on‐insulator (SOI) MOSFET’s,” IEEE Electron Device Lett., vol. 15, no. 5, pp. 183–185, May 1994. [2] V. P. Trivedi and J. G. Fossum, “Scaling fully depleted SOI CMOS,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2095–2103, Oct. 2003. [3] Wei‐Yuan Lu and Yuan Taur, “On the scaling limit of ultra thin SOI MOSFETs,” ,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1137–1141, May 2006 [4] B. Doris, et al., “Extreme scaling with ultra thin Si channel MOSFETs,” in IEDM Tech. Dig., Dec 2002, pp. 267‐270. [5] L. Ge, J. G. Fossum, and B. Liu, “Physical compact modeling and analyses of velocity overshoot in extremely scaled CMOS devices and circuits,” IEEE Trans. Electron Devices, vol. 48, pp. 2074–2080, Sept. 2001. [6] D. J. Frank et al., “Monte Carlo modeling of threshold variation due to dopant fluctuation,” in Symp. VLSI Tech. Dig., June 1999, pp. 169–170. [7] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte carlo simulation of a 30 nm dual‐gate MOSFET: How short can Si go?,” in IEDM Tech. Dig., 1992, pp. 553–556. [8] H.‐S. Wong, D. Frank, and P. Solomon, “Device design considerations for double‐gate, ground‐plane, and single‐gated ultra thin SOI MOSFET’s at the 25 nm channel length generation,” in Proc. Int. Electron Devices Meeting, 1998, p. 407. [9] F. Gámiz et al., “Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 45, pp. 1122–1126, May 1998. [10] I. Yang, C. Vieri, A. Chandrakasan, and D. Antoniadis, “Backgated CMOS on SOIAS for dynamic threshold voltage control,” IEEE Trans. Electron Devices, vol. 44, p. 822, 1997. [11] S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, M. Chan, “Threshold voltage model for deep‐submicrometer fully depleted SOI MOSFETʹs,” IEEE Trans. Electron Devices, vol. 42, pp. 1949‐55, November 1995 [12] H.‐K. Lim and J. G. Fossum, “Threshold voltage of thin‐film silicon‐on‐insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED‐30, pp. 1244–1251, Oct. 1983.

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[13] M. Noguchi, T. Numata, Y. Mitani, T. Shino, S. Kawanaka, Y. Oowaki, and A. Toriumi, “Back gate effects on threshold voltage sensitivity to SOI thickness in fully depleted SOI MOSFETs,” IEEE Electron Device Lett., vol. 22, pp. 32–34, Feb. 2001. [14] J. Pretet, S. Monfray, S. Cristoloveanu, and T. Skotnicki, “Silicon‐on‐nothing MOSFETs: performance, short‐channel effects, and backgate coupling,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 240–245, Feb. 2004. [15] H. Shimada, Y. Hirano, T. Ushiki, K. Ino, and T. Ohmi, “Tantalum‐gate thin‐film SOI nMOS and pMOS for low‐power applications,” IEEE Trans. Electron Devices, vol. 44, pp. 1903–1907, 1997. [16] T. Numata, K. Uchida, J. Koga, and S. Takagi, “Device design for subthreshold slope and threshold voltage control in sub‐100 nm fully‐depleted SOI MOSFETs,” in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 179‐180. [17] An X, Huang R, Zhao B, Zhang X and Wang Y 2004 Design guideline of an ultra‐thin body SOI MOSFET for low‐power and high‐performance applications Semicond. Sci. Technol. 19 347‐50

76

Chapter 8

Buried Insulator Engineering 8.1 Introduction In order to scale fully‐depleted SOI MOSFET below 100nm gate length, the buried oxide (BOX)

thickness must be scaled as well. Thinning the BOX cuts fringing field lines in the BOX from

drain and improves drain‐induced barrier lowering (DIBL). It allows for additional control of

threshold voltage thereby allowing silicon film to be thicker. BOX permittivity also has an effect

on short channel effect. As a rule, scaling the BOX permittivity reduces DIBL. Engineering the

buried oxide material and thickness to suppress short channel effects is referred to as buried

insulator engineering.

8.2 BOX Thickness Scaling The use of a highly conducting substrate underneath a thin buried oxide (known as ground‐plane

structure [1]) has been proved effective to reduce short channel effects in sub‐100nm fully

depleted SOI devices. To scale the SOI device to shorter channel lengths (Lg <50nm), with an

undoped Si body, requires a thinner BOX along with back‐gate voltage control to set the

threshold voltage to a level so that short channel effects are suppressed [2]. A thinner BOX is

needed more so as to ensure that sufficient reduction of short channel effects is achieved without

requiring to increase the magnitude of back‐gate voltage beyond the supply voltage. This is

because a thinner BOX increases the back‐gate coupling effect by increasing the body‐substrate

capacitance. Analysis in [3] show that Tbox < Lg/2 is required for substantive reduction of SCEs.

This means for sub‐50nm devices, BOX may be at most 25nm thick. 2D device simulations in [2],

[4] and [5] further support this theory.

Figure 8‐1a shows the potential contours in 30nm long device with ground‐plane and 200nm

BOX thickness. The BOX permittivity is 3.9. The ground‐plane device has a p+ implant of

77

concentration 5E18cm‐3 in the substrate under the gate. The substrate is doped 1E18cm‐3 and the

back‐gate voltage is ‐0.2V. Also simulated is the device without ground plane. It has a uniformly

doped substrate of concentration 1E15cm‐3 and connected to ground. This is referred to as the

low‐doped (LD) device. For both devices, silicon film is 7nm thick and metal workfunction is

4.7eV.

When the BOX is thick, the lateral penetration of electric field lines from drain to channel via the

BOX and the substrate is the major cause of DIBL. This component of DIBL is referred to as DIBL

through BOX. [6] The equipotential contours in BOX are not parallel to body/BOX interface but

highly deformed as shown in Figure 8‐1a for Tbox=200nm. At this thickness, the drain/source to

body capacitances dominates over the body‐substrate capacitance. The electric field vectors are

from source to body and drain to body. The result is that the back channel is driven under

conduction from depletion to weak inversion causing a peak in potential in BOX as shown in

Figure 8‐1b. This effect which causes additional short channel effects is referred to as drain‐

induced virtual substrate biasing (DIVSB) [6]. The potential at drain is coupled to the back

interface potential as if the substrate is positively biased. Ernst et al [3] developed analytical

expressions for source/drain to body capacitances and derived the criterion for suppressing the

DIVSB effect. The 1D body‐substrate capacitance must dominate over the 2D source/drain to

body capacitance. According to [3], ground‐plane structure along with very thin BOX should be

employed.

Figure 8‐2a shows potential contours in the ground‐plane device with 10nm thick BOX and

permittivity value 3.9, which are horizontal and parallel to BOX/body interface much like those in

the body of a long‐channel device. This means that at Tbox=10nm, the back channel is no longer

under the control of drain. The channel is no longer coupled to drain through the BOX and DIBL

through BOX is completely suppressed. Potential contours show that 1D body‐substrate

capacitance dominates over source/drain‐body capacitances and the electric field vector is now

perpendicular to the body/BOX interface. Figure 8‐1b shows the vertical electrostatic potential

through the center of silicon body for Tbox=10nm. As can be observed, the peak in potential at

body/BOX interface is completely suppressed. It is to note that, while employing ground‐plane

structure reduces the peak, (comparison with LD and GP device in Figure 8‐1b) combining it with

a thin BOX completely eliminates it. Thus, scaling the BOX thickness reduces short channel

78

a) b) Figure 8‐1 a) Simulated equipotential contours in ground‐plane device with source at ground, drain at 1V and back‐gate voltage Vbg=‐0.2V. BOX thickness is 200nm and permittivity is 3.9. The scale on x and y‐axis is in um b) Electrostatic Potential along a vertical cut though center of silicon body. The scale on x and y‐axis is in um and volts respectively

a) b) Figure 8‐2 a) Simulated equipotential contours in ground‐plane device with source at ground, drain at 1V and back‐gate voltage Vbg=‐0.2V. BOX thickness is 10nm and permittivity is a) k= 3.9 and b) k= 20. The scale on x and y‐axis is in um

79

effects. It leads to an increase in the threshold voltage and gives an alternative control over

threshold voltage in addition to back‐gate voltage and gate‐workfunction engineering.

8.3 BOX Permittivity Scaling Permittivity is a constant characteristic of the BOX material. It has been shown that reducing the

permittivity decreases short channel effects. [7][8] In particular, Oshima et al have shown in [9]

that DIVSB can be alleviated using a low‐k BOX material. For 60nm device with 20nm thick BOX,

10nm thick Si film and 1E15cm‐3 substrate doping, it has been shown [9] that, buried Alumina

with k=12.0 results in 7% higher peak in potential at body/BOX interface compared to buried SiO2

with k=3.9. Also, for the ground‐plane device, with Tbox=50nm, buried alumina results in 20mV

higher DIBL than buried SiO2 for 25nm gate length device. Thus it is commonly understood that

low‐k BOX results in lesser DIBL. The fact has formed the guiding principle for silicon‐on‐

nothing MOSEFT where an air‐gap acts as the dielectric between the silicon body and the

substrate. [10][11]

For sub‐50nm FDSOI device, BOX thickness needs to be thinner than 25nm. One would expect a

low‐k/thin BOX combination to yield least short channel effects and best device performance.

However, this is not the case as we show in this chapter. There is a limit to the BOX thickness,

until which, reducing the permittivity of the BOX lowers DIBL. However, below this limit which

occurs around 25nm for the ground‐plane device, the role of the BOX permittivity is reversed in

the sense that a lower‐k BOX yields larger DIBL compared to a higher‐k BOX. The fact was

briefly mentioned in [7] but has not been discussed comprehensively so far. Also quantum effects

were not considered in simulations in [7]. In this chapter, this theory is presented in detail and

support ed with 2D device simulations.

8.4 Permittivity role at thick and thin BOX DIBL in short channel devices is associated with electrostatic coupling of drain to channel. The

coupling of drain to channel via the silicon body is referred to as DIBL through silicon body

whereas coupling of drain to channel via the BOX and substrate is referred to as DIBL through

BOX. When the BOX is thick, the field lines from drain via the BOX and substrate turn the back

channel on as discussed above and therefore DIBL through BOX dominates.

80

Figure 8‐3 plots DIBL versus BOX thickness for low‐doped device and ground‐plane device with

Vbg=‐0.2V and Vbg=‐1V. Permittivity values of k=3.9 and k=20.0 are considered. For a range of BOX

thickness, from 200nmn down to a critical value, lower permittivity results in lower DIBL. At

TBox=100nm, DIBL at k=20 is 139% higher for ground‐plane device with Vbg=‐0.2V, 102% higher for

ground‐plane device with Vbg=‐1V and 168% higher for low‐doped device as compared to DIBL

at k=3.9. Thus, at thick BOX, low‐k BOX results in lesser DIBL. This is because, at thick BOX,

potential contours in the BOX are not parallel to body/BOX interface. The electric field vectors

begin from drain and curl up to channel via the BOX. (Figure 8‐1a) Reducing the BOX

permittivity reduces this 2D coupling of drain to channel via the BOX thereby reducing DIBL

through BOX. [9]

However, there exists a critical thickness below which the permittivity role is reversed and now a

low‐k BOX results in larger DIBL. Figure 8‐4 reproduces the plot in Figure 8‐3 for BOX

thicknesses below 60nm. The crossover point occurs at Tbox = 35nm for Vbg=‐1V and 25nm for Vbg=‐

0.2V in case of the ground plane device and at Tbox = 10nm for the low‐doped device. This

suggests that the ‘fringing field reducing’ effect of the BOX permittivity is no longer dominant

below the critical thickness and becomes secondary to another role played by permittivity which

needs to be explained. Figure 8‐4 suggests that below 25nm BOX thickness (as required for sub‐

50nm devices), a higher permittivity BOX is better suited to meet the scaling capability

requirements set by ITRS in terms of suppression of DIBL and therefore, also in achieving the

targeted off‐state leakage current value.

At BOX thickness, Tbox=10nm, DIBL for k=20 is lower than that for k=3.9 by 18mV (or 38%) for

ground plane device with Vbg=‐0.2V and by 17mV (or 45%) for ground‐plane device with Vbg=‐1V.

Even though the reduction in DIBL by high‐k BOX is small, it proves the point that a high‐k BOX

doesn’t hurt device performance at thin BOX thickness as needed by sub‐50nm devices.

Moreover, high‐k BOX only slightly improves the short channel effects.

Figure 8‐5 plots DIBL versus BOX thicknesses below Tbox=60nm for k=3.9 and k=5.0. The crossover

point occurs at Tbox = 25nm for Vbg=‐1V and 20nm for Vbg=‐0.2V in case of the ground plane device

and at Tbox = 8nm for the low‐doped device. Figure 8‐6 plots the threshold voltage versus BOX

81

0.00

0.06

0.12

0.18

0.24

0.30

0.36

0.42

0.48

0 40 80 120 160 200Box Thickness (nm)

Del

ta V

t (V)

k = 3.9 vbg=-0.2Vk = 20 vbg=-0.2Vk=3.9 vbg=-1Vk=20 vbg=-1Vk = 3.9 LDk = 20 LD

0.00

0.06

0.12

0.18

0.24

0 10 20 30 40 50 60

Box Thickness (nm)

Del

ta V

t (V)

k=3.9 vbg=-0.2Vk=20.0 vbg=-0.2Vk=3.9 vbg=-1Vk=20 vbg=-1Vk=3.9 LDk=20 LD

Vbg = -0.2V

Vbg = -1VVbg = 0V

Figure 8‐3 DIBL versus BOX thickness for ground‐plane device with Vbg=‐0.2V and Vbg=‐1V and low‐doped (LD) device. Lower‐k BOX gives lower DIBL for thick BOX Figure 8‐4 DIBL versus BOX thickness for ground‐plane device with Vbg=‐0.2V and Vbg=‐1V and low‐doped (LD) device with Vbg=0V. Higher‐k BOX gives lower DIBL below a critical BOX thickness

82

Figure 8‐5 DIBL versus BOX thickness for k=3.9 and k=5.0. Lg=30nm,TSi=7nm, Wf=4.7eV

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 20 40 60 80 100 120 140 160 180 200Box Thickness (nm)

Thre

shol

d Vo

ltage

(V) k=3.9,vbg=-0.2

k=5.0, vbg=-0.2k = 3.9, vbg=-1Vk = 5.0, vbg =-1Vk=3.9, LDk=5.0, LD

Figure 8‐6 Threshold Voltage versus TBox for k=3.9 and k=5.0. Lg=30nm,TSi=7nm, Wf=4.7eV

0.02

0.05

0.08

0.11

0.14

0.17

0 10 20 30 40 50 60

Box Thickness (nm)

Del

ta V

t (V)

k = 3.9 vbg=-0.2Vk = 5.0, vbg = -0.2Vk = 3.9, Vbg = -1Vk = 5.0, vbg=-1Vk=3.9, LDk=5.0, LD

83

thickness for k=3.9 and k=5.0. Since, threshold voltage is affected by DIBL; it reflects the crossover

as observed in DIBL plot. The definition of threshold voltage used in this paper is as in [12] and is

the gate bias that results in a drain current, IDS = (W/Lmet) x 10‐7 A. Here, W is the gate‐width set at

1μ m and Lmet is the metallurgical channel length corresponding to 30nm physical channel length.

The slight difference in crossover thickness between DIBL and threshold voltage plots is

attributed to the constant current model used for measuring threshold voltage.

So what is the role of BOX permittivity below critical BOX thickness? As shown in Figure 8‐2a

and discussed above, at TBox=10nm, the potential contours in the BOX are flat and parallel to the

body/BOX interface. The 1D body‐substrate capacitance dominates over the 2D source/drain‐

body capacitances opposite to what happens at thick BOX. Therefore, we can conclude that at the

critical BOX thickness, DIBL through BOX is suppressed and below it, the only persistent

component of DIBL is DIBL through silicon body. At this thickness, a high‐k BOX increases body‐

substrate capacitance and results in increased coupling between the drain and substrate. This

causes lateral field lines emanating from drain towards channel via the silicon body to be pulled

towards substrate reducing the DIBL through silicon body. In Figure 8‐2a, for k=3.9, the potential

lines from drain to channel exist beyond the drain boundary in the silicon body whereas in

Figure 8‐2b, for the case of k=20, they are pushed inside the boundary indicating termination of

field lines on the substrate. Also, k=20 results in more horizontal and flat potential contours in the

silicon body compared to k=3.9 implying reduced DIBL through silicon body. To support this,

Figure 8‐7 plots the channel potential along the body/BOX interface for k=3.9 and k=20 cases for

Tbox= 10nm and Tbox=200nm. AT TBox=200nm, the potential barrier between the source and channel

is larger for k=3.9 than k=20 implying lesser DIBL for k=3.9 case. However, at TBox=10nm, the

barrier is significantly higher for k=20 as compared to that for k=3.9 implying lesser DIBL for k=20

case. This explains why a high‐k BOX, k=20 yields lower DIBL below critical BOX thickness.

To conclude, a low‐k BOX yields lower DIBL for thick BOX by reducing DIBL through the BOX.

A high‐k BOX yields lower DIBL for thin BOX by reducing DIBL though the silicon body. Since,

Vbg=‐1V is more effective in suppressing DIBL through the BOX compared to Vbg=‐0.2V, the

crossover point is reached at a larger BOX thickness for the former. This is because DIBL through

the BOX is eliminated at a thicker BOX (Tbox=35nm in Figure 8‐4) for the former and a thinner

BOX (Tbox=25nm in Figure 8‐4) for the latter. For the low doped device, depletion in substrate

84

Figure 8‐7 Electrostatic potential along body/BOX interface at TBox =200nm and 10nm for k=3.9 and k=5.0. Lg=30nm,TSi=7nm, Wf=4.7eV. Scale on x‐axis is in um and y‐axis in volts

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

-1.5 -1 -0.5 0 0.5 1 1.5

Back-gate Voltage Vbg (V)

Thre

shol

d Vo

ltage

(V)

k=3.9k=5.0

Tbox=25nm

Tbox=100nm

Tbox=10nm

Figure 8‐8 Threshold voltage versus back‐gate bias for TBox =200nm, 25nm and 10nm for k=3.9 and k=5.0. Lg=30nm, TSi=7nm, Wf=4.7eV

85

adds to BOX thickness and since there is no ground‐plane, it takes a much thinner buried oxide,

(Tbox=10nm in Figure 8‐4) to completely eliminate DIBL through the BOX.

According to [5], SCEs in thin‐box SOI device are reduced due to increased transverse electric

field in the silicon body and not only reduction of fringing fields in the BOX. For significant

reduction, Tbox<25nm for ground‐plane device and Tbox<10nm for low‐doped device are required.

The limits agree well with critical BOX thickness we conclude above for suppression of DIBL

through BOX. In fact in Figure 8‐2b, it is observed that the field lines are more closely spaced in

the silicon body for k=20 as compared to k=3.9. This suggests that, there is an increase in vertical

electric field in the silicon body which gives more control to front‐gate over channel and

improves DIBL. This supports the theory in [5].

An important device design consideration for the ground‐plane device is the choice of the back‐

gate voltage. Figure 8‐8 plots threshold voltage variation with back‐gate bias for Tbox=10nm,

25nm and 100nm for permittivity values of 3.9 and 5.0. The back channel should be biased in

depletion and for this range of back‐gate voltage, for 10nm and 25nm BOX thicknesses, high‐k

results in larger threshold voltage suggesting smaller DIBL and capability for yielding smaller Ioff

values. For thick BOX, Tbox=100nm, a low‐k results in larger threshold voltage for the range of

back‐gate bias suggesting lower DIBL. The above discussion explains the permittivity role

reversal effect with regards to back‐gate bias. It is noted that at BOX thickness below critical

thickness, high‐k BOX yields lesser DIBL irrespective of the back‐gate bias.

The subthreshold swing variation with BOX thickness at drain bias, Vd =1V is shown in Figure 8‐

9. The swing improves as BOX thickness is scaled [1] and for short channel devices is governed

more by DIBL than the BOX capacitance effect. The crossover in DIBL characteristics in Figure 8‐4

are reflected in subthreshold characteristics as well. A high‐k BOX leads to better swing below

the critical thickness though the improvement is only a few mV/decade.

Figure 8‐10 plots Id‐Vg curves for ground‐plane device with Vbg=‐0.2V for permittivity values of

k=3.9, 5.0 and 20.0 for Tbox=200nm and 10nm. While high‐k results in greater off‐state leakage

current at Tbox=200nm, it results in smaller leakage at TBox=10nm.

86

75

85

95

105

115

125

135

145

155

165

0 10 20 30 40 50 60

BOX Thickness (nm)

Subt

hres

hold

Sw

ing

(mV/

deca

de) k = 3.9 Vbg= -0.2V

k = 20 Vbg= -0.2Vk = 3.9 Vbg= -1Vk = 20 Vbg= -1V

Figure 8‐9 Subthreshold swing Vs BOX thickness for ground plane‐device

Figure 8‐10 Id‐Vg curves for ground‐plane device for Tbox=10nm and 100nm at BOX permittivity of k=3.9, 5.0 and 20.0. Drain is at 1V, source at 0V and Vbg=‐0.2V

87

8.5 Device Simulation of epi-SOI device

The above sections discussed the role of BOX permittivity at thick and thin BOX and its impact

on short channel effects. The simulations were applicable to a standard device with buried

insulator being a single material. However, for the epitaxial‐oxide based device under

investigation, the buried insulator consists of high‐k template material on top of SiO2. If the total

insulator thickness is kept constant, and the thickness of template material is varied, then the

impact on device performance is indirectly due to the BOX permittivity variation. The ground‐

plane device is simulated with 5E18cm‐3 doped ground‐plane and 1E15cm‐3 doped substrate. The

template thickness is varied between 2nm and 5nm keeping the total insulator thickness constant

equal to 15nm. The back‐gate voltage is Vbg=‐1V, TSi=7nm and metal workfunction is 4.7eV.

8.5.1 Varying Template Thickness

The permittivity of the insulator is determined by the parallel combination of the capacitive

divider formed by template material and SiO2 underneath. For 15nm total thickness, the

permittivity of insulator is 5.4(5nm), 5.0(4nm), 4.7(3nm) and 4.4(2nm). Thus varying template

thickness varies BOX permittivity. It is to be noted that though 15nm BOX thickness is below the

critical thickness we have concluded above and one would expect a thinner template material to

yield a larger DIBL by virtue of lower permittivity, it doesn’t happen so. This is because; the

substrate doping for epitaxial buried‐oxide based device is lowly doped 1E15cm‐3 as against

1E18cm‐3 used in simulations before. A lower substrate doping implies a smaller critical BOX

thickness to suppress the short channel effects associated with BOX.

Figure 8‐11 plots DIBL versus channel length for 5nm and 2nm template thicknesses. A thinner

template results in smaller DIBL by virtue of lower BOX permittivity. It is observed that,

employing ground‐plane under the gate further improves DIBL.

Figure 8‐12 and Figure 8‐13 plot threshold voltage roll‐off trends. Delta‐Vt is measured as

deviation of threshold voltage from its value for a 1um long device. Roll‐off is worse for thicker

template and improves with ground‐plane. For ground‐plane device, delta Vt improves from

0.33V to 0.24V as template thickness changes from 5nm to 2nm.

88

-0.50

-0.45

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.0010 100

Channel Length (nm)

Del

ta V

t (V)

template 5nm GPtemplate 2nm GPtemplate 5nm soitemplate 2nm soi

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

010 100

Channel Length (nm)

Thre

shol

d Vo

ltage

(V)

5nm GP4nm GP3nm GP2nm GP5nm soi4nm soi3nm soi2nm soi

Figure 8-11 DIBL Vs Lg for two template thicknesses Figure 8-12 Threshold voltage roll-off Vs Lg for for device with ground-plane (GP, Vbg=-1V) and different template thicknesses for device with without (soi) ground-plane (GP, Vbg=-0.2V) and without (soi)

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

010 100

Channel Length (nm)

Del

ta V

t (V)

template 5nm GPtemplate 2nm GPtemplate 5nm soitemplate 2nm soi

60.00

80.00

100.00

120.00

140.00

160.00

180.00


S-Fa

ctor

(mV/

deca

de)

5nm GP4nm GP3nm GP2nm GP5nm soi4nm soi3nm soi2nm soi

Figure 8-13 Vt roll-off Vs Lg for 5nm and 2nm template Figure 8-14 Subthreshold Swing Vs Lg for different thicknesses for device with ground-plane (GP, template thicknesses for device with ground-plane Vbg=-0.2V) and without (soi) (GP, Vbg=-1V) and without (soi)

89

Figure 8‐14 plots subthreshold swing versus channel length. The value is about 69mV/decade for

ground‐plane device until 60nm channel length and begins to degrade below it. Ground‐plane

however significantly improves subthreshold slope. As expected, a thinner template results in a

better subthreshold slope. For 15nm BOX thickness, it can be shown that Ion/Ioff ratio is better for

a thinner template layer.

8.6 Conclusion Scaling the BOX thickness reduces fringing fields in the BOX and the lateral coupling of drain to

channel via the BOX. At thick BOX, reducing the permittivity, reduces DIBL through BOX.

However, at thin BOX, increasing the permittivity increases coupling between drain and

substrate allowing the field lines from drain penetrating the channel via silicon body to be

terminated on to substrate, thereby reducing DIBL through silicon body. Buried layer

engineering is an essential ingredient to scale FDSOI devices below 100nm gate length. In

particular for 15nm and 10nm gate length devices, the BOX thickness needs to be below 10nm. At

this thickness, a thicker template by virtue of higher permittivity would allow more ease in

meeting the ITRS specifications.

8.7 References [1] T. Ernst, and S. Cristoloveanu, “The ground‐plane concept for the reduction of short‐channel effects in fully depleted SO1 devices,” Electrochem. Soc. Proc., 1999, 99, (3), p. 329 [2] T. Numata, K. Uchida, J. Koga, and S. Takagi, “Device design for subthreshold slope and threshold‐voltage control in sub‐100 nm fully‐depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 2161‐2167, Dec. 2004 [3] T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, “Fringing field in sub‐0.1 um fully depleted SOI MOSFETs: Optimization of the device architecture,” Solid State Electron., vol. 46, pp. 373–378, 2002 [4] A. Vandooren et al., “Scaling assessment of fully‐depleted SOI technology at the 30nm gate length generation,” in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 25–26. [5] V. P. Trivedi and J. G. Fossum, “Nanoscale FD/SOI CMOS: Thick or thin BOX,” IEEE Electron Device Lett., vol. 26, no. 1, pp. 26–28, Jan. 2005 [6] T. Ernst and S. Cristoloveanu, “Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture,” in Proc. IEEE Int. SOI Conf., 1999, pp. 38‐39. [7] R. Koh, “Buried layer engineering to reduce the drain‐induced barrier lowering of sub‐0.05 μm SOI‐MOSFET,” Jpn. J. Appl. Phys., vol. 38, no. 4B, pp. 2294–2299, 1999

90

[8] H.‐S. Wong, D. Frank, and P. Solomon, “Device design considerations for double‐gate, ground‐plane, and single‐gated ultra thin SOI MOSFET’s at the 25 nm channel length generation,” in Proc. Int. Electron Devices Meeting, 1998, p. 407. [9] K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, and S. Deleonibus, “Advanced SOI MOSFETʹs with buried alumina and ground plane: Self‐heating and short channel effects,” Solid‐State Electron, vol. 48, pp. 907‐917, 2004. [10] J. Pretet, S. Monfray, S. Cristoloveanu and T. Skotnicki, “Silicon‐on‐nothing MOSFETs: performance, short‐channel effects, and backgate coupling,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 240‐244, Feb. 2004 [11] M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, and S. Monfray, “Silicon‐on‐Nothing (SON)‐an innovative process for advanced CMOS,” IEEE Trans. Electron Devices, vol. 47, pp. 2179–2187, Nov. 2000 [12] T. Numata, T. Mizuno, T. Tezuka, J. Koga, and S. Takagi, “Control of threshold voltage and short channel effects in ultra‐thin strained‐SOI CMOS devices,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1780‐1786, Aug. 2005

91

Chapter 9 Device Design Optimization 9.1 Introduction In chapter 7 and chapter 8, short channel effects degrading device performance of sub‐100nm

fully depleted SOI devices were discussed. Device design parameters to control the threshold

voltage and suppress short channel effects were studied. The major design parameters are silicon

body thickness, silicon body doping, buried oxide thickness, substrate doping, back‐gate bias and

gate workfunction. The above parameters can be adjusted to achieve the desired device

performance in terms of reduced off‐state leakage or increased drive current or steep

subthreshold slope or reduced drain‐induced barrier lowering. In this chapter, device design

parameters for devices with gate lengths 60nm, 45nm, 30m, 15nm and 10nm are specified. The

design specifications are set in order to meet the ITRS High Performance Logic Technology (ITRS’

2005) target for Ion/Ioff ratio. If instead of Ion/Ioff ratio, the performance target is DIBL or

subthreshold slope, then the device parameters would need to be adjusted and would be

different. However, for this work, and for the devices based on epitaxial buried oxide, devices are

designed with regards to meeting the Ion/Ioff ratio specification by ITRS.

9.2 60nm Gate Length For 60nm gate length device, the ITRS target values for subthreshold leakage current and drive

current are 1E‐8A/um and 0.9mA/um respectively. It was shown in Chapter 5, that the targets are

met for 60nm device without the need for ground plane. Thus, final device design parameters for

the device are,

1. Silicon body thickness TSi=7nm

2. Buried oxide thickness TBox=15nm

3. Undoped silicon body

92

4. Lowly doped substrate 1E15cm‐3 without ground‐plane

5. Back‐gate bias of 0V

6. Gate workfunction of 4.53eV.

Figure 9‐1 plots Id‐Vg curves for device with above parameters for different template thicknesses.

For any template thickness, the off‐state current value, Ioff is less than the ITRS specified value.

Figure 9‐1 Id‐Vg plot for Lg=60nm for different template thicknesses. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um. The off‐state leakage current for different template thicknesses is less than the ITRS specified

value by almost an order of magnitude or 89% for 5nm thick template, 93% for 4nm thick

template, 96% for 3nm thick template and 97.6% for 2nm thick template. The drive current or Ion

values for either template thickness is larger than the ITRS target value of 0.9mA/um.

ITRS Ioff 1E-8

93

Table 9‐1 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The

definition of threshold voltage used is the gate bias that results in a drain current, IDS = (W/Lmet) x

10‐7 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V.

Subthreshold swing is measured at a drain bias of 1V.

Table 9‐1 Threshold voltage, Ioff, Ion, Subthreshold swing and DIBL values for 60nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 1E‐8A/um and 0.9mA/um

Template Vt (V) Ioff(A/um) Ion (mA/um) SS (mV/decade) DIBL (mV)

5nm 0.23 1.10E-09 0.961 79.1 45.4

4nm 0.24 7.10E-10 0.955 76.5 42.3

3nm 0.25 4.40E-10 0.947 73.9 39.6

2nm 0.26 2.60E-10 0.937 72.1 36.4 From Table 9‐1 it is inferred that for the design parameters listed above, the average threshold

voltage is 0.24V, subthreshold swing is 75mV/decade and DIBL is 41mV. While the threshold

voltage is low enough and so is DIBL, the subthreshold swing seems a little too far off from the

ideal value of 60mV/decade at room temperature. However, device has been designed to meet

the Ion/Ioff requirements and not specifically for subthreshold slope. If subthreshold slope needs

to be improved, the device can be re‐engineered.

For example, if the workfunction is increased from 4.53eV to 4.7eV, a ground plane included in

the substrate under the gate and back‐gate voltage decreased from 0V to ‐1V, keeping all other

parameters the same, the subthreshold swing for the 5nm thick template case, reduces from

79.1mV/decade to 70mV/decade and Ioff reduces from 1.1E‐9 A/um to 1.4E‐15 almost by five

orders of magnitude. However, the demerit is the reduction in Ion from 0.96mA/um to

0.3mA/um For the ground plane device with 4.7eV workfunction, as the back gate voltage is

decreased from ‐0.2V to ‐1V, subthreshold swing improves from 73mV/decade to 70mV/decade

and Ioff falls from 5E‐14A/um to 1.4E‐15A/um. The device design parameters listed in the above

table therefore represents one set of solutions designed for device to meet specifically the Ion/Ioff

ratio specification.

94


current are 3E‐8A/um and 0.98mA/um respectively. It was shown in Chapter 5, that the Ion/Ioff

ratio target is met for 45nm device without the need for ground plane for all template thicknesses

except 5nm. A ground‐plane structure is, therefore, included to suppress the short channel

effects and meet target values for all template thicknesses. Thus, final device design parameters

for the device are,




4. Lowly doped substrate 1E15cm‐3 with ground‐plane doped 5E18cm‐3

5. Back‐gate bias of 0.2V




The off‐state leakage current for different template thicknesses is less than the ITRS specified

value by almost an order of magnitude or 95% for 5nm thick template, 96.4% for 4nm thick

template, 97.7% for 3nm thick template and 98.7% for 2nm thick template. The drive current or

Ion values for either template thickness is larger than the ITRS target value of 0.98mA/um.





From Table 9‐1 it is inferred that for the design parameters listed above, the average threshold

voltage is 0.265V, subthreshold swing is 86.4mV/decade and DIBL is 62.5mV. As was the case

with 60nm device, while the threshold voltage is low enough and so is DIBL, the subthreshold

swing seems a little too far off from the ideal value of 60mV/decade at room temperature.

95

Figure 9‐2 Id‐Vg plot for Lg=45nm for different template thicknesses. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.

However, device has been designed to meet the Ion/Ioff requirements and not specifically for

subthreshold slope. If subthreshold slope needs to be improved, the device can be re‐engineered.



5nm 0.25 1.5E-09 1.006 89.5 73.9

4nm 0.26 1.1E-09 1.005 87.2 67.6

3nm 0.27 6.9E-10 1.003 85.2 59.1

2nm 0.28 3.9E-10 0.995 83.7 49.2

ITRS Ioff 3E-8A/um

96

For example, if the workfunction is increased from 4.53eV to 4.7eV, and back‐gate voltage

decreased from 0.2V to ‐1V, keeping all other parameters the same, the subthreshold swing for

the 5nm thick template case, reduces from 89.5mV/decade to 76.87mV/decade and Ioff reduces

from 1.5E‐9 A/um to 6.7E‐14 almost by five orders of magnitude. However, the demerit is the

reduction in Ion from 1mA/um to 0.764mA/um. As the back gate voltage is decreased from ‐0.2V

to ‐1V, subthreshold swing improves from 85mV/decade to 76.87mV/decade and Ioff falls from

2.7E‐12A/um to 6.7E‐14A/um.

The device design parameters listed in the above table therefore represents one set of solutions

designed for device to meet specifically the Ion/Ioff ratio specification


current are 5E‐8A/um and 1.09mA/um respectively. It was shown in Chapter 5, that the Ion/Ioff

ratio target is not met for 30nm device without ground plane for any template thickness. A

ground‐plane structure is, therefore, included to suppress the short channel effects and meet

target values for all template thicknesses. Thus, final device design parameters for the device are,





5. Back‐gate bias of ‐0.85V





value by 54% for 5nm thick template, 62% for 4nm thick template, 74% for 3nm thick template

and 87% for 2nm thick template. The drive current or Ion values for either template thickness is

larger than the ITRS target value of 1.09mA/um.

97

Figure 9‐3 Id‐Vg plot for Lg=30nm for different template thicknesses. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um. Table 9‐3 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The






5nm 0.20 2.30E-08 1.195 116.5 146.2

4nm 0.20 1.90E-08 1.194 112.8 144.1

3nm 0.21 1.30E-08 1.191 106.9 135.6

2nm 0.22 6.40E-09 1.178 100.0 121.6

ITRS Ioff 5E-8A/um

98



voltage is low enough, the subthreshold swing is reasonable. For DIBL, a value less than 100mV

is generally considered a good value.

As before, the device can be re‐engineered to further reduce DIBL and improve subthreshold

swing. For example, if the silicon body thickness reduced from 7nm to 5nm, workfunction

increased from 4.53eV to 4.7eV and back‐gate voltage decreases from ‐0.85V to ‐1V, subthreshold

swing for 5nm thick template case reduces from 116.5mV/decade to 96.5mV/decade and DIBL

improves from 146.2mV to 119mV. Thus, device design parameters specified in above table refer

to only one possible set of solutions designed for device to meet the Ion/Ioff ratio target.

Figure 9‐4 Id‐Vg plot for Lg=30nm for 5nm and 4nm thick template at Tbox=15nm and 10nm. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.

It was shown in chapter 8 that for ground plane device, a low‐k buried oxide yields slightly

larger DIBL and therefore larger off‐state leakage current at BOX thickness below a critical value.

99

Since, the substrate in 60nm, 45nm and 30nm devices is lowly doped 1E15cm‐3 as against 1E18cm‐

3 used for simulations in chapter 8, the critical BOX thickness occurs at less than 15nm. Therefore,

at Tbox=10nm, a thinner template thickness should yield larger off‐state current by virtue of

smaller effective BOX permittivity. Figure 9‐4 plots Id‐Vg curves for 5nm and 4nm thick

templates for TBox=15nm and 10nm. The metal workfunction is 4.53eV and back‐gate voltage is ‐

0.2V. It is observed that while at Tbox=15nm, 5nm thick template yields larger Ioff, at Tbox=10nm, it

yields lower Ioff compared to 4nm thick template. Therefore, if the 30nm device is engineered

with a 10nm BOX thickness, ITRS Ioff requirement will be met with ease however, a thinner

template would yield a larger off‐state leakage current. Also to be noted from Figure 9‐4 is that,

keeping all other device parameters the same, Tbox=10nm results in a steeper subthreshold slope

and smaller DIBL but at the cost of slightly reduced drive current.

9.5 25nm Gate Length

For 25nm gate length device, the ITRS target values for subthreshold leakage current and drive

current are 1.7E‐7A/um and 1.48mA/um respectively. It was shown in Chapter 5, that the Ion/Ioff



target values for all template thicknesses. Thus, final device design parameters for the device are,





5. Back‐gate bias of ‐0.7V






100


however smaller than the ITRS target value of 1.48mA/um. Nevertheless the Ion/Ioff target is

met.

Figure 9‐5 Id‐Vg plot for Lg=25nm for different template thicknesses. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.







voltage is low enough, the subthreshold swing is large. For DIBL, a value less than 100mV is

generally considered a good value. However, for 25nm gate length device, this DIBL value is

very reasonable.

ITRS Ioff 1.7E-7A/um

101

Table 9‐4 Threshold voltage, Ioff, Ion, Subthreshold swing and DIBL values for 25nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 1.7E‐7 A/um and 1.48mA/um


5nm 0.22 5.1E-08 0.789 172.1 311.4

4nm 0.23 3.8E-08 0.787 165.6 296.5

3nm 0.26 2.1E-08 0.776 155.8 270.1

2nm 0.30 7.9E-09 0.755 145.6 233.2

The above set of device design parameters meets the Ion/Ioff target. However, this represents

only one out of several possible device designs. Discussed below are other device design options.

I. TSi=7nm, TBox=10nm, Workfunction =4.6eV

If the Workfunction is 4.6eV and BOX thickness is 15nm, then the ITRS target for 5nm thick

template is not met even with –1V bias on the back‐gate. In order to avoid doping the silicon

body, the BOX thickness must be scaled keeping the Workfunction as the same. With ΦM=4.6eV

and TBox=10nm, the back‐gate bias needs to be at least ‐0.2V which results in an Ioff of 6.2E‐8A/um

and Ion of 1.17mA/um. If the back‐gate bias is ‐0.1V, resulting Ioff is 1.1E‐7A/um which doesn’t

meet the target. Thus, with TSi=7nm, TBox=10nm, and workfunction =4.6eV, the range of back‐gate

bias is Vbg≤‐0.2V.

II. TSi=7nm, TBox=10nm or 15nm, Workfunction =4.7eV

If the workfunction is increased to 4.7eV, the ITRS target for 5nm thick template can be met with

15nm BOX thickness unlike the case above for ΦM=4.6eV. However this requires a back‐gate bias

of Vbg≤‐0.8V. At Vbg=‐0.8V, resulting Ioff and Ion are 9.94E‐8A/um and 1mA/um respectively. If

the workfunction is kept the same, and BOX thickness is scaled to 10nm, the range on back‐gate

bias is increased to Vbg≤0V which provides more tunability. As Vbg is decreased from 0V to ‐0.4V,

Ioff reduces from 5.5E‐8A/um to 4E‐9A/um and Ion from 0.948mA/um to 0.825mA/um

respectively.

102

III. TSi=7nm, TBox=10nm or 15nm, Workfunction =4.8eV

If the workfunction is increased to 4.8eV, the ITRS target for 5nm thick template can be met with

15nm BOX thickness with a back‐gate bias of Vbg≤‐0.4V. At Vbg=‐0.4V, resulting Ioff and Ion are

1.2E‐7A/um and 0.834mA/um respectively. And at Vbg=‐0.7V, as shown in the table above,

resulting Ioff and Ion are 5.1E‐8A/um and 0.789mA/um respectively. If the BOX thickness is

scaled to 10nm, the target can be met at Vbg=0V resulting in Ioff and Ion as 1.5E‐8A/um and

0.707mA/um respectively.

Figure 9‐6 Id‐Vg plot for Lg=25nm for two device design parameters. TSi=7nm and 5nm thick template for both. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um. Figure 9‐6 plots Id‐Vg curves for 5nm thick template for two device design conditions. For

TBox=15nm and ΦM=4.8eV, the back‐gate bias is adjusted to be ‐0.7V and for second case with

TBox=10nm and ΦM=4.6eV, Vbg is adjusted to be ‐0.3V so that both result in same Ioff of 3.5E‐

8A/um. It is clear that, for same Ioff, a thinner Box thickness, TBox=10nm results in a much steeper

subthreshold slope and therefore larger drive current. A major reason for scaling BOX thickness


103

is the improvement in subthreshold swing. However, a thin BOX also increases parasitic

source/drain – substrate capacitances and undermines that advantage of using SOI substrate.

With regards to this, the device solution for 25nm gate length involves 15nm BOX thickness.

Figure 9‐7 Id‐Vg plot for Lg=25nm for 5nm and 4nm thick template at Tbox=15nm and 10nm. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.

Figure 9‐7 plots Id‐Vg curves for 5nm and 4nm thick templates for TBox=15nm and 10nm. The

metal workfunction is 4.8eV and back‐gate voltage is 0V. It is observed that while at Tbox=15nm,

5nm thick template yields larger Ioff, at Tbox=10nm, it yields lower Ioff compared to 4nm thick

template. This is due to the BOX permittivity role reversal below critical thickness as discussed in

chapter 8. Therefore, if the 25nm device is engineered with a 10nm BOX thickness, ITRS Ioff

requirement will be met with more ease for a thicker template layer by virtue of a higher BOX

permittivity.

104






target values for all template thicknesses. It was discussed in chapter 8 that TBox <Lg/2 is required

for substantive reduction of DIBL. Keeping this in view, 6nm Box thickness is chosen. However,

since this is below the critical thickness, a thinner template would find difficult to meet the ITRS

target. Also, silicon body thickness is reduced to 5nm to suppress short channel effects. Thus,

final device design parameters for the device are,





5. Back‐gate bias is adjusted to be ‐0.2V(5nm template), ‐0.6V(4nm template), ‐0.9V(3nm

template, ‐1V(2nm template)







however smaller than the ITRS target value of 2.03mA/um. Nevertheless the Ion/Ioff target is

met.



105



Figure 9‐8 Id‐Vg plot for Lg=15nm for different template thicknesses. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um. Table 9‐5 Threshold voltage, Ioff, Ion, Subthreshold swing and DIBL values for 15nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 2.9E‐7 A/um and 2.03mA/um


5nm 0.19 3.47E-08 1.28 131.5 221.8

4nm 0.17 5.57E-08 1.35 135.2 230.3

3nm 0.15 7.98E-08 1.41 135.3 242.7

2nm 0.11 1.36E-07 1.50 141.2 255.2


106


voltage is 0.16V, subthreshold swing is 136mV/decade and DIBL is 237mV. The threshold voltage

is low enough. The subthreshold swing is good for 15nm device and DIBL is small enough. The

above set of device design parameters meets the Ion/Ioff target. However, this represents only

one out of several possible device designs. Discussed below are other device design options.

I. TSi=5nm, TBox=6nm, Workfunction=4.53eV

If the Workfunction is 4.53eV and BOX thickness is 6nm, then the ITRS target for 5nm thick

template is with back‐gate bias of Vbg<0V. The ITRS target for Ioff and Ion are 2.9E‐7A/um and

2.03mA/um. As Vbg is decreased from ‐0.1V to ‐0.6V, Ioff decreases from 6.4E‐8A/um to 3.2E‐

9A/um and Ion from 1.35mA/um to 1.02mA/um. The subthreshold swing improves from

139mV/decade to 116.5mV/decade. For 4nm thick template, the back‐gate bias needs to be Vbg<‐

0.4V. For 3nm thick template, Vbg<‐0.8V and for 2nm thick template, Vbg<‐1V. However, at the

same value of back‐gate bias, a thinner template yields larger off‐state leakage current. Therefore,

the device performance specifications are easier to meet with thicker template.

For 4nm thick template case, as Vbg is decreased from ‐0.4V to ‐1V, Ioff decreases from 1.4E‐

7A/um to 7.8E‐9A/um and Ion from 1.46mA/um to 1.15mA/um. The subthreshold swing

improves from 141mV/decade to 119mV/decade. For 3nm thick template case, as Vbg is decreased

from ‐0.8V to ‐V, Ioff decreases from 1.1E‐7A/um to 5.3E‐8A/um and Ion from 1.46mA/um to

1.37mA/um. The subthreshold swing improves from 135mV/decade to 134mV/decade. For 2nm

thick template case, Vbg=‐1V yields Ioff of 1.36E‐7A/um, Ion of 1.5mA/um and subthreshold

swing of 141,2mV/decade.

The Ioff target is met easily but Ion values are smaller than the desired value. Nevertheless,

Ion/Ioff target is met.

II. TSi=5nm, TBox=6nm, Workfunction=4.6eV

When the workfunction is increased to 4.6eV, the constraint on back‐gate voltage is less harsh for

same value of Ioff. With ΦM=4.6eV, the back‐gate bias needs to be, Vbg<0V for 5nm thick template,

Vbg<‐0.2V for 4nm thick template, Vbg<‐0.5V for 3nm thick template and Vbg<‐0.7V for 2nm thick

template. For 5nm thick template, as Vbg decreases from 0V to ‐0.8V, Ioff reduces from 3.9E‐

107

8A/um to2.6E‐10A/um, Ion from 1.22mA/um to 0.719mA/um and subthreshold swing from

139mV/decade to 114mV/decade. For 4nm thick template, Vbg=‐0.4v results in Ioff of 4.7E‐8A/um,

Ion of 1.26mA/um and subthreshold swing of 137mV/deacde. For 3nm thick template, as Vbg

decreases from ‐0.5V to ‐0.8V, Ioff reduces from 1.6E‐7A/um to 3.6E‐8A/um, Ion from 1.39mA/um

to 1.25mA/um and subthreshold swing from 142mV/decade to 135mV/decade. For 2nm thick

template, Vbg=‐0.9V and ‐1V result in 1E‐7A/um and 6.4E‐8A/um of off‐state leakage current both

meeting the ITRS target.

Figure 9‐9 Id‐Vg plot for Lg=15nm for 4nm thick template. TSi=5nm, TBox=6nm, ΦM=4.53eV. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.

Figure 9‐9 plots Id‐vg curves for ΦM=4.53eV and 4nm template thickness for four different back‐

gate voltages. While Ioff target is not met at Vbg=‐0.2V, it is met with most ease at Vbg=‐1V. Figure

9‐10 plots Id‐Vg curves for ΦM=4.53eV and Vbg=‐1V for different template thicknesses. It verifies

the fact that at TBox=6nm, keeping all other parameters the same, a thicker template yields a

smaller Ioff by virtue of a higher BOX permittivity.


108

Figure 9‐10 Id‐Vg plot for Lg=15nm with TSi=5nm, TBox=6nm, ΦM=4.53eV and Vbg=‐1V. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.

Thus, several device design parameters meeting the target have been discussed. The important

thing to note is that Ion/Ioff ratio target is met without the need for silicon channel doping. With

BOX thickness as thin as 6nm, the workfunction requirement is 4.53eV or 4.6eV unlike a high

value as 4.8eV like for 25nm device.






target values for all template thicknesses. It was discussed in chapter 8 that TBox <Lg/2 is required

for substantive reduction of DIBL. This means that BOX thickness needs to be as thin as 5nm.


109

And since this is below the critical thickness, a thinner template would find difficult to meet the

ITRS target. Silicon body thickness needs to be as thin as 5nm to suppress short channel effects.

Thus, final device design parameters for the device are,


2. Buried oxide thickness TBox=6nm ( for 5nm and 4nm thick template) and 4nm (for 3nm

and 2nm thick template)



5. Back‐gate bias is adjusted to be ‐0.4V(5nm template), ‐1V(4nm template), ‐0.3V(3nm

template, ‐0.7V(2nm template)

6. Gate workfunction is adjusted to be 4.8eV(5nm template), 4.98eV(4nm template),

5.3eV(3nm template) and 5.45eV(2nm template)

Figure 9‐11 Id‐Vg plot for Lg=10nm for different template thicknesses The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.


110

Figure 9‐11 plots Id‐Vg curves for device with above parameters for different template

thicknesses. For any template thickness, the off‐state current value, Ioff is less than the ITRS

specified value.




however smaller than the ITRS target value of 2.1.8mA/um. Nevertheless the Ion/Ioff target is

met. As can be observed the device design parameters are different for different thicknesses of

template. When template is 5nm thick, the effective BOX permittivity is 28.0 and ITRS target is

met with a good subthreshold slope. However, as template thickness reduces, increase in BOX

permittivity makes it harder to achieve the target. This is the reason why 5nm and 4nm thick

templates require TBox=5nm whereas 3nm and 2nm thick templates need TBox=4nm. Even the gate

workfunction increases from 4.8eV for 5nm thick template to 5.3eV for 2nm thick template.





Table 9‐6 Threshold voltage, Ioff, Ion, Subthreshold swing and DIBL values for 10nm device designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 3.7E‐7 A/um and 2.18mA/um


5nm 0.28 1.80E-08 0.785 160.0 360

4nm 0.29 2.55E-08 0.652 186.5 460

3nm 0.42 1.73E-08 0.228 233.1 480

2nm 0.48 1.38E-08 0.122 247.0 490

111


voltage is 0.36V, subthreshold swing is 206mV/decade and DIBL is 447mV. The subthreshold

swing and DIBL are large. A good way to improve those would be to dope the silicon channel

which however is not a good option because of dopant induced Vt fluctuation and mobility

degradation. The above set of device design parameters meets the Ion/Ioff target. However, this

represents only one out of several possible device designs. Discussed below are other device

design options.

I. TSi=5nm, TBox=5nm, 5nm Template Thickness

Figure 9‐12 plots Id‐Vg curves for 5nm template thickness for three different values of gate‐

workfunction. Silicon body and BOX thickness is 5nm. Back‐gate bias is ‐0.4V. If the gate‐

workfunction increases from 4.6eV to 4.8eV, off‐state leakage current drops from 2.9E‐7A/um to

1.8E‐8A/um and Ion from 1.32mA/um to 0.785mA/um. With workfunction of 4.8eV, while Vbg=‐

0.2V yields 6.5E‐8A/um of leakage current, Vbg=‐0.4V reduces it to 1.8E‐8A/um. Subthreshold

swing degrades slightly from 178.6mV/decade to 160mV/decade.

Figure 9‐12 Id‐Vg plot for Lg=10nm with TSi=5nm, TBox=5nm, Vbg=‐0.4V and variable ΦM. The parameter on x‐axis is gate‐voltage in volts and on y‐axis is drain current in A/um.


112

II. TSi=5nm, TBox=5nm, 4nm Template Thickness

With ΦM=4.8eV, Vbg=‐0.8V results in Ioff=5E‐7A/um and doesn’t meet the target. When back‐gate

voltage is reduced to Vbg=‐1V, Ioff reduces to 2.1E‐7A/um and resulting Ion is 1.13mA/um. The

ITRS Ioff target is also met with ΦM=5.0eV and Vbg<‐0.4V until Ion decreases by a large amount

and ITRS Ion/Ioff ratio target is not met. The chosen set of device parameters however are

ΦM=4.98eV and Vbg=‐1V.

II. TSi=5nm, TBox=4nm, 3nm Template Thickness

If BOX thickness is retained at 5nm, the gate‐workfunction needs to be increased to more than

5.3eV. For (ΦM, Vbg) = {5.3eV, ‐1V}, Ioff is 3.6E‐8A/um and Ion is 0.289mA/um. The Ion/Ioff ratio is

8E3A/A. If ΦM is increased to 5.44eV and Vbg is kept the same, resulting Ioff and Ion are 1.2E‐

8A/um and 0.123mA/um respectively. The Ion/Ioff ratio increases to 1E4A/A. If ΦM is increased

further, one would expect a drop in Ioff and therefore rise in Ion/Ioff ratio. However, Ion drops

by a large amount by virtue of increase in threshold voltage so the Ion/Ioff ratio is not improved.

For ΦM=5.5eV and Vbg=‐1V, Ioff reduces to 7.4E‐9A/um but Ion becomes a meager 7.8E5A/um. The

resulting Ion/Ioff ratio is thus 9.8E3A/A smaller than that for ΦM=5.44eV case. In order to achieve

a larger Ion/Ioff ratio, the BOX thickness is reduced to 4nm and so for same template thickness of

2nm, the BOX permittivity is increased which provides more ease in achieving the target. At

TBox=4nm while (ΦM, Vbg) = {5.3eV, ‐0.3V} results in {Ioff, Ion} = {1.7E‐8A/um, 0.228mA/um}, (ΦM,

Vbg) = {5.4eV, ‐0.3V} results in {Ioff, Ion} = {7.4E‐9A/um, 0.114mA/um. The Ion/Ioff ratio is

1.3E4A/A for the former and 1.5E4A/A for the latter.

III. TSi=5nm, TBox=4nm, 2nm Template Thickness

At TBox=4nm and ΦM=5.45eV, as Vbg is reduced from ‐0.7V to ‐0.9V, Ioff reduces from 1.4E‐8A/um

to 4.3E‐9A/um, Ion from 0.122mA/um to 8.2E‐5A/um and consequently Ion/Ioff ratio increases

from 8.8E3A/A to 1.9E4A/A.

The device design considerations for 10nm gate length device were discussed. Even though the

ITRS Ion/Ioff ratio targets are met with undoped silicon body, the subthreshold slope and DIBL

are large. Some improvement can result in by doping the silicon channel. However even then, the

device under consideration would perform better than standard SOI device. This is because, at

such thin BOX thickness as needed for 10nm device, a high‐k BOX yields lesser DIBL and greater

ease in meeting the target off‐state leakage values.

113

9.8 Meeting ITRS Ion/Ioff Specification

The goal of device modeling was to design the device so that ITRS High Performance Logic

Technology specifications are met at every gate length. Figure 9‐13 plots Ion/Ioff ratio as specified

by ITRS and as designed, for different gate lengths. It has been shown in previous sections that

ITRS specifications can be met for any gate length with undoped silicon body and for any

template thickness. Because, 15nm and 10nm devices require an ultra‐thin BOX with thickness

below critical thickness as described in chapter 8, a thicker template yields a larger Ion/Ioff ratio.

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08


Channel Length (nm)

Ion/

Ioff

5nm4nm3nm

2nmITRS'05 HP Logic

Figure 9‐13 ITRS expected and Simulated Ion/Ioff ratio versus channel length

Figure 9‐14 shows an alternate representation of Ion/Ioff ratios versus channel length. The

vertical bars corresponding to different template thicknesses are larger than that corresponding

to the ITRS specification suggesting that the target is met for every template thickness and at

every gate length. For 15nm and 10nm gate lengths, a thinner template results in smaller Ion/Ioff

ratio. Table 9‐7 summarizes device design parameters for all gate‐lengths as discussed in detail

in above sections.

114

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

10 15 25 30 45 60

Channel Length (nm)

Ion/

Ioff

5nm4nm3nm

2nmITRS'05 HP Logic

Figure 9‐14 ITRS expected and Simulated Ion/Ioff ratio versus channel length Table 9‐7 Summary of device design parameters to meet ITRS HP Logic Ion/Ioff specification for different channel lengths. Except for 60nm, all other gate‐length devices employ ground‐plane. Substrate doping is 1E15cm‐3 and p+ ground‐plane implant is 5E18cm‐3

Channel Length Lg

(nm)

Silicon Body Thickness TSi

(nm)

BOX Thickness TBox (nm)

Gate Workfunction ΦM (eV)

Back‐gate Bias Vbg (V)

Body Doping (cm‐3)

60 7 15 4.53 0.00 Undoped

45 7 15 4.53 0.20 Undoped

30 7 15 4.53 ‐0.85 Undoped

25 7 15 4.80 ‐0.70 Undoped

15 5 6 4.53 5nm: ‐0.2V 4nm: ‐0.6V 3nm: ‐0.9V 2nm: ‐1.0V

Undoped

10 5 5nm: 5 4nm: 5 3nm: 4 2nm: 4

5nm: 4.80 4nm: 4.98 3nm: 5.30 2nm: 5.45

5nm: ‐0.4V 4nm: ‐1.0V 3nm: ‐0.3V 2nm: ‐0.7V

Undoped

115

9.9 Conclusion In this chapter it has been shown that epitaxial‐oxide based SOI device can meet ITRS Ion/Ioff

target down to 10nm channel length. The device design parameters for each gate‐length device

were discussed. While buried oxide is 15nm thick for until 25nm gate‐length device, it becomes

as thin as 4nm for 10nm gate‐length device. Silicon body thickness is small to make sure full‐

depletion and suppressed DIBL through silicon body. It becomes as thin as 5nm for 15nm and

10nm gate‐length devices. The silicon body is undoped for all gate‐lengths. This avoids the

problems associated with very high channel doping. The gate‐workfunction is 4.53eV for until

30nm gate‐length and increases to 5.45eV for 10nm device. As long as the buried oxide is thick,

15nm, a thinner template material results in a larger Ion/Ioff ratio. However, for 10nm and 15nm

devices, that require, BOX thickness below critical thickness of about 10nm, a thinner template

material gets hard to meet the ITRS target with. Thus, while high‐k template oxide is not a

favorable option at thick BOX, it provides better device performance and scalability at thin BOX.

Nevertheless, it has been shown that despite high‐k template, ITRS Ion/Ioff target can be met for

any channel length.

116

Chapter 10 Conclusion and Future Work 10.1 Conclusion The goal of this work was to demonstrate that high‐k template oxide won’t hurt device

performance significantly and that ITRS Ion/Ioff specifications can be met for any gate length.

Two dimensional device modeling has shown that Floating Epitaxy based SOI devices can meet

ITRS Ion/Ioff specifications down to 10nm channel length for any thickness of template material

between 2nm and 5nm.. This however requires appropriate device design. While ground‐plane is

essential to suppress short channel effects associated with buried oxide; silicon body thickness,

back‐gate bias and gate workfunction are important device design parameters that control

threshold voltage. Buried layer engineering is another option for reducing short channel effects. It

requires appropriate selection and modeling of these parameters to meet the ITRS target and

ensuring good subthreshold slope and small DIBL at the same time.

A major conclusion as part of this work is also that, while high‐k BOX causes more DIBL at thick

BOX, it slightly helps device performance at thin BOX by resulting in lesser DIBL. Therefore, for

very small devices, in sub‐15nm regime, which require ultra thin buried oxides, a high

permittivity will be of more advantage. This is because; a high permittivity BOX is more capable

of causing field lines from drain to terminate on substrate rather than channel thereby reducing

DIBL through silicon body.

It can be concluded that future SOI devices based on epitaxial‐buried oxide as discussed in this

work will not only guarantee expected device performance but will also solve much of the

problems associated with SOI manufacturing today from ease of fabrication and cost perspective.

117

10.2 Future Work Now that the device modeling has been done, devices will be fabricated on wafer samples

available of the floating epitaxy substrate. Devices of varying gate‐length and template thickness

will be fabricated. Device characterization and measurements will reveal the device performance

from perspective of short channel effects and Ion/Ioff ratio.

Thesis

Documents

ultrathin body soi devices

depleted soi devices

sub15nm devices

thesis work

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floating epitaxy soi

nanoscale device design

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