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THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept. Indus University 1
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THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

Mar 31, 2015

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Page 1: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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THE 8253 IC(PIT)

Vatsal N Shah – IU1241090055Sharon Benedict – IU1241090056

Microprocessor & Interfacing

Electronics and Communication Engineering Dept.Indus University

Page 2: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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What is 8253?

Contents

PIN-DIAGRAM OF 8253

ARCHITECTURE OF 8253

MODES OF 8253

Interfacing with 8085

References

Page 3: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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What is 8253?

• The Intel 8253 is a programmable counter.• It includes 3 identical 16 bit counters.• It is packaged in a 24-pin DIP.• Six programmable modes.• Gate is used to enable or disable the counter.

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ARCHITECTURE OF 8253

D7-D0

RDWRA0A1

CS

DATABUSBUFFER

READ/WRITELOGIC

CONTROLWORD REGISTER

COUNTER 0

COUNTER 1

COUNTER 2

CLK 0

GATE 2

OUT 1

OUT 0

OUT 2

GATE 1

GATE 0

CLK 2

CLK 1

Page 5: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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D7

D1

D0

OUT 0

GATE 0

GND

D6

D5

D4

D3

D2

CLK 0

8253

VCC

OUT 2

GATE 2

CLK 1

OUT 1

GATE 1

RD

CS

A1

A0

CLK 2

WR

PIN DIAGRAM OF 8253

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Data Bus Buffer:• This block contains the logic to buffer the data bus to the

microprocessor and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.

Control Logic:• The control section has five signals: Read, Write, Chip select

and the address lines A0 and A1.• In peripheral I/O mode read and write signals are connected

to IOR and IOW while in memory mapped these are connected to MEMR and MEMW.

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• The control word register and counters are selected according to signals on lines A0 and A1 as shown below:

CS A1 A0 Select 0 0 0 Counter 0

0 0 1 Counter 1 0 1 0 Counter 2 0 1 1 Control Reg.

Control word Register:• This register is accessed when lines A0 and A1 are at logic

1.• It is used to write command word which specifies the

counter to be used, its mode and either read or write format.

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8253 Timer

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MODES OF 8253

MODE 0: Interrupt on terminal count.

MODE 1: Programmable 1 shot.

MODE 2: Rate generator.

MODE 3: Square wave generator.

MODE 4: Software triggered strobe.

MODE 5: Hardware triggered strobe.

Page 10: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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Mode 0: Interrupt on Terminal Count• The output will start off zero. The count is loaded and the

timer will start to count down.• When the count has reached zero the output will be set high,

and remain high until the next count has been reloaded.• This can be used as an interrupt.

Mode 1: Programmable One-Shot• The output will go low following the rising edge of the gate

input. • The counter will count and the output will go high once the

counter has reached zero.

Page 11: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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Mode 2: Rate Generator• This mode is used to generate a pulse equal to the clock

period at a given interval.• When count is loaded the OUT stays high until the count

reaches 1 and the the OUT goes low for one clock period.• The count is reloaded automatically and the pulse is

generated continuously.

Mode 3: Square Wave Generator• This mode is similar to mode 2. However, the duration of the

high and low clock pulses of the output will be different from mode 2.

Page 12: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

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• Suppose n is the number loaded into the counter (the COUNT message), the output will be:

• high for n/2 counts, and low for n/2 counts, if n is even.• high for (n+1)/2 counts, and low (n-1)/2 for counts, if n is odd

Mode 4: Software Triggered Pulse. • The output will remain high until the timer has counted to

zero, at which point the output will pulse low and then go high again.

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Mode 5: Hardware Triggered Pulse • The counter will start counting once the gate input goes high,

when the counter reaches zero the output will pulse low and then go high again.

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Modes of Operation of 8253

Page 15: THE 8253 IC (PIT) Vatsal N Shah – IU1241090055 Sharon Benedict – IU1241090056 Microprocessor & Interfacing Electronics and Communication Engineering Dept.

8253 Example

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