OPERATING MODES AND THEIR REGULATIONS OF VOLTAGE-SOURCED CONVERTER BASED FACTS CONTROLLERS By Xia Jiang A Thesis Submitted to the Graduate Faculty of Rensselaer Polytechnic Institute in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Major Subject: Electrical Engineering Approved by the Examining Committee: Joe H. Chow, Thesis Adviser Sheppard J. Salon, Member Jian Sun, Member Murat Arcak, Member Behruz Fardanesh, Member Abdel-Aty Edris, Member Rensselaer Polytechnic Institute Troy, New York March 2007 (For Graduation May 2007)
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Tesis_ Operating Modes and Their Regulations of Voltage Sourced Converters Based FACTS Controllers
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OPERATING MODES AND THEIR REGULATIONSOF VOLTAGE-SOURCED CONVERTER BASED
FACTS CONTROLLERS
By
Xia Jiang
A Thesis Submitted to the Graduate
Faculty of Rensselaer Polytechnic Institute
in Partial Fulfillment of the
Requirements for the Degree of
DOCTOR OF PHILOSOPHY
Major Subject: Electrical Engineering
Approved by theExamining Committee:
Joe H. Chow, Thesis Adviser
Sheppard J. Salon, Member
Jian Sun, Member
Murat Arcak, Member
Behruz Fardanesh, Member
Abdel-Aty Edris, Member
Rensselaer Polytechnic InstituteTroy, New York
March 2007(For Graduation May 2007)
OPERATING MODES AND THEIR REGULATIONSOF VOLTAGE-SOURCED CONVERTER BASED
FACTS CONTROLLERS
By
Xia Jiang
An Abstract of a Thesis Submitted to the Graduate
Faculty of Rensselaer Polytechnic Institute
in Partial Fulfillment of the
Requirements for the Degree of
DOCTOR OF PHILOSOPHY
Major Subject: Electrical Engineering
The original of the complete thesis is on filein the Rensselaer Polytechnic Institute Library
The resulting incremental P ,Q flows, denoted by ∆P and ∆Q with respect to
the uncompensated base case, on the series compensated line are shown in Figure
3.11, where the points correspond to those in Figure 3.10(a). Note that dispatch
traces are elliptically shaped ∆P -∆Q curves, which are not strongly dependent on
the shunt VSC reactive power injections. The regions contained in the ∆P -∆Q
curves are the feasible dispatchable flow of the UPFC, given the ratings of the
VSCs. The controllable line real power incremental flow ranges from −102 MW to
107 MW, and line reactive power incremental flow ranges from −112 Mvar to 120
Mvar.
40
-150
-100
-50
0
50
100
150
-150 -100 -50 0 50 100 150Line ∆P (MW)
Qsh=0.5 CapacitiveQsh=0.0Qsh=0.5 Inductive
1
2
345
6
7
8
9 1011
12
Figure 3.11: UPFC Series Line Incremental P -Q Curves
3.5.3.2 Maximum IPFC Dispatchability
In the IPFC configuration, the VSCs are inserted in series on two lines in
different paths of the same transfer interface of the system. The line compensated
by VSC 2 is normally heavily loaded in the nominal system without any VSCs. Here
the line flow regulation of the IPFC is demonstrated.
A. VSC 1 as the Master and VSC 2 as the Slave
In the first set of dispatch computation, VSC 1 is set as master VSC such that
its injected voltage magnitude reference is kept constant at 1.0 pu while its angle
varies with step variations of 20◦ for a set of 18 values, as shown in Figure 3.10(b).
The dispatch is computed for two injected voltage reference settings of the slave
VSC (VSC 2) (Figure 3.10(b)):
• (Case 1) Vqref = 0.23 pu,
41
• (Case 2) Vqref = 0.8 pu.
The resulting dispatch of the master and slave VSCs is shown in Figure 3.12.
Both the master and slave VSC ∆P -∆Q curves are shaped like ellipses, with the
slave ∆P -∆Q ellipses being more narrow and the points corresponding to those in
Figure 3.10(b). Note also that Case 2, which has a higher Vqref , results in about 60
MW and 20 Mvar more power flow on the slave SVC line and about 10 MW less
on the master line than Case 1. The master SVC line reactive power flows for both
cases are very close.
-100
-50
0
50
100
-100 -50 0 50 100Master Line ∆P (MW)
Case 1Case 2
-100
-50
0
50
100
-50 0 50 100 150Slave Line ∆P (MW)
Case 1Case 2
1
5
14
189
1
5
9
14
181
18
14
9
5
Figure 3.12: Incremental P -Q Curves of IPFC Lines
Figure 3.13 shows the d-axis and q-axis components of the injected voltage of
the slave VSC. When the slave VSC reference value is high as in Case 2, with the
master VSC simultaneously requiring large active power circulation (|Vd| > 0.6 pu),
the slave VSC voltage insertion will exceed its limit. Based on the power circulation
priority rule in Section 3.4.2.2.ii, the slave VSC Vq cannot keep its reference value
any more, and it will be reduced to ensure the slave VSC voltage satisfies its limit.
B. VSC 2 as the Master and VSC 1 as the Slave
In the second set of dispatch, VSC 2 is set as the master such that its magnitude
of the injected voltage reference is kept constant while its angle varies, as shown in
Figure 3.10(b). The dispatch is computed for two settings:
42
-1
-0.5
0
0.5
1
-1 -0.5 0 0.5 1Slave Vq (pu)
Case1Case2
1
5
9
14
181
9
5
14
18
Figure 3.13: Injected Series Voltage of IPFC Slave VSC
• (Case 3) Master VSC Vmref = 0.5 pu,
• (Case 4) Master VSC Vmref = 1.0 pu.
The slave inverter VSC 1 reference is set at Vqref = 0.1 pu.
-100
-50
0
50
100
-100 -50 0 50Slave Line ∆P (MW)
Case 3Case 4
-100
-50
0
50
100
-150 -100 -50 0 50 100 150Master Line ∆P (MW)
Case 3Case 4
1
18
5
9
14
A1
A2
118
5
9
14
1
2
10
11
Figure 3.14: Incremental P -Q Curves of IPFC Lines
The resulting incremental P -Q curves of the master and slave VSCs are shown
in Figure 3.14. Case 4, which has higher injected voltage magnitude of the master
43
VSC, has a larger line flow dispatch region than Case 3. However, compared to Case
3, in Case 4 the top and bottom of the near-elliptical ∆P -∆Q curves are clipped
because of the limits of the slave VSC. Note that two additional reference points
A1 and A2 in Case 4 are added to the set of 18 values for a clearer illustration of
this limitation. Figure 3.15 shows the d-axis and q-axis components of the injected
voltages of the IPFC. When the master VSC reference Vdref is too high (|Vdref | > 0.6
pu), that is, the master VSC requires larger active power circulation, even though
the slave Vd is set to its limit, it is still unable to support the power circulation.
Based on the power circulation priority rule, the master VSC Vd will be reduced to
allow the slave VSC to provide enough active power circulation.
-1
-0.5
0
0.5
1
-1 -0.5 0 0.5 1Slave Vq (pu)
Case 3Case 4
-1
-0.5
0
0.5
1
-1 -0.5 0 0.5 1Master Vq (pu)
Case 3Case 4
1(10)1(10)
56
(6)5
14
14
1 1
5
5 6
6
10 10
(15)
14
1415
15
15
Figure 3.15: Injected Series Voltage of the IPFC
3.6 Summary and Conclusions
In this chapter, we have presented a novel computation approach required for
dispatching the many control modes associated with multi-functional VSC-based
FACTS controllers. The shunt or series VSCs are separately modeled and then
functionally coupled by the circulating active power between them. This approach
can be adopted in all dispatch computation tools involving converter-based con-
trollers.
44
Rated-capacity operation strategies have also been implemented, such that
maximum dispatchability of VSCs can be studied. This feature may be used as
a tool for both the siting and sizing of converter-based transmission controllers.
The developed dispatch software has been implemented in an Operator Training
Simulator (OTS), which is customized to the CSC installed at NYPA’s Marcy 345
kV Substation.
CHAPTER 4
FACTS CONTROLLER DYNAMIC MODELS AND
SETPOINT CONTROL
A comprehensive set of regulator models of FACTS controllers, which include the
DC link capacitor dynamics and are applicable to various operating modes, are
proposed in this thesis work. In our approach, shunt VSC controllers and series VSC
controllers are modeled as controllable voltage sources with equivalent transformer
reactance. In the control model implementation, the shunt VSC controls and the
series VSC controls are modeled as separate regulators. When a VSC changes its
operating mode, only the input signals of the corresponding regulator need to be
adjusted. With this implementation, we only need to select and combine the proper
functionalities of the shunt VSC, the series VSC and the DC link coupling to form
the specified type of a FACTS controller and to operate it in the desired operating
mode.
In this chapter, we will focus on the formulation of the regulation model for
multi-functional FACTS Controllers. The modeling and setpoint control for the
shunt VSC, the series VSC, and the DC link capacitor are summarized in Sec-
tions 4.1. The nonlinear differential equation formulation for the different operating
modes, the algebraic equations of the network solution, and the numerical simulation
are included in Section 4.2. Application results are given in Section 4.3.
4.1 VSC Dynamic Modeling and Control
4.1.1 VSC Dynamic Model
Figure 4.1 shows the schematic diagrams for a shunt VSC and a series VSC,
where γsh and γse are modulation ratio signals to control the shunt and series con-
verter voltage magnitudes, respectively, and αsh and αse are firing angles of the shunt
VSC and series VSC, respectively. Note that αsh and αse in the dynamic models are
measured with respect to the angle of the from-bus voltage V1, while α1 and α2 in
the loadflow models in Chapter 3 are measured with respect to the swing bus angle.
45
46
+
_
Z1V1V2
~ ~ ~
Vdc
Ssh
C
Idc1
γsh αsh
Z2V3
From-bus
+
_
Z4V2Z3
V1V3 V4~ ~ ~ ~
Vdc
From-bus To-bus
Sse
C
Idc2
γse αse
(a) Shunt VSC (b) Series VSC
Figure 4.1: Voltage-Sourced Converters Showing DC Capacitors
In the time scale of transient stability, in which the VSC switching dynamics
are neglected, the model of a VSC with modulation ratio γ and firing angle α can
be represented as a voltage source
Vm = kVdcεjα (4.1)
where k is a factor which relates the inverter DC-side voltage to its AC-side terminal
voltage. Note that k is dependent on the modulation ratio γ.
The dynamic balanced positive-sequence model of a shunt VSC is shown in
Figure 4.2 (a). The shunt VSC is modeled as a controllable injected voltage source
Vm1 behind an equivalent transformer reactance Xt1, where Vm1 can be expressed as
Vm1 = k1Vdcεj(αsh+θ1) = Vm1ε
j(αsh+θ1) (4.2)
where k1 is the factor between the DC-side voltage Vdc and the AC-side voltage
magnitude Vm1 of the shunt VSC and θ1 is the angle of the from-bus voltage V1.
The injected current Ish and the injected power Ssh from the shunt VSC into the
system are the same as given in (3.1) and (3.2) for the steady-state shunt VSC
model, respectively.
As shown in Figure 4.2 (b), the series VSC is modeled as a controllable injected
47
jXt1
Ish
+_ Vm1
~
Z1 Z2V1V2 V3
~ ~ ~
Ssh,~ ~
From-bus
Z4V2Z3
V1V3 V4jXt2 + _Vm2~
Ise
~ ~ ~ ~From-bus To-bus
Sse,
S2~
~ ~
(a) Shunt VSC (b) Series VSC
Figure 4.2: Voltage-Sourced Converter Models
voltage source Vm2 behind an equivalent transformer reactance Xt2, where Vm2 can
be expressed as
Vm2 = k2Vdcεj(αse+θ1) = Vm2ε
j(αse+θ1) (4.3)
where k2 is the factor between the DC-side voltage Vdc and the AC-side voltage
magnitude Vm2 of the series VSC and θ1 is the angle of the from-bus voltage V1. The
line current Ise, the power injected by the series VSC Sse, and the power injected into
the to-bus (Bus 2) S2 are the same as given in (3.3), (3.4), and (3.5) for the steady-
state series VSC model, respectively. The series injected voltage Vm2 can be split
into two components: Vd is a component in phase with the from-bus voltage which
mainly affects the reactive power of the compensated line and Vq is a component in
quadrature with the from-bus voltage which mainly affect the active power of the
compensated line.
During transient studies, the DC link capacitor of FACTS controllers will ex-
change energy with the system and consequently its voltage will vary. The variation
of the DC capacitor voltage is dependent on its current inflow, which can be modeled
as
CdVdc
dt= Idc (4.4)
where Idc is the current flowing into the DC capacitor C from the VSC. In steady-
state operations when the power transfer is balanced, Idc = 0, and hence, dVdc/dt is
zero.
48
The FACTS dynamic models will be interfaced with the other dynamic com-
ponents in a power system, such as synchronous machines and excitation systems,
through the algebraic network equations. In using injected voltage sources for the
VSCs in the loadflow formulation, this transition to dynamic modes will be seamless,
because Vm1 and Vm2 are operational states in the loadflow models.
4.1.2 VSC Setpoint Controller Models
The same separation of shunt and series control modes for loadflow calculation
can be implemented dynamically also. The following subsections show separately
the Proportional-Integral (PI) regulators for each of the setpoint control modes of
the shunt VSC and the series VSC. Each of the regulators allows for setpoint control
by creating an error signal between the desired setpoint value and the actual value.
4.1.2.1 Shunt VSC Model
The shunt VSC can be operated either in voltage control mode or Var control
mode. The block diagrams for these two operating modes are shown in Figure 4.3
(a) and (b), respectively. The magnitude Vm1 and angle α1 of the inverter voltage
are generated by the control systems.
In the magnitude control of the shunt VSC, the factor k1 between its AC-side
voltage Vm1 and DC-side voltage Vdc is set to a constant. Thus the changes in the
magnitude of the inverter output voltage are achieved by charging or discharging
the DC bus capacitor to a different voltage.
For the angle control of the shunt VSC, an outer voltage regulation loop and
an inner current regulation loop are built to regulate the from-bus voltage V1 in the
voltage control mode, whereas in the Var control mode the shunt reactive current
Ishq is directly controlled to its reference value without the outer voltage regulation
loop.
The outer voltage regulation loop in the voltage control mode, which consists of
an integral controller Kv/s and a feedback droop α, is used to regulate the from-bus
voltage V1 towards its setpoint Vref . This loop produces a reactive current reference
I∗shq for the inner current loop. The shunt reactive current Ishq is controlled to I∗
shq
by the inner current loop, which consists an PI controller Kp + Ki/s and an LP
49
V1
Vref +_
+sKv
sKiKp+
αDroop
I*shq +
Ishq
θ1
-αsh
Vm1
α111+Ts
k1Vdc
_
_
_
(a) Voltage Regulation Mode
+_s
KiKp+Ishqref +
Ishq_
θ1
-αsh
Vm1
α111+Ts
k1Vdc
(b) Var Control Mode
Figure 4.3: Setpoint Control Schemes of a Shunt VSC
filter 1/(1 + Ts). The output of the inner current loop is the minus shunt inverter
voltage angle −αsh. The inverter voltage angle α1 can then be obtained with the
information of the from-bus voltage angle θ1.
In the var control mode, the shunt reactive current setpoint Ishqref is directly
specified in the operator screens. The shunt reactive current Ishq is controlled to
I∗shq by an PI controller Kp + Ki/s and an LP filter 1/(1 + Ts). This current loop
produces the angle information −αsh.
In steady state the angle αsh is zero, which means that the inverter output
voltage is kept essentially in phase with the from-bus voltage. Small transient posi-
tive or negative deviations in αsh cause nonzero active power to go through the DC
capacitor and thus result in an increase or decrease of the DC bus voltage Vdc.
4.1.2.2 Standalone Series VSC Model
The standalone series VSC can be either in the line active power control mode
or the inverter voltage magnitude control mode. The block diagrams for these two
50
modes are shown in Figures 4.4 and 4.5, respectively. The magnitude Vm2 and angle
α2 of the inverter voltage are generated by the control systems.
P
Pref
+sKiKp++
θl∆αse α2
π2
+11+Ts
Vm2k2Vdc
+-1
_
_
(a) Pref ≥ P0
P
Pref
+sKiKp++
_
θl∆αse α2
π2
+11+Ts
Vm2k2Vdc
+1
_
(b) Pref ≤ P0
Figure 4.4: Setpoint Control Schemes of a Standalone or “Slave” SeriesVSC in Line Active Power Regulation Mode
The standalone series VSC is also operated with a constant k2 between its AC-
side voltage Vm2 and DC-side voltage Vdc, and hence the changes in the magnitude
of the inverter output voltage are achieved by charging or discharging the DC bus
capacitor to a different voltage.
An PI controller Kp + Ki/s and an LP filter 1/(1 + Ts) are applied for the
angle control of the standalone series VSC. The input signal for the line active power
control mode is the difference of the line active power setpoint Pref and its measured
value P , while the input signal for the inverter voltage magnitude control mode is
the difference of the inverter voltage magnitude setpoint |Vm2ref | and k2Vdc. In each
operating mode, the output signal from the LP filter is the angle deviation ∆αse.
In steady state, ∆αse is zero, which means that the inverter output voltage is kept
essentially in quadrature with the current of the compensated line. Small transient
positive or negative deviations in the phase of the inverter voltage cause nonzero
51
|Vm2ref|
+sKiKp++
θl∆αse α2
π2
+11+Ts
Vm2k2Vdc
+-1
k2Vdc
_
_
(a) Vm2ref ≤ 0
|Vm2ref|
+sKiKp++
θl∆αse α2
π2
+11+Ts
Vm2k2Vdc
+1
k2Vdc
_
_
(b) Vm2ref ≥ 0
Figure 4.5: Setpoint Control Schemes of a Standalone or “Slave” SeriesVSC in Fixed Injected Voltage Mode
active power to go through the DC capacitor and thus result an increase or decrease
of the DC bus voltage.
In the line active power control mode, when the line active power setpoint Pref
is larger than the original line active power without compensation P0, the inverter
voltage angle α2 is (Figure 4.4 (a))
α2 = θ� − π
2+ ∆αse (4.5)
such that in steady state the inverter voltage is 90 degree lagging the line current
vector. When Pref ≤ P0, the inverter voltage angle α2 is (Figure 4.4 (b))
α2 = θ� +π
2− ∆αse (4.6)
such that in steady state the inverter voltage is 90 degree leading the line current
vector.
In the inverter voltage magnitude control mode, a polarity is added to the
52
inverter voltage reference Vm2ref to indicate whether leading or lagging voltage in-
jection is required. When Vm2ref ≤ 0, the inverter voltage angle α2 is (Figure 4.5
(a))
α2 = θ� − π
2+ ∆αse (4.7)
Thus in steady state the inverter voltage is 90 degree lagging the line current vector,
which means that it will increase the line active power. When Vm2ref ≥ 0, the inverter
voltage angle α2 is (Figure 4.5 (b))
α2 = θ� +π
2− ∆αse (4.8)
Thus in steady state the inverter voltage is 90 degree leading the line current vector,
which means that it will decrease the line active power.
4.1.2.3 Coupled Series VSC Model
The UPFC shunt VSC is operated in the same way as a STATCOM. For the
UPFC series VSC control, both the DC-to-AC ratio of the inverter and the phase
angle of the inverter output voltage are controlled.
The coupled series VSC can be either in the inverter voltage Vd,Vq control
mode or the line power P ,Q control mode. The block diagrams for both modes are
shown in Figure 4.6 (a) and (b), respectively. The magnitude Vm2 and angle α2 of
the inverter voltage are generated by the control systems.
Because the q-axis output voltage of the series VSC Vq has a strong impact on
the line active power flow P while the d-axis output voltage of the series VSC Vd
has a significant effect on the line reactive power flow Q. Therefore, in the line P ,Q
control mode, line active power P regulation and reactive power Q regulation are
implemented by independently controlling the q-axis and d-axis output voltage of
the series VSC Vq and Vd by using the PI controllers and LP filters as shown in 4.6
(a). Then the magnitude and angle of inverter voltage Vm2 and α2 can be obtained
as
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq
Vd)
(4.9)
53
+
sKiKp+
Pref +
P
θ1
αse α2
11+Ts
+sKiKp+
Qref +
Q
11+Ts
Magnitudeand AngleCalculator
Vm2Vq
Vd
_
_
(a) Line Power Regulation Mode
+θ1
αse α2
+
Magnitudeand AngleCalculator
Vm2Vdref
Vqref
(b) Fixed Injected Voltage Mode
Figure 4.6: Setpoint Control Schemes of a Coupled Series VSC
where θ1 is the angle of the from-bus voltage V1.
In the inverter voltage Vd,Vq control mode, the magnitude and angle of inverter
voltage Vm2 and α2 are instantaneously calculated from the setpoints Vdref and Vqref
as
Vm2 =√
V 2dref + V 2
qref
α2 = θ1 + tan−1(Vqref
Vdref)
(4.10)
4.1.2.4 The IPFC Model
An IPFC can be implemented by having a combination of the standalone and
coupled series regulators discussed above. However we make an exception for the
IPFC model here to include certain special control features associated with the real
hardware. In this IPFC control, both the DC-to-AC ratio of the inverter and the
phase angle of the inverter output voltage are controlled. The DC bus voltage is
held at an essentially constant value by the control action, while the inverter output
voltages can take on any values between zero and the maximum.
The IPFC VSCs can be either in the inverter voltage control mode or the line
power control mode. The block diagrams for these two operating modes are shown
54
in Figure 4.7 and 4.8, respectively. One VSC of an IPFC is operated as the Master
VSC, and the other is operated as the Slave VSC. The magnitude Vm2 m and angle
α2 m of the Master inverter voltage and the magnitude Vm2 s and angle α2 s of the
Slave inverter voltage are generated by the control systems.
VdcVdcref +
++
sKiKp+
KαDroop
∆Vd +
V*d
+
θ1
αse
Vm2_m
α2_m
11+Ts Magnitude
and AngleCalculator
V*q
Vq
Vd
Q
Qref +_
sKiKp+ 1
1+Ts
PPref +
sKiKp+ 1
1+Ts
_
_
_
(a) The Master VSCVdc
Vdcref +_
++
sKiKp+
∆Vd
αse
Vm2_s
α2_s
11+Ts Magnitude
and AngleCalculator
V*q
Vq
Vd
PPref +
sKiKp+ 1
1+Ts
_
(b) The Slave VSC
Figure 4.7: Setpoint Control Schemes of an IPFC in the Line Power Reg-ulation Mode
In these two operating modes, a DC bus voltage regulation loop, which consists
of an PI controller Kp + Ki/s and an LP filter 1/(1 + Ts), is applied for each VSC
of the IPFC. The control difference between the DC bus voltage regulation loops of
the Master and Slave VSCs is that there is a nonzero feedback droop for the Slave
VSC, while there is no such a feedback loop for the Master VSC. Thus the DC
bus voltage is more strictly controlled by the Slave VSC. The output signal of each
DC bus voltage regulator, denoted as ∆Vd, are the error signal to form the d-axis
inverter voltage Vd of the corresponding VSC.
55
VdcVdcref +
_
++
_ sKiKp+
KαDroop
∆Vd +
Vdref
+
θ1
αse
Vm2_m
α2_m
11+Ts Magnitude
and AngleCalculatorVqref
Vd
(a) The Master VSC
Vdc
Vdcref +
_
+
sKiKp+
∆Vd +
Vdref
+
θ1
αse
Vm2_s
α2_s
11+Ts Magnitude
and AngleCalculatorVqref
Vq
Vd
+
(b) The Slave VSC
Figure 4.8: Setpoint Control Schemes of an IPFC in the Fixed InjectedVoltage Mode
In the line power control mode, the Master line active and reactive power
P and Q regulations are implemented by independently controlling the q-axis and
d-axis voltages of the Master VSC V ∗q and V ∗
d by using the PI controllers and LP
filters as shown in 4.7 (a). The Master inverter voltage can then be obtained as
Vd = V ∗d + ∆Vd
Vq = V ∗q
Vm2 m =√
V 2d + V 2
q
αm2 m = θ1 + tan−1(Vq
Vd)
(4.11)
For the Slave VSC, only its line active power P is controlled by the PI controller
and LP filter as shown in 4.7 (b). The regulator output is the q-axis voltage of
the Slave VSC v∗q . The d-axis component v∗
d is not specified in order to meet the
power circulation constraint of the IPFC. Moreover, Vq of the Slave inverter voltage
is limited as a function of Vd to prioritize the transfer of power circulation. The
56
Slave inverter voltage can then be obtained as
Vd = ∆Vd
Vq =
V ∗q if Vm2 s ≤ Vm max
sign(V ∗q ) ·
√V 2
mmax − V 2d if Vm2 s ≥ Vm max
Vm2 s =√
V 2d + V 2
q
αm2 s = θ1 + tan−1(Vq
Vd)
(4.12)
where Vm max is the maximum limit of the Slave inverter voltage.
In the inverter voltage control mode, d-axis and q-axis inverter voltage ref-
erences Vdref and Vdref are specified directly in the operator screens. The Master
inverter voltage can be obtained as
Vd = Vdref + ∆Vd
Vq = Vqref
Vm2 m =√
V 2d + V 2
q
αm2 m = θ1 + tan−1(Vq
Vd)
(4.13)
And the Slave inverter voltage can be obtained as
Vd = Vdref + ∆Vd
Vq =
Vqref if Vm2 s ≤ Vm max
sign(Vqref) ·√
V 2mmax − V 2
d if Vm2 s ≥ Vm max
Vm2 s =√
V 2d + V 2
q
αm2 s = θ1 + tan−1(Vq
Vd)
(4.14)
4.1.3 DC Link Capacitor Dynamics
The AC instantaneous active power injection into the power system by a shunt
VSC is given by
Psh =V1Vm1 sin(αsh)
Xt1
(4.15)
and by a series VSC is given by
Pse = −V1Vm2 sin(αse) − V2Vm2 sin(αse + θ1 − θ2)
Xt2
(4.16)
57
Thus the AC instantaneous active power flowing into a single shunt VSC, such as a
STATCOM, is
Pac = −Psh (4.17)
and into a single series VSC, such as an SSSC, is
Pac = −Pse (4.18)
If the DC bus of a FACTS controller is coupled with M shunt VSCs and N series
VSCs, the AC instantaneous active powers flowing into the VSCs from the system
is given as
Pac = −(M∑i=1
Pshi+
N∑i=1
Psei) (4.19)
Assuming that the VSC model is ideal, the total AC instantaneous active
powers on the AC-side is equal to the DC-side active power, that is
Pac = VdcIdc (4.20)
From (4.4) and (4.20), we have
dVdc
dt=
1
CVdc
Pac (4.21)
Equation (4.21) is, in general, not per-unitized.
The block diagram of the DC link dynamics is shown in Figure 4.9.
1s
Pac VdcCVdc
1
Figure 4.9: DC Link Dynamics
58
4.2 Numerical Computation
The power system dynamic models can be written as a set of differential equa-
tions (4.22) and a set of algebraic equations (4.23) in vector form as
x = f(x, V ) (4.22)
I(x, V ) = Y V (4.23)
where I and V are complex injection currents and voltage vectors of dimension n,
respectively, and x is a state variable vector of dimension m. The number n is equal
to the number of nodes in the system and the number m depends on the number
and the type of the dynamic models used for the actual equipment. For example,
for a generator modeled with subtransient reactance, the state variables are its rotor
angle δ, speed ω, and direct- and quadrature-axis fluxes E′q, ψd, E
′d, and ψq [56].
In the explicit integration approach, (4.22) is used to update the state variables
x and then the algebraic variables V in (4.23) can be solved iteratively by a Newton
method given by (4.62), at every integration step.
4.2.1 Nonlinear Dynamic Models
The FACTS controls are represented as nonlinear differential equations for
transient stability studies.
The block realization of a PI regulator in series with an LP filter is shown in
Figure 4.10. The time-domain state equation is derived as
+ 1sTj
1_
ej zj.
zj
+1s
xj.
xjKij
Kpj+
Figure 4.10: Block Realization of the PI regulator and LP filter
59
xj = Kijej
zj = (Kpjej + xj − zj)/Tj
(4.24)
where xj and zj are the state variables for the jth regulators.
We introduce three additional state variables I∗shq, x1, and z1 for a shunt VSC,
two state variable x2 and z2 for a standalone VSC, four state variables x3, z3, x4,
and z4 for a coupled series VSC, and ten state variables x5, z5, x6, z6, x7, z7, xM ,
zM , xS, and zS for an IPFC into the state variable vector x in (4.22). Also the DC
link dynamic state variable xdc = Vdc will be incorporated.
In this section we provide the equations for formulating the different shunt
and series VSC operating modes.
4.2.1.1 Shunt Operating Modes
(Sh1) Voltage control mode with droop α: the differential equations of state variables
I∗shq, x1, and z1 can be expressed as
I∗shq = Kv(Vref − V1 − αI∗
shq)
x1 = Ki1(I∗shq − Ishq)
z1 = [Kp1(I∗shq − Ishq) + x1 − z1]/T1
(4.25)
where Kv is the gain of the voltage regulator, Kp1 and Ki1 are the proportional
and integral gain coefficients of the PI controller, and T1 is the time constant
of the LP filter (Figure 4.3 (a)). The shunt injected voltage source can be
obtained as
Vm1 = k1Vdc
α1 = θ1 − z1
(4.26)
where k1 is the constant ratio between Vm1 and Vdc and θ1 is the from-bus
voltage angle. Note that α1 is with regard to to the system swing bus angle.
(Sh2) Control the Var output of the shunt VSC to a desired value Ishqref : the dif-
ferential equations of the state variables I∗shq, x1, and z1 can be expressed
60
as
I∗shq = 0
x1 = Ki1(Ishqref − Ishq)
z1 = [Kp1(Ishqref − Ishq) + x1 − z1]/T1
(4.27)
where Kp1 and Ki1 are the proportional and integral gain coefficients of the PI
controllers and T1 is the time constant of the LP filter (Figure 4.3 (b)). The
shunt injected voltage source can be obtained as
Vm1 = k1Vdc
α1 = θ1 − z1
(4.28)
where k1 is the constant ratio between Vm1 and Vdc and θ1 is the from-bus
voltage angle. Note that α1 is with regard to to the system swing bus angle.
4.2.1.2 Standalone Series Dispatch Modes
(Se1) Control the line active power flow P to a desired value Pref : the differential
equations of state variables x2 and z2 can be expressed as
x2 = Ki2(Pref − P )
z2 = [Kp2(Pref − P ) + x2 − z2]/T2
(4.29)
where Kp2 and Ki2 are the proportional and integral gain coefficients of the
PI controller and T2 is the time constant of the LP filter (Figure 4.4). The
series injected voltage source can be obtained as
Vm2 = k2Vdc
α2 =
θl − π/2 + z2 if Pref ≥ P0
θl + π/2 − z2 if Pref ≤ P0
(4.30)
where k2 is the constant ratio between Vm2 and Vdc and θ� is the line current
angle.
(Se2) Fix the injected voltage magnitude, in either the quadrature leading or lag-
ging direction with respect to the transmission line current: the differential
61
equations of state variables z2 and z2 can be expressed as
x2 = Ki2(Vm2ref − Vm2)
z2 = [Kp2(Vm2ref − Vm2) + x2 − z2]/T2
(4.31)
where Kp2 and Ki2 are the proportional and integral gain coefficients of the
PI controller and T2 is the time constant of the LP filter (Figure 4.5). The
series injected voltage source can be obtained as
Vm2 = k2Vdc
α2 =
θl − π/2 + z2 if Vm2ref ≤ 0
θl + π/2 − z2 if Vm2ref ≥ 0
(4.32)
where k2 is the constant ratio between Vm2 and Vdc and θ� is the line current
angle.
4.2.1.3 Coupled Series Dispatch Modes
(SeC1) Control the line active and reactive power flow P and Q to their desired values
Pref and Qref , respectively: the differential equations of state variables x3, z3,
x4, and z4 can be expressed as
x3 = Ki3(Pref − P )
z3 = [Kp3(Pref − P ) + x3 − z3]/T3
x4 = Ki4(Qref − Q)
z4 = [Kp4(Qref − Q) + x4 − z4]/T4
(4.33)
where Kp3, Ki3, Kp4, and Ki4 are the proportional and integral gain coefficients
of the PI controllers and T3 and T4 are the time constants of the LP filters
(Figure 4.6 (a)). The series injected voltage source can be obtained as
Vq = z3
Vd = z4
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.34)
62
(SeC2) Fix the d-axis and q-axis of the injected voltage at Vdref and Vqref with respect
to the from-bus voltage vector V1: the differential equations of state variables
x3, z3, x4, and z4 can be expressed as
x3 = 0
z3 = 0
x4 = 0
z4 = 0
(4.35)
Note that (4.35) is listed here only for completeness. The series injected voltage
source can be obtained as
Vq = Vqref
Vd = Vdref
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.36)
4.2.1.4 IPFC Operating Modes
A. The Master VSC
(SeM1) Control the Master line active and reactive power flow P and Q to their desired
values Pref and Qref , respectively: the differential equations of state variables
x5, z5, x6, z6, xM , and zM can be expressed as
x5 = Ki5(Pref − P )
z5 = [Kp5(Pref − P ) + x5 − z5]/T5
x6 = Ki6(Qref − Q)
z6 = [Kp6(Qref − Q) + x6 − z6]/T6
xM = KiM(Vdcref − Vdc − KαzM)
zM = [KpM(Vdcref − Vdc − KαzM) + xM − zM ]/TM
(4.37)
where Kp5, Ki5, Kp6, Ki6, KpM, and KiM are the proportional and integral gain
coefficients of the PI controllers and T5, T6, and TM are the time constants
of the LP filters (Figure 4.7 (a)). The Master injected voltage source can be
63
obtained as
∆Vd = zM
Vq = z5
Vd = z6 + ∆Vd
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.38)
(SeM2) Fix the d-axis and q-axis of the injected voltage at Vdref and Vqref with respect
to the from-bus voltage vector V1: the differential equations of state variables
x5, z5, x6, z6, xM , and zM can be expressed as
x5 = 0
z5 = 0
x6 = 0
z6 = 0
xM = KiM(Vdcref − Vdc − KαzM)
zM = [KpM(Vdcref − Vdc − KαzM) + xM − zM ]/TM
(4.39)
where KpM and KiM are the proportional and integral gain coefficients of the
PI controllers and TM is the time constant of the LP filter (Figure 4.8 (a)).
The Master injected voltage source can be obtained as
∆Vd = zM
Vq = Vqref
Vd = Vdref + ∆Vd
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.40)
B. The Slave VSC
(SeS1) Control the Slave line active power flow P to its desired value Pref : the differ-
64
ential equations of state variables x7, z7, xS, and zS can be expressed as
x7 = Ki7(Pref − P )
z7 = [Kp5(Pref − P ) + x7 − z7]/T7
xS = KiS(Vdcref − Vdc)
zS = [KpS(Vdcref − Vdc + xS − zS]/TS
(4.41)
where Kp7, Ki7, KpS, and KiS are the proportional and integral gain coefficients
of the PI controllers and T7 and TS are the time constants of the LP filters
(Figure 4.7 (b)). The Slave injected voltage source can be obtained as
∆Vd = zS
Vq = z7
Vd = ∆Vd
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.42)
(SeS2) Fix the q-axis of the injected voltage at and Vqref with respect to the from-bus
voltage vector V1: the differential equations of state variables x7, z7, xS, and
zS can be expressed as
x7 = 0
z7 = 0
xS = KiS(Vdcref − Vdc)
zS = [KpS(Vdcref − Vdc + xS − zS]/TS
(4.43)
where KpS and KiS are the proportional and integral gain coefficients of the
PI controllers and TS is the time constant of the LP filter (Figure 4.8 (b)).
65
The Slave injected voltage source can be obtained as
∆Vd = zS
Vq = Vqref
Vd = Vdref + ∆Vd
Vm2 =√
V 2d + V 2
q
α2 = θ1 + tan−1(Vq/Vd)
(4.44)
4.2.2 Network Equations
The bus admittance matrix equation of a power system without FACTS con-
trollers and non-conforming loads can be written as follows
Ygg Ygl
Ylg Yll
Vg
Vl
=
Ig
0
(4.45)
where Vg is the generator bus voltage vector and Vl is the bus voltage vector for all
the load buses.
If a shunt VSC is connected to Bus f of the power system, the bus admittance
equation is expanded to
Ygg Ygf Ygl 0
Yfg Yff + 1jXt1
Yfl − 1jXt1
Ylg Ylf Yll 0
Vg
Vf
Vl
Vm1
=
Ig
0
0
(4.46)
Rearranging (4.46) by moving Vm1 to the right hand side, we obtain
Ygg Ygf Ygl
Yfg Yff + 1jXt1
Yfl
Ylg Ylf Yll
Vg
Vf
Vl
=
Ig
Vm1/jXt1
0
(4.47)
If a series VSC is inserted into the line with from-bus f and to-bus t of the
66
power system, the bus admittance equation is expressed as follows
Ygg Ygf Ygt Ygl 0
Yfg Yff + 1jXt2
Yft − 1jXt2
Yfl − 1jXt2
Ytg Ytf − 1jXt2
Ytt + 1jXt2
Ytl1
jXt2
Ylg Ylf Ylt Yll 0
Vg
Vf
Vt
Vl
Vm2
=
Ig
0
0
0
(4.48)
Rearrange (4.48) by moving Vm2 to the right hand side, we obtain
Ygg Ygf Ygt Ygl
Yfg Yff + 1jXt2
Yft − 1jXt2
Yfl
Ytg Ytf − 1jXt2
Ytt + 1jXt2
Ytl
Ylg Ylf Ylt Yll
Vg
Vf
Vt
Vl
=
Ig
Vm2/jXt2
−Vm2/jXt2
0
(4.49)
If a VSC has the same from-bus or to-bus with some other shunt or series
VSCs, the effect of all these VSCs on the bus admittance matrix equation can be
added together.
Suppose the total number of distinct from-buses of FACTS controllers is L,
and the total number of distinct to-buses of FACTS Controllers is R in a specific
power system and let the from-bus fi have Nf i shunt VSCs and Mf i series VSCs
connected to it, for i = 1, . . . , L, and the to-bus tk have Mtk series VSCs connected
to it, for k = 1, . . . , R. The bus admittance matrix equation can be expressed as
Ygg YgF YgF Ygl
YFg YFF YFT YFl
YTg YTF YTT YTl
Ylg YlF YlT Yll
Vg
VF
VT
Vl
=
Ig
IF
IT
0
(4.50)
67
where
YFF =
Y′f1f1
. . . 0
Y′fifi
0. . .
Y′fLfL
L×L
(4.51)
YTT =
Y′t1t1
. . . 0
Y′tktk
0. . .
Y′tRtR
R×R
(4.52)
YFT = Y TFT =
Y′f1t1
· · · Y′f1tk
· · · Y′f1tR
.... . .
......
Y′fit1
· · · Y′fitk
· · · Y′fitR
......
. . ....
Y′fLt1
· · · Y′fLtk
· · · Y′fLtR
L×R
(4.53)
Y′fifi
= Yfifi+
Nf i∑i=1
1
jXt1i
+Mf i∑i=1
1
jXt2i
, i = 1, . . . , L (4.54)
Y′tktk
= Ytktk +Mtk∑k=1
1
jXt2k
, k = 1, . . . , R (4.55)
Y′fitk
=
Yfitk , no series VSCs in Line fitk
Yfitk −M�s∑s=1
1
jXt2s
, M�s series VSCs in Line fitk(4.56)
i = 1, . . . , L; k = 1, . . . , R
Ifi=
Nf i∑i=1
Vm1i
jXt1i
+Mf i∑i=1
Vm2i
jXt2i
=Nf i∑i=1
Vm1iej(α1i+θ1i)
jXt1i
+Mf i∑i=1
Vm2iej(α2i+θ1i)
jXt2i
68
i = 1, . . . , L (4.57)
Itk = −Ntk∑i=1
Vm2i
jXt2i
= −Ntk∑i=1
Vm2iej(α2i+θ1i)
jXt2i
k = 1, . . . , R (4.58)
where Yfifi, Ytktk , and Yfitk are the nodal admittances and mutual admittances at the
bus fi and bus tk of the system without considering FACTS Controllers, respectively.
Next, we reduce the bus admittance matrix to the generator internal buses
and the FACTS controllers’ from-buses and to-buses. The corresponding reduced
bus admittance matrix equation takes the form
YGG YGF YGT
YFG YFF YFT
YTG YTF YTT
E′′
Vf
Vt
=
Ig
IF
IT
(4.59)
where E′′
is the generator internal voltage vector behind the transient or subtransient
reactance.
It is clear that in (4.57) and (4.58), Vm1, α1, Vm2, and α2 are known from
the control outputs Vm1, α1, Vd, and Vq in Section 4-1. The only unknown is the
from-bus angle θ1, which can be obtained from the network solution. An iterative
process can be applied to obtain the solutions of Vf , θ1, and Vt.
4.2.3 Newton’s Method
Rearranging the second and third equations of (4.59), we have
YFF YFT
YTF YTT
VF
VT
=
IF − YFGE
′′
IT − YTGE′′
(4.60)
Define the functions ∆F1 and ∆F2 as
∆F1
∆F2
=
YFFVF + YFTVT + YFGE
′′ − IF
YTFVF + YTTVT + YTGE′′ − IT
(4.61)
69
Use the Newton’s method to solve for the variables VFre , VFim, VTre , and VTim
itera-
tively as
VFre
new = VFre
old + ∆VFre
VFim
new = VFim
old + ∆VFim
VTre
new = VTre
old + ∆VTre
VTim
new = VTim
old + ∆VTim
(4.62)
where the updates are computed as
∆VFre
∆VFim
∆VTre
∆VTim
=
∂∆F1re
∂VFre
∂∆F1re
∂VFim
∂∆F1re
∂VTre
∂∆F1re
∂VTim
∂∆F1im
∂VFre
∂∆F1im
∂VFim
∂∆F1im
∂VTre
∂∆F1im
∂VTim
∂∆F2re
∂VFre
∂∆F2re
∂VFim
∂∆F2re
∂VTre
∂∆F2re
∂VTim
∂∆F2im
∂VFre
∂∆F2im
∂VFim
∂∆F2im
∂VTre
∂∆F2im
∂VTim
−1
∆F1re
∆F1im
∆F2re
∆F2im
(4.63)
Then we get VF = VFre + jVFimand VT = VTre + jVTim
. Substituting VF and
VT into the first equation of (4.59) gives the current injections Ig into the generator
internal buses
Ig = YGGE′′
+ YGFVF + YGTVT (4.64)
4.2.4 Integration Method
The predictor-corrector scheme [56] is used to solve the problem of (4.22). It
consists of two main steps, a predictor step:
xk+1 = xk + f(xk, tk)∆t (4.65)
and a corrector step:
xk+1 = xk +[f(xk, tk) + f(xk+1, tk+1)]
2∆t (4.66)
This multi-step scheme will result in a second-order accuracy of the solution, that
is, the local error of the method, which is the difference between the approximate
solution xk obtained by using this method and the exact solution x∗k of the differential
equation, is O((∆t)3) as ∆t → 0.
70
4.3 Simulation Results
The regulator models of the VSC-based FACTS controllers are simulated in a
22-bus test system as shown in Figure 4.11, which has 6 equivalent generators and
3 equivalent loads. The loads of the test system are concentrated in the southeast
part of the system, while the generations are mainly in the northwest area. The
arrows indicate the direction of the active power flows. A 100 MVA shunt VSC can
be connected to Bus 4 by closing its switch and two 100 MVA series VSCs can be
inserted into Line 4-11 and Line 4-12, which are the two major paths between the
generations and the loads, by opening their bypass switches, respectively. Note that
the system base is 100 MVA.
4
2 3
7
9
6
8
10
1 5
11
1213
14
15
17
19
20
21
1618
VSC 2
Load 1Load 2
VSC 1
22
G 1
G 2
G 3
G 4
G 5
G 6
VSC 3
Figure 4.11: 22-Bus Test System
71
In the dynamic simulations, each generator are modeled with a subtransient
reactance, controlled by a simple voltage regulator. The loads are modeled as con-
stant impedances.
4.3.1 FACTS Controller Dynamic Simulations
By manipulating the switches, four configurations of FACTS controllers, named
a STATCOM, an SSSC, a UPFC, and an IPFC, can be simulated to study their
dynamic effects in the 22-bus test system. The simulation results for one operating
mode in each configuration are displayed in the following subsections.
4.3.1.1 STATCOM Dynamics
The STATCOM configuration is formed by connecting the shunt VSC 1 to
Bus 4 and leaving the bypass switches of the series VSC 2 and VSC 3 closed.
Table 4.1: Operating Conditions of the STATCOM in Var Control Mode
Control Original DisturbanceGains Setpoint Event
Kp=0.01 At t=0.2 s, the reactive current injectionKi=0.1 Ishqset = −1.0 pu reference has a step change from full
T=0.02 s inductive (−1 pu) to full capacitive (1 pu).
Figure 4.12 shows the simulation results of the STATCOM in var control mode
under the operating conditions in Table 4.1. A positive value of reactive power in-
jection reference Ishqset implies capacitive shunt reactive power compensation, while
a negative value implies inductive compensation.
When the reactive current reference changes from inductive to capacitive, the
shunt reactive power injected into the from bus by the VSC will respond to the
change, and thus will cause the from-bus voltage increase. Both the DC capacitor
voltage and the inverter voltage increase but the ratio between them is kept constant.
As shown in Figure 4.12, when the shunt reactive power compensation changes
from full inductive to full capacitive, the DC capacitor voltage increases from about
−20% below to 20% above nominal.
Note that the fast oscillations in the system voltage are due to the FACTS
controller and generator automatic voltage controllers, and the slower oscillations
72
are the effect of the superposition of the impact of all machine swing modes. This
also explains the voltage oscillations for all the following cases.
4.3.1.2 SSSC Dynamics
The SSSC configuration is formed by opening the bypass switch of the series
VSC 2 to insert the series VSC 2 into Line 4-11, while leaving the switch of the
shunt VSC 1 open and the bypass switch of the series VSC 3 closed.
Table 4.2: Operating Conditions of the SSSC in Vm Control Mode
Control Original DisturbanceGains Setpoint EventKp=20 At t=0.01 s, Vmref has a rampKi=200 Vmref = −0.05 pu increase from −0.05 pu to 0.05T=0.02 pu in 10 s.
Figure 4.13 shows the simulation results of the SSSC in inverter voltage magni-
tude control mode under the operating conditions in Table 4.2. The polarity of Vmref
indicates that the insertion of the SSSC is either inductive when it is positive or is
capacitive when it is negative. We observe that the DC capacitor voltage decreases
from over 10 kV to zero and then goes back up, while the from-bus voltage keeps
decreasing from 1.0122 pu to 1.0058 pu. The line active power decreases about 160
MW with the SSSC control from 0.05 pu capacitive to 0.05 pu inductive.
4.3.1.3 UPFC Dynamics
The UPFC configuration is formed by connecting the shunt VSC 1 to Bus 4
and inserting the series VSC 2 into Line 4-11, while leaving the bypass switch of the
series VSC 3 closed.
Table 4.3: Operating Conditions of the UPFC in V ,Vd,Vq Control Mode
Shunt Series Original DisturbancesGains Gains Setpoint Event 1 Event 2 Event 3
Kv=500 Kp=0.01 Vset=1.025 pu At t=1 s, At t=7 s, At t=13 s,Kp=0.01 Ki = 0.1 α=0.03 shunt Vset has series Vdref has series Vqref hasKi = 0.1 T=0.02 Vdref=0.01 pu a step increase a step increase a step decreaseT=0.02 Vqref=−0.02 pu of 0.01 pu. of 0.02 pu. of 0.02 pu.
73
Figure 4.14 shows the simulation results of the UPFC in V ,Vd,Vq control mode
under the operating conditions in Table 4.3. We observe that the from-bus voltage,
the series VSC voltage Vd, and the series VSC voltage Vq are independently con-
trolled to their reference values. The change of Vq mainly affects line active power,
while the change of Vd mainly affects line reactive power.
4.3.1.4 IPFC Dynamics
The IPFC configuration is formed by inserting the series VSC 2 into Line 4-11
as the Master VSC and inserting the series VSC 3 into Line 4-12 as the Slave VSC,
while leaving the switch of the shunt VSC 1 open.
Table 4.4: Operating Conditions of the IPFC in Inverter Voltage ControlMode
Kα=100 Kp=.1 Master At t=1 s, At t=7 s, At t=13 s,Kp=.1 Ki = 1 Vdref=0.02 pu Master Vqref has Slave Vqref has Master Vdref hasKi = 1 T=0.02 Vqref=0.0 pu; a step decrease a step decrease a step decreaseT=0.02 Slave of 0.01 pu. of 0.01 pu. of 0.02 pu.
Vqref=−0.03 pu
Figure 4.15 and 4.16 show the simulation results of the IPFC in inverter voltage
control mode under the operating conditions in Table 4.4. We observe that the
Master VSC Vd, the Master VSC Vq, and the Slave VSC Vq are independently
controlled to their reference values. Note that the DC capacitor voltage is also
controlled to its reference value. The step change (-0.01 pu) of the Master line Vdref
causes a 0.009 pu (3 kV in nominal) increase of the to-bus voltage of the Master
line and the same amount of decrease of the to-bus voltage of the Slave line at the
same time.
4.3.2 Transient Power Transfer Capability Analysis Example
In order to evaluate maximum power transfer capability of the critical paths
in the 22-bus system, we stress the system by gradually increasing the active powers
of Load L2 on Bus 17 and Generators G1, G2, and G3. The original active power of
Load L2 is 2500 MW. At time t=0.1 s, a three-phase line-to-ground fault is applied
74
on the Bus 3 side of Line 3-13, which is a line paralleled with Line 4-11. Its near end
is cleared at t=0.15 s and remote end is cleared at t=0.17 s. The maximum load
on Bus 17 that the system can stand during the fault and the corresponding power
transfers on Line 4-11 and Line 4-12 are displayed in Table 4.5 for seven different
system configurations. The setpoints for these configurations are simply specified
on their rated capacity.
Table 4.5: Comparison of Transient Power Transfer Capability Analysiswithout and with Various FACTS Controllers
Max Load Line PowerConfiguration Setpoints on Bus 17 Transfer (MW)
(MW) Line 4-11 Line 4-121. No FACTS - 3235 1390 904
2. STATCOM 100 MVA Ishqref = 1.0 pu 3268 1403 912Var Control
3. STATCOM 200 MVA Ishqref = 2.0 pu 3300 1415 920Var Control
magnitude response to a 0.1 pu step change of Master line active power reference at
time t = 0.1 seconds. The five curves represent the cases without damping control
and with damping controllers designed by using the four candidate signals. The
details of the four designed damping controllers are given in Table 6.4. We observe
that the case using measured signal Im4−11 reduced the damping effect in the first 3
circles of oscillation. So this signal is not recommended. Compared the other three
cases with damping controllers, the cases using V4 achieve better damping effect on
the bus voltage. As a result, the two candidates V4, R3 and V4, R5 are selected for
final consideration.
Table 6.4: Designed Damping Controllers for the IPFC
Damping Controller ExpressionV4,R3 u = −300 · 0.1s
1+0.1s· 1+0.341s
1+0.0852s· 1
1+0.1s, −0.1 ≤ u ≤ 0.1
V4,R5 u = −200 · 0.1s1+0.1s
· 1+0.341s1+0.0852s
· 11+0.1s
, −0.1 ≤ u ≤ 0.1
P4−11,R3 u = 40 · 0.1s1+0.1s
· 1+0.341s1+0.0852s
· 11+0.1s
, −0.1 ≤ u ≤ 0.1
Im4−11,R5 u = 3 · 0.1s1+0.1s
· 11+0.1s
, −0.1 ≤ u ≤ 0.1
Figures 6.20 and 6.21 show the line flows and DC capacitor voltage of the
two cases using V4, compared with the case without damping control. The case
V4,R3 damps the inter-area mode by injecting a damping signal to the Master line
P regulator, which results in a 6.1 MW oscillation of the Master line P in the first 2
seconds. The case V4,R5 damps the inter-area mode by injecting a damping signal to
the Slave line P regulator, which results in a 4.4 MW oscillation of the Slave line P in
the first 2 seconds. Considering the operation of an IPFC, the main function of the
Master VSC is to regulate the Master line flow, while the more important function
of the Slave VSC is not to regulate the Slave line flow but to provide real power
circulation to the Master VSC. Thus a smooth Master line active power response is
117
more preferable than a smooth Slave one. As a result, V4,R5 is recommended and
considered as the best damping signal in this example.
Figure 6.19: Bus 4 Voltage without and with Damping Controllers
0 1 2 3 4 51.1995
1.2
1.2005
1.201
1.2015
1.202
1.2025x 10
4
time in seconds
DC
vol
tage
vol
ts
IPFC capacitor voltage Vdc
no dmpdmp:V
4,R
3
dmp:V4,R
5
Figure 6.20: DC Capacitor Voltage without and with Damping Con-trollers
6.7 Summary and Conclusions
In this chapter, two indices are derived from the effective control actions based
on the multi-machine modal decomposition technique and are used in damping input
118
signal selection. The damping controller design processes for the the STATCOM,
SSSC, UPFC, and IPFC are discussed. The designed damping controllers show
substantial improvement of the damping effect on the system inter-area mode.
However, we notice that the damping controllers built on the regulators of
FACTS controllers will cause larger oscillations in the inverter variables. Due to
high injection of the damping signal at the moment of faults or oscillations, a large
disturbance may cause the damping controllers ineffective or even cause severe extra
system oscillations.
The damping controllers built on the basis of the regulator control of FACTS
controllers are a trade-off to the system. And the damping controllers need to be
designed carefully to not cause unexpected problems.
119
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 57.5
7.52
7.54
7.56
7.58
7.6
7.62
time in seconds
pow
er fl
ow p
er u
nit
master line active power P4−11
no dmpdmp:V
4,R
3
dmp:V4,R
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
6.09
6.1
6.11
6.12
6.13
time in seconds
pow
er fl
ow p
er u
nit
slave line active power P4−12
no dmpdmp:V
4,R
3
dmp:V4,R
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5−0.56
−0.555
−0.55
−0.545
time in seconds
pow
er fl
ow p
er u
nit
master line reactive power Q4−11
no dmpdmp:V
4,R
3
dmp:V4,R
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50.495
0.5
0.505
0.51
0.515
0.52
time in seconds
pow
er fl
ow p
er u
nit
slave line reactive power Q4−12
no dmpdmp:V
4,R
3
dmp:V4,R
5
Figure 6.21: IPFC Line Flows without and with Damping Controllers
CHAPTER 7
MAIN CONTRIBUTIONS AND FUTURE WORK
RECOMMENDATIONS
In this research work, we focus on the loadflow and dispatch strategies, linearized
models, dynamic simulations, and damping control design for VSC-based FACTS
Controllers in various operating modes.
7.1 Main Contributions
1. An efficient control mode implementation has been developed to reduce the
complexity associated with the many setpoint control modes, by the approach-
ing of advocating separate modelling for a shunt VSC and for a series VSC.
This separation of models can readily accommodate all VSC configurations.
In this approach, the unknown variables of the loadflow solution are always
kept the same, independent of the VSC controller operating mode. In this
way, when a VSC controller changes mode, only two equations for each shunt
VSC and two equations for each series VSC need to be adjusted.
2. Except for shunt voltage setpoint control mode and line power flow regulation
mode, additional reactive power setpoint control mode and reactive power
reserve mode for the shunt VSC and fixed injected voltage control mode for
the series VSC have been incorporated into the control mode implementation
3. Efficient dispatch strategies are developed to optimize power transfer when one
or both VSCs are loaded to their rated capacity, which allows one to study
maximum dispatchability of FACTS controllers in large power systems under
all the operating constraints considered.
4. A versatile regulator model, which includes the DC link capacitor dynamics
and takes into account various operating modes, is proposed. The control
mode implementation is applied to complete this model. The shunt VSC
120
121
controls and the series VSC controls are modeled as separate regulators. When
a VSC changes its operating mode, only the input signals of the corresponding
regulator need to be adjusted. The VSC operating constraints due to various
ratings and operating limits are imposed in the VSC controls. The versatile
regulator model has been incorporated into the positive-sequence transient
stability simulation program to evaluate their impact on transient stability
under oscillations and faults.
5. Small-signal linearized models based on the dynamic models are derived by
using small-signal perturbation. By this approach, dynamic simulation and
small-signal analysis are able to share identical codes for generators, exciters,
FACTS controllers, and so on.
6. A new modal decomposition approach, fully decouples all state modes and
considers the interaction of other state modes to the inter-area mode of in-
terest, is proposed to to quantify levels of controllability, observability, and
inner-loop gains of the linearized models.
7. Damping controllers supplemental to the regulation controls of FACTS con-
trollers are investigated to improve small-signal stability.
7.2 Future Research Recommendations
While the following items for future research are not exhaustive, they are con-
sidered important to improve the operations of the VSC-based FACTS Controllers.
1. Regulation Gain Validation for FACTS Controller Dynamic Models
2. Dynamic Simulation of Large-Scale Systems
3. Multiple FACTS coordination
Further research work is needed on the damping control design of the VSC-
based FACTS Controllers together with other regulation devices at different
122
system operating conditions. We need investigate the interactions of multiple
FACTS Controllers, that is, how one VSC controller affects the effectiveness
of other VSC controllers and how the interactions can be quantified. The
damping control design will be based on potential interactions of nearby or
coupled VSCs. Strategies for best utilizing interacting FACTS controllers for
damping control will then be provided.
4. Real-time simulation
To implement the strategies in real-time, more studies on the automatic control
system are needed.
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APPENDIX A
DATA FILE OF A 22-BUS POWER SYSTEM
22-Bus Power System Test Case
Subtransient Generator Models
Bus Data Format
Bus number, bus voltage magnitude (pu), bus voltage angle (degree), generator
real power (pu), generator reactive power (pu), load real power (pu), load reactive
power (pu), G shunt (pu), B shunt (pu), bus type: 1 for swing bus; 2 for generator
bus (PV bus); 3 for load bus (PQ bus), maximum generator reactive power (pu),
minimum generator reactive power (pu), bus voltage rating (kV), maximum bus