0,1 1 10 tal Harmonic Distortion - % 4Ohm (6kHz) 4Ohm (1kHz) TOTAL HARMONIC DISTORTION+NOISE VS OUTPUT POWER 0,001 0,01 0,1 1 10 0,01 1 100 THD+N - Total Harmonic Distortion - % P O - Output Power - W 4Ohm (6kHz) 4Ohm (1kHz) TOTAL HARMONIC DISTORTION+NOISE VS OUTPUT POWER TC = 75 C CONFIG = BTL TAS5611 www.ti.com SLAS681A – DECEMBER 2009 – REVISED APRIL 2010 125W STEREO / 250W MONO PurePath™ HD ANALOG-INPUT POWER STAGE Check for Samples: TAS5611 1FEATURES APPLICATIONS • Home Theater Systems 23• PurePath™ HD Enabled Integrated Feedback Provides: • AV Receivers • DVD/Blu-ray Receivers – Signal Bandwidth up to 80kHz for High Frequency Content From HD Sources • Mini Combo System • Active Speakers and Subwoofers – Ultralow 0.03% THD at 1W into 4Ω – Flat THD at all Frequencies for Natural DESCRIPTION Sound – 80dB PSRR (BTL, No Input Signal) The TAS5611 is a high performance analog input Class D amplifier with integrated closed loop – >100dB (A weighted) SNR feedback technology (known as PurePath™ HD) with – Click and Pop Free Startup the ability to drive up to 125W (1) Stereo into 4 to 8 Ω • Pin compatible with TAS5630, TAS5615 and Speakers from a single 32.5V supply. TAS5613 PurePath™ HD technology enables traditional • Multiple Configurations Possible on the Same AB-Amplifier performance (<0.03% THD) levels while PCB With Stuffing Options: providing the power efficiency of traditional class D amplifiers. – Mono Parallel Bridge Tied Load (PBTL) – Stereo Bridge Tied Load (BTL) Unlike traditional Class D amplifiers, the distortion curve only increases once the output levels move into – 2.1 Single Ended Stereo Pair and Bridge clipping. PurePath™ HD Power PAD™ Tied Load Subwoofer PurePath™ HD technology enables lower idle losses • Total Output Power at 10%THD+N making the device even more efficient. – 250W in Mono PBTL Configuration into 2Ω – 125W per Channel in Stereo BTL Configuration into 4Ω • Total Output Power in BTL configuration at 1%THD+N – 130W Stereo into 3Ω – 105W Stereo into 4Ω – 70W Stereo into 6Ω – 55W Stereo into 8Ω • >90% Efficient Power Stage With 60-mΩ Output MOSFETs • Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short-Circuit Protection) With Error Reporting • EMI Compliant When Used With Recommended System Design • Two Thermally Enhanced Package Options: (1) Achievable output power levels are dependent on the thermal – PHD (64-Pin QFP) configuration of the target application. A high performance – DKD (44-Pin PSOP3) thermal interface material between the package exposed heatslug and the heat sink should be used to achieve high output power levels. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2PurePath, Power PAD are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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0,1
1
10
talH
arm
on
icD
isto
rtio
n-
%
4Ohm (6kHz)
4Ohm (1kHz)
TOTAL HARMONIC DISTORTION+NOISEVS
OUTPUT POWER
0,001
0,01
0,1
1
10
0,01 1 100
TH
D+
N-
To
talH
arm
on
icD
isto
rtio
n-
%
PO - Output Power - W
4Ohm (6kHz)
4Ohm (1kHz)
TOTAL HARMONIC DISTORTION+NOISEVS
OUTPUT POWER
TC = 75 CCONFIG = BTL
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
125W STEREO / 250W MONO PurePath™ HD ANALOG-INPUT POWER STAGECheck for Samples: TAS5611
1FEATURES APPLICATIONS• Home Theater Systems
23• PurePath™ HD Enabled Integrated FeedbackProvides: • AV Receivers
• DVD/Blu-ray Receivers– Signal Bandwidth up to 80kHz for HighFrequency Content From HD Sources • Mini Combo System
• Active Speakers and Subwoofers– Ultralow 0.03% THD at 1W into 4Ω– Flat THD at all Frequencies for Natural
DESCRIPTIONSound– 80dB PSRR (BTL, No Input Signal) The TAS5611 is a high performance analog input
Class D amplifier with integrated closed loop– >100dB (A weighted) SNRfeedback technology (known as PurePath™ HD) with
– Click and Pop Free Startup the ability to drive up to 125W (1) Stereo into 4 to 8 Ω• Pin compatible with TAS5630, TAS5615 and Speakers from a single 32.5V supply.
TAS5613PurePath™ HD technology enables traditional
• Multiple Configurations Possible on the Same AB-Amplifier performance (<0.03% THD) levels whilePCB With Stuffing Options: providing the power efficiency of traditional class D
amplifiers.– Mono Parallel Bridge Tied Load (PBTL)– Stereo Bridge Tied Load (BTL) Unlike traditional Class D amplifiers, the distortion
curve only increases once the output levels move into– 2.1 Single Ended Stereo Pair and Bridgeclipping. PurePath™ HD Power PAD™Tied Load SubwooferPurePath™ HD technology enables lower idle losses• Total Output Power at 10%THD+Nmaking the device even more efficient.– 250W in Mono PBTL Configuration into 2Ω
– 125W per Channel in Stereo BTLConfiguration into 4Ω
• Total Output Power in BTL configuration at1%THD+N– 130W Stereo into 3Ω– 105W Stereo into 4Ω– 70W Stereo into 6Ω– 55W Stereo into 8Ω
• >90% Efficient Power Stage With 60-mΩOutput MOSFETs
• Self-Protection Design (IncludingUndervoltage, Overtemperature, Clipping, andShort-Circuit Protection) With Error Reporting
• EMI Compliant When Used WithRecommended System Design
• Two Thermally Enhanced Package Options:(1) Achievable output power levels are dependent on the thermal– PHD (64-Pin QFP)
configuration of the target application. A high performance– DKD (44-Pin PSOP3) thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve highoutput power levels.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PurePath, Power PAD are trademarks of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
PIN ONE LOCATION PHD PACKAGE
2616
15
OC_ADJ
14
RESET
13
C_STARTUP
12
INPUT_A
11
INPUT_B
10
VI_CM
9
GND8AGND7
VREG
6
INPUT_C
5
INPUT_D
4
FREQ_ADJ
3
OSC_IO+
2
OSC_IO-
1
SD 64-pins QFP package
Pin 1 MarkerWhite Dot
32
GN
D_D
31
PV
DD
_D
30
PV
DD
_D
29
OU
T_D
28
OU
T_D
27
BS
T_D
GV
DD
_D
25
GV
DD
_C
24
GN
D23
GN
D22
NC
21
NC
20
NC
19
NC
18
PS
U_R
EF
17
VD
D
33 GND_D34 GND_C35 GND_C36 OUT_C37 OUT_C38 PVDD_C39 PVDD_C40 BST_C41 BST_B42 PVDD_B43
OUT_B44
GND_B45
GND_A
464748
55
49
50
51
RE
AD
Y
52
M1
53
M2
54
M3
GN
D
56
GN
D57
GV
DD
_B
58
GV
DD
_A
59
BS
T_A
60
OU
T_A
61
OU
T_A
62
PV
DD
_A
63
PV
DD
_A
64
GN
D_A
OTW1
CLIP
PVDD_B
OUT_B
GND_B
DKD PACKAGE(TOP VIEW)
44
pins
PA
CK
AG
E(T
OP
VIE
W)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23M3
OC_ADJ
VDD
PSU_REF
M2
M1
READY
OTW
SD
OSC_IO-
OSC_IO+
FREQ_ADJ
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
RESET
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
GND_D
GVDD_AB
GVDD_CD
PVDD_A
PVDD_D
OUT_D
OUT_A
OT
W2
PHD PACKAGE(TOP VIEW)
Electrical Pin 1
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5611 is available in two thermally enhanced packages:• 64-Pin QFP (PHD) Power Package• 44-Pin PSOP3 package (DKD)
The package types contain heat slugs that are located on the top side of the device for convenient thermalcoupling to the heat sink.
2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
MODE SELECTION PINS
MODE PINS OUTPUTANALOG INPUT DESCRIPTION
CONFIGURATIONM3 M2 M1
0 0 0 Differential 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 Differential 2 × BTL BD mode
Differential Single0 1 1 1 × BTL +2 ×SE BD mode, BTL DifferentialEnded
1 0 0 Single Ended 4 × SE AD mode
INPUT_C (1) INPUT_D (1)
1 0 1 Differential 1 × PBTL 0 0 AD mode
1 0 BD mode
1 1 0Reserved
1 1 1
(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=GND).
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER TAS5611PHD TAS5611DKD
RqJC (°C/W) – 2 BTL or 4 SE channels 3.2 2.1
RqJC (°C/W) – 1 BTL or 2 SE channel(s) 5.4 3.5
RqJC (°C/W) – 1 SE channel 7.9 5.1
Pad Area (2) 64 mm2 80 mm2
(1) JC is junction-to-case, CH is case-to-heat sink(2) RqCH is an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the
pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and 0.44°C/W forthe DKD package.
Table 1. ORDERING INFORMATION (1)
TA PACKAGE DESCRIPTION
0°C–70°C TAS5611PHD 64 pin HTQFP
0°C–70°C TAS5611DKD 44 pin PSOP3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TAS5611
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted (1)
VALUE UNIT
VDD to GND –0.3 to 13.2 V
GVDD to GND –0.3 to 13.2 V
PVDD_X to GND_X (2) –0.3 to 53 V
OUT_X to GND_X (2) –0.3 to 53 V
BST_X to GND_X (2) –0.3 to 66.2 V
BST_X to GVDD_X (2) –0.3 to 53 V
VREG to GND –0.3 to 4.2 V
GND_X to GND –0.3 to 0.3 V
GND to AGND –0.3 to 0.3 V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO-, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF –0.3 to 4.2 Vto GND
INPUT_X –0.3 to 7 V
RESET, SD, OTW1, OTW2, CLIP, READY to GND –0.3 to 7 V
Continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA
Operating junction temperature range, TJ 0 to 150 °C
Storage temperature, Tstg –40 to 150 °C
Human body model (3) (all pins) ±2 kVElectrostatic discharge
Charged device model (3) (all pins) ±500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Please ensure
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 16 32.5 34.1 V
GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4Output filter according to schematics in theRL(SE) Load impedance 1.8 2 Ωapplication information section
RL(PBTL) 1.6 2
Output filter according to schematics in theapplication information section and addRL(BTL) Load impedance 2.8 3 ΩSchottky diodes on all output nodes to GND_X,ROC = 22kΩ
LOUTPUT(BTL) 7 10
LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 mH
LOUTPUT(PBTL) 7 10
Nominal 350 400 450PWM frame rate selectable for AM interferenceFPWM AM1 300 340 380 kHzavoidance; 1% Resistor tolerance.
AM2 260 300 335
Nominal; Master mode 9.5 10 10.5
RFREQ_ADJ PWM frame rate programming resistor AM1; Master mode 19.8 20 20.2 kΩ
AM2; Master mode 29.7 30 30.3
CPVDD PVDD close decoupling capacitors 2.0 mF
ROC Over-current programming resistor Resistor tolerance = 5% 22 30 kΩ
ROC_LATCHED Over-current programming resistor Resistor tolerance = 5% 47 64 kΩ
4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
RECOMMENDED OPERATING CONDITIONS (continued)over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Voltage on FREQ_ADJ pin for slave modeVFREQ_ADJ Slave mode 3.3 Voperation
TJ Junction temperature 0 150 °C
PIN FUNCTIONSPIN
FUNCTION (1) DESCRIPTIONNAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_D required.
CLIP 18 — O Clipping warning; open drain; active low
C_STARTUP 3 5 O Startup ramp requires a charging capacitor of 4.7 nF to GND in BTL mode
FREQ_ADJ 12 14 I PWM frame rate programming pin requires resistor to GND
7, 23, 24, 57,GND 9 P Ground58
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate drive voltage supply requires 0.1 mF capacitor to GND_A
GVDD_B 56 — P Gate drive voltage supply requires 0.1 mF capacitor to GND_B
GVDD_C 25 — P Gate drive voltage supply requires 0.1 mF capacitor to GND_C
GVDD_D 26 — P Gate drive voltage supply requires 0.1 mF capacitor to GND_D
GVDD_AB — 44 P Gate drive voltage supply requires 0.22 mF capacitor to GND_A/GND_B
GVDD_CD — 23 P Gate drive voltage supply requires 0.22 mF capacitor to GND_C/GND_D
INPUT_A 4 6 I Input signal for half bridge A
INPUT_B 5 7 I Input signal for half bridge B
INPUT_C 10 12 I Input signal for half bridge C
INPUT_D 11 13 I Input signal for half bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect, pins may be grounded.
OC_ADJ 1 3 O Analog overcurrent programming pin requires 30kΩ resistor to GND.
OSC_IO+ 13 15 I/O Oscillator master/slave output/input.
OSC_IO– 14 16 I/O Oscillator master/slave output/input.
OTW — 18 O Overtemperature warning signal, open drain, active low.
OTW1 16 — O Overtemperature warning signal, open drain, active low.
OTW2 17 — O Overtemperature warning signal, open drain, active low.
OUT_A 52, 53 39, 40 O Output, half bridge A
OUT_B 44, 45 36 O Output, half bridge B
OUT_C 36, 37 31 O Output, half bridge C
OUT_D 28, 29 27, 28 O Output, half bridge D
PSU_REF 63 1 P PSU Reference requires close decoupling of 330 pF to GND
(1) I = Input, O = Output, P = Power
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TAS5611
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
PIN FUNCTIONS (continued)
PINFUNCTION (1) DESCRIPTION
NAME PHD NO. DKD NO.
Power supply input for half bridge A requires close decoupling of 2uF capacitorPVDD_A 50, 51 41, 42 P GND_A
Power supply input for half bridge B requires close decoupling of 2uF capacitorPVDD_B 42, 43 35 P GND_B
Power supply input for half bridge C requires close decoupling of 2uFPVDD_C 38, 39 32 P capacitor GND_C
Power supply input for half bridge D requires close decoupling of 2uFPVDD_D 30, 31 25, 26 P capacitor GND_D
READY 19 19 O Normal operation; open drain; active high
RESET 2 4 I Device reset Input; active low
SD 15 17 O Shutdown signal, open drain, active low
Power supply for digital voltage regulator requires a 10-mF capacitor in parallelVDD 64 2 P with a 0.1-mF capacitor to GND for decoupling.
VI_CM 6 8 O Analog comparator reference node requires close decoupling of 1nF to GND
VREG 9 11 P Digital regulator supply filter pin requires 0.1-mF capacitor to GND
6 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
2-CHANNELH-BRIDGEBTL MODE
Output
H-Bridge 2
PV
DD
_A
,B
,C
,D
GN
D_
A,
B,C
,D
Hardwire
Over-
Current
Limit
8
GN
D
VD
D
VR
EG
AG
ND
OC
_A
DJ
PVDDPower Supply
Decoupling
GVDD, VDD,
& VREGPower Supply
Decoupling
SYSTEM
Power
Supplies
PVDD
GVDD (12V)/VDD (12V)
GND
32.5V
12V
GND
VAC
Bootstrap
Caps
BST_C
BST_D
2nd
Order
L-C Output
Filter for
each
H-Bridge
OUT_C
OUT_D
GV
DD
_A
,B
,C
,D
Bootstrap
Caps
BST_A
BST_B
INPUT_A 2nd
Order
L-C Output
Filter for
each
H-Bridge
OUT_A
OUT_B
8 4
Output
H-Bridge 1
Input
H-Bridge 1INPUT_B
M2
M1
M3
Hardwire
Mode
Control
Input
H-Bridge 2
INPUT_C
INPUT_DV
I_C
M
C_S
TA
RT
UP
PS
U_R
EF
Caps for
External
Filtering
&
Startup/Stop
Input DC
Blocking
Caps
Input DC
Blocking
Caps
/RE
SE
T
/OT
W1
,/O
TW
2,/O
TW
/CLIP
System
microcontroller
or
Analog circuitry
RE
AD
Y
/SD
ANALOG_IN_A
ANALOG_IN_B
ANALOG_IN_C
ANALOG_IN_D
FREQ_ADJ
Hardwire
PWM Frame
Rate Adjust
&
Master/Slave
Mode
OSC_IO+
OSC_IO-
Oscillator
Synchronization
2
2
2
2
(2)
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
TYPICAL SYSTEM BLOCK DIAGRAM
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TAS5611
M1
M2
/RESET
/SD
/OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD_C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_XOUT_XGND_X
TIMING
CONTROLCONTROL GATE-DRIVE
TIMING
CONTROLCONTROL GATE-DRIVE
TIMINGCONTROL
CONTROL GATE-DRIVE
TIMING
CONTROLCONTROL GATE-DRIVE
PWMRECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
AN
AL
OG
CO
MP
AR
ATO
RM
UX
+
-
+
-
+
-
PR
OT
EC
TIO
N&
I/O
LO
GIC
VI_CM
STARTUP
CONTROL
POWER-UP
RESET
TEMPSENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
OSCILLATOR
FREQ_ADJ
OSC_SYNC_IO-
AN
AL
OG
INP
UT
MU
X
PSU_FFPSU_REF
4
4
4
PVDD_X4
GND
OSC_SYNC_IO+
/OTW1
READY
/CLIP
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
AUDIO CHARACTERISTICS (BTL)PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V,GVDD_X = 12 V, RL = 4Ω, fS = 400kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7mH, CDEM = 680nF,MODE = 010, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 3 Ω, 10% THD+N (add Schottky diodes onall output nodes OUT_X to GND_X, ROC = 16522kΩ)
RL = 4 Ω, 10% THD+N 125PO Power output per channel W
RL = 3 Ω, 1% THD+N (add Schottky diodes onall output nodes OUT_X to GND_X, ROC = 13022kΩ)
RL = 4 Ω, 1% THD+N 105
THD+N Total harmonic distortion + noise 1 W 0.03%
A-weighted, AES17 filter, Input CapacitorVn Output integrated noise 168 mVGrounded
|VOS| Output offset voltage Inputs AC coupled to GND 20 40 mV
SNR Signal-to-noise ratio (1) A-weighted, AES17 filter 100 dB
DNR Dynamic range A-weighted, AES17 filter 100 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 1.3 W
(1) SNR is calculated relative to 1% THD+N output level..(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO CHARACTERISTICS (PBTL)PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V,GVDD_X = 12 V, RL = 2Ω, fS = 400kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7 mH, CDEM = 1.5 mF,MODE = 101-10, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10% THD+N 250
RL = 3 Ω, 10% THD+N 165
RL = 4 Ω, 10% THD+N 125PO Power output per channel W
RL = 2 Ω, 1% THD+N 210
RL = 3 Ω, 1% THD+N 135
RL = 4 Ω, 1% THD+N 105
THD+N Total harmonic distortion + noise 1 W 0.03%
Vn Output integrated noise A-weighted 170 mV
SNR Signal to noise ratio (1) A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 1.3 W
(1) SNR is calculated relative to 1% THD-N output level.(2) Actual system idle losses are affected by core losses of output inductors.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TAS5611
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
ELECTRICAL CHARACTERISTICSPVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as referenceVREG VDD = 12 V 3 3.3 3.6 Vnode, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 20IVDD VDD supply current mA
Idle, reset mode 20
50% duty cycle 10IGVDD_X GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output 10 mAfilterIPVDD_X Half-bridge supply currentReset mode, No switching 540 mA
ANALOG INPUTS
RIN Input resistance READY = HIGH 33 kΩVIN Maximum input voltage swing 7 V
IIN Maximum input current 1 mA
G Voltage Gain (VOUT/VIN) 21 dB
OSCILLATOR
Nominal, Master Mode 3.5 4 4.5
fOSC_IO+ AM1, Master Mode FPWM × 10 3.0 3.4 3.8 MHz
AM2, Master Mode 2.6 3 3.35
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) 60 100 mΩTJ = 25°C, excludes metallizationRDS(on) resistance, GVDD = 12 VDrain-to-source resistance, high side (HS) 60 100 mΩ
10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS (continued)PVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I/O PROTECTION
Undervoltage protection limit, GVDD_x andVuvp,G 9.5 VVDD
Vuvp,hyst(1) 0.6 V
OTW1 (1) Overtemperature warning 1 95 100 105 °C
OTW2 (1) Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTWOTWhyst
(1) temperature for OTW to be inactive after 25 °COTW event.
Overtemperature error 145 155 165 °COTE (1)
OTE-OTW differential 30 °C
A reset needs to occur for SD to be releasedOTEhyst(1) 25 °Cfollowing an OTE event
OLPC Overload protection counter fPWM = 400 kHz 2.6 ms
Resistor – programmable, nominal peak 12.6 Acurrent in 1Ω load, ROCP = 30kΩResistor – programmable, nominal peakIOC Overcurrent limit protectioncurrent in 1Ω load, ROCP = 22kΩ (add 16.3 ASchottky diodes on all output nodesOUT_X to GND_X)
Resistor – programmable, nominal peak 12.6 Acurrent in 1Ω load, ROCP = 64kΩResistor – programmable, nominal peakIOC_LATCHED Overcurrent limit protectioncurrent in 1Ω load, ROCP = 47kΩ (add 16.3 ASchottky diodes on all output nodesOUT_X to GND_X)
Time from switching transition to flip-stateIOCT Overcurrent response time 150 nsinduced by overcurrent
Connected when RESET is active toInternal pulldown resistor at output of eachIPD provide bootstrap charge. Not used in SE 3 mAhalf bridge mode.
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage 1.9 VINPUT_X, M1, M2, M3, RESET
VIL Low level input voltage 0.8 V
Ilkg Input leakage current 100 mA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to VREG,RINT_PU 20 26 32 kΩOTW2 to VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6VOH High level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low level output voltage IO = 4 mA 200 500 mV
Device fanout OTW1, OTW2, SD, CLIP,FANOUT No external pullup 30 devicesREADY
(1) Specified by design.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TAS5611
0
50
100
150
200
P-
Ou
tpu
t P
ow
er
- W
O
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PV - Supply Voltage - VDD
T = 75°C
THD+N = 10%C
3 W
4 W
6 W
8 W
0.001
0.01
0.1
1
10
TH
D+
N -
To
tal H
arm
on
ic D
isto
rtio
n +
No
ise -
%
0.01 1 100P - Output Power - WO
0.1 10 1000
3 W
4 W
6 W
8 W
T = 75°CC
0
50
100
150
P-
Ou
tpu
t P
ow
er
- W
O
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PV - Supply Voltage - VDD
3 W
4 W
6 W
8 W
T = 75°CC
100
90
80
70
60
50
40
30
20
10
0
Eff
icie
ncy -
%
0 50 100 150 200 250 3002 Channel Output Power - W
4 W6 W8 W
T = 25°C
THD+N = 10%C
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATIONTOTAL HARMONIC+NOISE OUTPUT POWER
vs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 1. Figure 2.
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCYvs vs
SUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
0
10
20
30
40
4 W
6 W
8 W
T = 25°C
THD+N = 10%C
0 50 100 150 200 250 3002 Channel Output Power - W
Po
wer
Lo
ss -
W
20 30 40 50 60 70 80 90 100
T - Case Temperature - °CC
0
50
100
150
200
P-
Ou
tpu
t P
ow
er
- W
O
3 W
4 W
6 W
8 W
THD+N = 10%
-160
-140
-120
-100
-80
-60
-40
-20
0
0 5 10 15 20f - Frequency - kHz
4 W
T = 75°C,
VREF = 22.98 V,Sample Rate = 48 kHz,FFT Size = 16384
C
No
ise
Am
plitu
de -
dB
0.001
0.01
0.1
1
10
TH
D+
N -
To
tal H
arm
on
ic D
isto
rtio
n -
%
10 100 1k 10k 100k
f - Frequency - Hz
R = 4 ,
T = 75°C,
Toroidal Output Inductors
L
C
W
1W
17.3 W (1/8 Power)
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)SYSTEM POWER LOSS OUTPUT POWER
vs vsOUTPUT POWER CASE TEMPERATURE
Figure 5. Figure 6.
NOISE AMPLITUDE TOTAL HARMONIC DISTORTION+NOISEvs vs
FREQUENCY FREQUENCY
Figure 7. Figure 8.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TAS5611
0
50
100
150
200
250
300
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PV - Supply Voltage - VDD
P-
Ou
tpu
t P
ow
er
- W
O
3 W
4 W
6 W
8 W
T = 75°C
THD+N = 10%C
2 W
0.01 1 100P - Output Power - WO
0.1 10 1000
0.001
0.01
0.1
1
10
TH
D+
N -
To
tal H
arm
on
ic D
isto
rtio
n +
No
ise -
%
3 W
4 W
6 W
8 W
T = 75°CC 2 W
0
50
100
150
200
250
300
20 30 40 50 60 70 80 90 100
T - Case Temperature - °CC
P-
Ou
tpu
t P
ow
er
- W
O
3 W
4 W
6 W
8 W
THD+N = 10%
2 W
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATIONTOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 9. Figure 10.
OUTPUT POWERvs
CASE TEMPERATURE
Figure 11.
14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2 oz. (70mm) is recommended for use with the TAS5611. The use of thismaterial can provide for higher power output, improved thermal performance, and better EMI margin (due tolower PCB trace inductance).
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. Thesecapacitors should be selected for proper voltage margin and adequate capacitance to support the powerrequirements. In practice, with a well designed system power supply, 1000mF, 50V will support moreapplications. The PVDD capacitors should be low ESR type because they are used in a circuit associated withhigh-speed switching.
DECOUPLING CAPACITOR RECOMMENDATIONS
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audioperformance, a quality decoupling capacitors should be used. In practice, X7R should be used in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in theselection of the 2mF that is placed on the power supply to each half-bridge. It must withstand the voltageovershoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripplecurrent created by high power output. A minimum voltage rating of 50V is required for use with a 32.5V powersupply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices used for the TAS5611.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TAS5611
IN_
LE
FT
_N
IN_
LE
FT
_P
R_
RIG
HT
_N
IN_
RIG
HT
_P
/RE
SE
T
/SD
/OT
W1
/OT
W2
/CL
IP
RE
AD
Y
OS
C_
IO+
OS
C_
IO-
GV
DD
/VD
D (
+12
V)
PV
DD G
VD
D/V
DD
(+
12V
)
PV
DD
PV
DD
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VR
EG
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VR
EG
VR
EG
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
OU
T_
LE
FT
_P
OU
T_
LE
FT
_M
+-
OU
T_
RIG
HT
_P
OU
T_
RIG
HT
_M
+-17
62
63 18
19
64
20
21
24
23
22
25
27
26
29
28
30
31
32
1
33
34
35
37
2 3
36
4
38
39
5 6 7
40
41
8 9
42
10
43
11
44
45
12
46
47
13
48
14
15
49
16
50
51
52
54
53
56
55
57
58
59
60
61
C2
3
33
0p
F
C2
3
33
0p
F
R71
3.3
R
R71
3.3
R
C1
5
10
0p
F
C1
5
10
0p
F
R72
3.3
RR
72
3.3
R
C30
10
0n
F
C30
10
0n
F
C3
3
10
0n
F
C3
3
10
0n
F
C2
0
4.7
nF
C2
0
4.7
nF
C61
2uF
C61
R73
3.3
RR
73
3.3
R
R3
2
3.3
R
R3
2
3.3
R
C72
1n
FC
72
1n
F
R2
1
10
kR2
1
10
k
C6
02
uF
C6
0
L11
7uH
L11
7uH
C53
68
0nF
C53
68
0nF
C2
2
10
0n
F
C2
2
10
0n
F
R30
3.3
R
R30
3.3
R
C1
8
10
0p
F
C1
8
10
0p
F
C50
68
0nF
C50
68
0nF
R3
1
3.3
R
R3
1
3.3
R
C52
68
0nF
C52
68
0nF
C64
10
00u
F
C64
10
00u
F
L10
7uH
L10
7uH
C3
2
10
0nF
C3
2
10
0nF
C77
10n
FC
77
10n
F
C1
7
10
0p
F
C1
7
10
0p
F
C4
1
33n
F
C4
1
33n
F
R70
3.3
RR
70
3.3
R
C11
10
0p
F
C11
10
0p
F
C4
033
nF
C4
033
nF
R11
10
0R
R11
10
0R
L12
7uH
L12
7uH
R3
3
3.3
R
R3
3
3.3
R
C6
6
100
0uF
C6
6
100
0uF
C4
2
33n
F
C4
2
33n
FC
16
10
uF
C1
6
10
uF
C69
2.2
uF
C69
2.2
uF
C1
4
10
uF
C1
4
10
uF
C7
8
10n
F
C7
8
10n
F
R1
9
47
k
R1
9
47
k
C1
2
10
uF
C1
2
10
uF
R1
3
10
0R
R1
3
10
0R
L13
7uH
L13
7uH
C74
10n
FC
74
10n
F
C26
10
0nF
C26
10
0nF
C2
1
1n
F
C2
1
1n
F
C2
51
0u
FC
25
10u
F
C1
0
10
uF
C1
0
10
uF
C67
10
00u
F
C67
10
00u
F
R1
0
10
0R
R1
0
10
0R
C51
68
0nF
C51
68
0nF
C70
1n
FC
70
1n
F
R1
8
10
0R
R1
8
10
0R
C4
333
nF
C4
333
nF
C75
10n
F
C75
10n
F
C62
2uF
C62
R2
0
30
k
R2
0
C6
5
10
00
uF
C6
5
10
00
uF
C1
31
00
pF
C1
31
00
pF
C71
1n
FC
71
1n
F
C3
1
10
0n
F
C3
1
10
0n
F
C6
32
uF
C6
3C
73
1n
FC
73
1n
F
R7
4
3.3
R
R7
4
3.3
R
R1
2
10
0R
R1
2
10
0R
C76
10n
FC
76
10n
FC6
847
uF
63V
C6
847
uF
63V
U10
TA
S5611
PH
D
OC
_A
DJ
/RE
SE
T
C_S
TA
RT
UP
INP
UT
_A
INP
UT
_B
VI_
CM
GN
D
AG
ND
VR
EG
INP
UT
_C
INP
UT
_D
FR
EQ
_A
DJ
OS
C_IO
+
OS
C_IO
-
/SD
/OT
W1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GN
D_A
GN
D_B
GN
D_B
OU
T_B
OU
T_B
PV
DD
_B
PV
DD
_B
BS
T_B
BS
T_C
PV
DD
_C
PV
DD
_C
OU
T_C
OU
T_C
GN
D_C
GN
D_C
GN
D_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
Figure 12. Typical Differential Input BTL Application With BD Modulation Filters
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5611
IN_
N
IN_
P
/RE
SE
T
/SD
/OT
W1
/OT
W2
/CL
IP
RE
AD
Y
GV
DD
(+
12
V)
PV
DD
OS
C_
IO+
OS
C_
IO-
GV
DD
(+
12
V)
VD
D (
+1
2V
)
PV
DD
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VR
EG
GN
D
GN
D
GN
D
GN
DG
ND
VR
EG
GN
DG
ND
GN
D
GN
DG
ND
GN
D
VR
EG
VR
EG
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
1 2 3 4 5 6 7 8 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+-
OU
T_LE
FT
_P
OU
T_LE
FT
_M
4.7
nF
4.7
nF
10
0n
F1
00
nF
3.3
R3
.3R
10
0n
F1
00
nF
10
0n
F1
00
nF
10
00
uF
63
V1
00
0u
F6
3V
10
uF
10
uF
33
0p
F3
30
pF
10
00
uF
63
V
10
00
uF
63
V7
uH
7u
H
3.3
R3
.3R
47
k4
7k
2u
F
3.3
R3
.3R
1n
F1
00
V1
nF
10
0V
10
0n
F1
00
nF
10
00
uF
63
V1
00
0u
F6
3V
10
uF
10
uF
7u
H7
uH
3.3
R3
.3R
33
nF
33
nF
47
uF
63
V
47
uF
63
V
1u
F2
50
V2
50
V
25
0V
1u
F
25
0V
10
0R
10
0R
1n
F1
nF
10
0R
10
0R
3.3
R3
.3R
10
nF
10
0V
10
nF
10
0V
10
0R
10
0R
2u
F
7u
H7
uH
33
nF
33
nF
10
0n
F1
00
nF
10
nF
10
0V
10
nF
10
0V
10
0p
F1
00
pF
10
uF
10
uF
1n
F1
00
V1
nF
10
0V
TA
S5
611
PH
D
OC
_A
DJ
/RE
SE
T
C_
STA
RT
UP
INP
UT
_A
INP
UT
_B
VI_
CM
GN
D
AG
ND
VR
EG
INP
UT
_C
INP
UT
_D
FR
EQ
_A
DJ
OS
C_
IO+
OS
C_
IO-
/SD
/OT
W1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GN
D_
A
GN
D_
B
GN
D_
B
OU
T_
B
OU
T_
B
PV
DD
_B
PV
DD
_B
BS
T_
B
BS
T_
C
PV
DD
_C
PV
DD
_C
OU
T_
C
OU
T_
C
GN
D_
C
GN
D_
C
GN
D_
D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
2u
F
10
0p
F1
00
pF
30
k
10
nF
10
0V
10
nF
10
0V
2.2
uF
10
0V
2.2
uF
10
0V
3.3
R3
.3R
33
nF
33
nF
3.3
R3
.3R
7u
H7
uH
10
00
uF
63
V1
00
0u
F6
3V
2u
F
10
0p
F1
00
pF
10
0n
F1
00
nF
33
nF
33
nF
10
k1
0k
TAS5611
www.ti.com SLAS681A –DECEMBER 2009–REVISED APRIL 2010
Figure 13. Typical Differential (2N) PBTL Application With BD Modulation Filters
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30 k
W
2F
m
2F
m
2F
m
2F
m
TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
Figure 14. Typical Differential Input BTL Application With BD Modulation Filters DKD Package
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5611 needs only a 12V supply in addition to the (typical) 32.5V power-stagesupply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analogcircuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, isaccommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive andoutput stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separategate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, anadditional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12V source,it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuitboard (PCB) by RC filters (see application diagram for details). These RC filters provide the recommendedhigh-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to theirassociated pins as possible. In general, inductance between the power supply pins and decoupling capacitorsmust be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor ischarged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and thebootstrap pin. When the powerstage output is high, the bootstrap capacitor potential is shifted above the outputpotential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWMswitching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even duringminimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remainingpart of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCBplacement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). Foroptimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin isdecoupled with a 2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended tofollow the PCB layout of the TAS5611 reference design. For additional information on recommended powersupply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output impedance voltage regulator. Likewise, the 32.5Vpower-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is notcritical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5611 is fully protected againsterroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) arenon-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5611 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedancestate until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specificallyrequired, it is recommended to hold RESET in a low state while powering up the device. This allows an internalcircuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5611 does not require a power-down sequence. The device remains fully operational as long as thegate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltagethreshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is agood practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active low, open-drain outputs. Their function is for protection-modesignaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes lowwhen the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperatureexceeds 100°C (see the following table).
OTW2,SD OTW1 DESCRIPTIONOTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature0 0 1 warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TIrecommends monitoring the OTW signal using the system microcontroller and responding to an overtemperaturewarning signal by, e.g., turning down the volume to prevent further heating of the device resulting in deviceshutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTWoutputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see theElectrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5611 contains advanced protection circuitry carefully designed to facilitate system integration and easeof use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such asshort circuits, overload, overtemperature, and undervoltage. The TAS5611 responds to a fault by immediatelysetting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other thanoverload and overtemperature error (OTE), the device automatically recovers when the fault condition has beenremoved, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
BTL Mode PBTL Mode SE Mode
Local error in Turns Off or in Local error in Turns Off or in Local error in Turns Off or in
A A AA+B A+B
B B BA+B+C+D
C C CC+D C+D
D D D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) isshorted to GND_X or PVDD_X. For comparison, the OC protection system detects an over current after thedemodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed atstartup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup will notactivate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridgesare kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and startsswitching. The detection is controlled globally by a two step sequence. The first step ensures that there are noshorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The totalduration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is
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<15ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changesapplied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A devicereset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, thedetection is not performed in SE mode. To make sure the PPSC detection system is not tripped, it isrecommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options has individual overtemperature protection schemes.
PHD Package:The TAS5611 PHD package option has a three-level temperature-protection system that asserts an active lowwarning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the devicejunction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), thedevice is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.Thereafter, the device resumes normal operation.
DKD Package:The TAS5611 DKD package option has a two-level temperature-protection system that asserts an active lowwarning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junctiontemperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputsbeing set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear theOTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5611 fully protect the device in any power-up/down and brownout situation.While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fullyoperational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold onany VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)state and SD being asserted low. The device automatically resumes operation when all supply voltages haveincreased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enablesweak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state whenasserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SDoutput, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation afteran overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after thefalling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audibleartifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signalgoes low, hence, filtering is needed if the signal is intended for audio muting in non microcontroller systems.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audiovolume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequencycan be changed from nominal to lower values. These values should be chosen such that the nominal and thelower value switching frequencies together results in the fewest cases of interference throughout the AM band,and can be selected by the value of the FREQ_ADJ resistor connected to GND in master mode.
For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This will configure theOSC_I/O pins as inputs and needs to be slaved from an external clock.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply forpower and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuitcontains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routingthe audio input should be kept short and together with the accompanied audio source ground. A local groundarea underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 12.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins andwithout going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink andclose to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 15. Printed Circuit Board - Top Layer
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Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keepimpedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductancecurrent loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 16. Printed Circuit Board - Bottom Layer
SPACER
REVISION HISTORY
Changes from Original (December 2009) to Revision A Page
• Deleted the Product Preview banner from the DKD PACKAGE .......................................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com 12-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type PackageDrawing
Pins Package Qty Eco Plan (2) Lead/Ball Finish
MSL Peak Temp (3) Samples
(Requires Login)
TAS5611PHD NRND HTQFP PHD 64 90 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TAS5611PHDR NRND HTQFP PHD 64 1000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
TAS5611PHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5611PHDR HTQFP PHD 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.
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