System design methodology

System Design System Design Methodology Methodology

System Design System Design Methodology Methodology

Gookyi Dennis A. N. Gookyi Dennis A. N.

SoC Design Lab.SoC Design Lab.

August.26.2014

ContentsContents Finite-State Machines (FSM) RTL Design RTL Implementation Options

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Finite State Machines (FSMs)Finite State Machines (FSMs)

3

Finite State Machines (FSMs)Finite State Machines (FSMs) Moore and Mealy machines

4

DQ

QB

Combinationalcircuit

Combinationalcircuit

Clock Present state

Next state

Inputsoutputs

DQ

QB

Combinationalcircuit

Combinationalcircuit

Clock Present state

Next state

Inputsoutputs

Moore machine

Mealy machine

Finite State Machines (FSMs)Finite State Machines (FSMs) Common FSM encoding options:

One-hot codeBinary codeGray code Random code

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State Binary Gray One hot

A 00 00 1000

B 01 01 0100

C 10 11 0010

D 11 10 0001

Finite State Machines (FSMs)Finite State Machines (FSMs) There are two basic approaches to realize an FSM in

Verilog HDL:Explicit FSM:

• States are declared explicitly • Easy to write• Very widely used

Implicit FSM:• State register not declared explicitly • Inferred from the activity within a cyclic behavior• Hard to write• Not supported by every synthesis tool

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FSM Modeling StylesFSM Modeling Styles Realization issues:

State-registerNext-state and output functions

State registerOne registerTwo registers

Output and next state functionsContinuous assignment FunctionAlways block

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FSM Modeling StylesFSM Modeling Styles Problem description: Pattern Detector A sequential circuit has input x and output z. the

input receives a sequence of 1 and 0. the output outputs a 1 when ever the circuit detects the pattern 0101 in its input

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Input(x)

Clock(clk)

Output(z)

A B C D

1/0

1/0

0/0

0/0

0/0

0/0 1/0 1/1Block diagram

State diagram

Timing chart

FSM Modeling StylesFSM Modeling Styles Transition table:

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Present state Input Next state output

A 00 00

01

B 01A 00

00

B 01 01

01

B 01C 10

00

C 10 10

01

D 11A 00

00

D 11 11

01

B 01C 10

01

A B C D

1/0

1/0

0/0

0/0

0/0

0/0 1/0 1/1

FSM Modeling StylesFSM Modeling Styles One state register style:

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• Declare one state register for both present state and next state

Part 1:•Initialize and update the state register•Use an always block for this purpose•The next state is computed by the function fsm_next_state

Part 2:•compute next state using function•Next state is dependent on both current inputs and present state

Part 3:•Compute output function•Can take the form of an always block or a continuous assignment•The output function is dependent on the current inputs and the state

FSM Modeling StylesFSM Modeling Styles RTL schematic of one state register style:

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FSM Modeling StylesFSM Modeling Styles Testbench and waveform for one state register style:

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FSM Modeling StylesFSM Modeling Styles Two state register style:

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• Two registers are declared for the present state and next state

Part 1:•Initialize and update the present state register•An always block is used for this purpose

Part 2:•Compute the next state•An always block is used to compute the next state from both the current input and the present state

Part 3:•Compute the output function•The output function can be computed by using either an always block or continuous assignment

FSM Modeling StylesFSM Modeling Styles RTL schematic and waveform of two register state

style:

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RTL DesignRTL Design RTL design is often used for designing large systems

at the algorithmic level Digital systems operate at RTL in such a way that

data from the output of registers are transferred to other registers through a combinational logic which is used to change the property of the data

Two widely used design approaches at RTL include:ASM chartDatapath and controller

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ASM ChartASM Chart Two essential features of ASM charts:

They specify RTL operations since they define what happens on every cycle of operation

They show clearly the flow of control from state to state

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ASM ChartASM Chart An ASM chart is composed of three types of blocks,

state block, decision block and conditional output block

An ASM block contains exactly one state block together with possible decision and condition blocks

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Block Description

State Specifies a machine state and a set of unconditional RTL operations associated with itEach state along with its related operations occupy a clock period

Condition

Describe RTL operations that are executed under conditions specified by decision blocksInputs must be from outputs of decision blocks

Decision Describes the condition under which an ASM will execute specific actions and select the next state based on the value of the primary input or present state

Output or operation Output or operation

condition conditioncondition

State nameState assignment

(invalid) 0

(invalid) 0

(invalid) 1

(invalid) 1

State block Conditional output block

Decision block

ASM ChartASM Chart Features of ASM block:

It has exactly one entrance path and one or more exit paths

It contains one state block and a serial-parallel network of decision and conditional output blocks

Example of valid ASM blocks:

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00x

0

1

1

0

00x

0

01

1x1

x1

x2

x2

B B + 3B B + 3

C 0

C 0d 5 d 5

Serial test Parallel test

ASM ChartASM Chart Basic constructing rules for ASM charts:

Each state and its associated set of conditions must define a unique next state

Every path of the network of conditions must terminate at a next state

There cannot exist any loop in the network of conditions

Examples of invalid ASM blocks

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ASM ChartASM Chart Equivalence between state diagram and ASM chart

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A

C

B

z’

z’

z’

z

z z

x

x

x

0

0

0

1

1

1

1/0

1/0

0/1

0/1

1/10/0

x/z

State diagram

ASM chart

A

C

B

ASM Modeling StylesASM Modeling Styles Like FSM, ASM chart can be modeled in two styles:

One register and one always block styleTwo registers and three always block style

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ASM Modeling StylesASM Modeling Styles Problem description: Booth Algorithm Assume two inputs X and Y, then the Booth

(multiplication) algorithm is described as follows: Initialization:

Load acc and mp[0] with zerosLoad mp[W:1] with multiplier and mcand with

multiplicand Repeat n times:

If mp[1] = 1 and mp[0] = 0, do acc – mcand, else if mp[1]=0 and mp[0]=1, do acc + mcand

Shift {acc,mp} one bit right using sign extension

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mp[1] mp[0]

Operation

1 0 acc - mcand

0 1 acc + mcand

1 1 No operation

0 0 No operation

ASM Modeling StylesASM Modeling Styles Example: 119 * 19 = 2261 mp = 01110111 mcand = 00010011 / 11101101

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acc mp[W:1] mp[0]

cnt operation

0000000011101101

01110111

0 7 acc = acc – mcand

1110110111110110111110111111110100010011

101110110101110110101110

111

765

Right shift acc:mpRight shift acc:mpRight shift acc:mpacc = acc + mcand

000100000000100011101101

01010111

0 4 Right shift acc:mp

1111010111111010111111011111111000010011

101010110101010110101010

111

321

Right shift acc:mpRight shift acc:mpRight shift acc:mpacc = acc + mcand

0001000100001000

11010101

0 0 Right shift acc:mp

mp[1] mp[0]

Operation

1 0 acc - mcand

0 1 acc + mcand

1 1 No operation

0 0 No operation+

+

+

+

- mcand

2261

ASM Modeling StylesASM Modeling Styles ASM chart of Booth Algorithm

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idle

load

compute

shiftright

finish

mcand <- multiplicandmp <- multiplieracc <- 0cnt <- W - 1

finish <- 1 cnt != 0

mp[1:0]

acc <- acc - mcandacc <- acc + mcand

{acc, mp} <- {acc[n-1], acc, mp}cnt <- cnt - 1

01

0011

10

10

0

1

ASM Modeling StylesASM Modeling Styles One register one always block style:

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• Declare only one state register

• Using only one always block, initialize, compute, update the state register and execute RTL operations

• An if-else is used to separate the initial operations from the rest of the operations in the ASM chart

ASM Modeling StylesASM Modeling Styles RTL schematic of one register style:

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ASM Modeling StylesASM Modeling Styles Testbench and waveform of one register style:

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ASM Modeling StylesASM Modeling Styles Two registers three always blocks style:

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• Declare two registers, one for the present state and the other for the next state

Part 1:•Initialize and update state register

Part 2:•Compute next state from both current input and present state

Part 3:•Execute RTL operations using case statements

ASM Modeling StylesASM Modeling Styles RTL schematic of two register state style:

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ASM Modeling StylesASM Modeling Styles Waveform of two register state style:

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Datapath and Controller Datapath and Controller designdesign In general, a digital system is composed of:

DatapathMemory Controller

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Unit Description Implementation

Datapath Performs all operations desired in the system

Adder/subtractor, multiplier, shifter, ALU, comparator, registers

Memory Temporarily stores intermediate data used and generated by the datapath

RAM, ROM, shift registers, registers

Controller Controls and schedules all operations performed by the datapath

FSM described by state diagram or ASM chart and implemented by using PLA, ROM or random logic

Data outputData input

dataread/write

statusControl signals

Memory

Datapath

Controllerclock

Datapath and Controller Datapath and Controller designdesign Transforming an ASM chart into a datapath and

controller architecture follows three steps:Model the design Extract datapath from the module and construct it as

an independent moduleExtract the control unit and construct a top module

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Datapath and Controller Datapath and Controller designdesign Datapath and controller extracted from ASM chart of

Booth Algorithm:

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Datapath and Controller Datapath and Controller designdesign Datapath and controller signals

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Signal Description

start_n Reset signal resets all modules to their initial states

mcand_load

Load multiplicand into the register mcand

add_sub Determines whether the operation is add or sub

acc_mode Two bit selection signal:00: do nothing10: load the accumulator01: shift the content of the accumulator to the right once

mp_mode Two bit mode selection signal:00: do nothing10: load register mp01: shift content of register mp to the right once

Datapath and Controller Datapath and Controller designdesign Datapath module of booth algorithm:

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Shift register module:Instantiated for both acc and mp to shift their contents to the right

Register module:For storing the contents of mcand

Addsub module:For performing both addition and subtraction depending on the control signals

Datapath and Controller Datapath and Controller designdesign Datapath module of booth algorithm: top module

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Datapath and Controller Datapath and Controller designdesign RTL schematic of datapath:

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Datapath and Controller Datapath and Controller designdesign Controller module of booth algorithm

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Datapath and Controller Datapath and Controller designdesign Combining all modules into a top module:

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Datapath and Controller Datapath and Controller designdesign RTL schematic of datapath and controller design of

Booth algorithm: the interface

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Datapath and Controller Datapath and Controller designdesign RTL schematic of datapath and controller design of

Booth algorithm:

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Datapath and Controller Datapath and Controller designdesign Waveform:

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