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The Pennsylvania State University
The Graduate School
SYNTHESIS, PROCESSING, AND ELECTRICAL CHARACTERIZATION OF
1.1 State of the Electronics Industry ................................................................................... 1
1.2 Role of Novel Materials ............................................................................................... 3 1.3 Goal of this Thesis ....................................................................................................... 4
Chapter 2: Literature Review ...................................................................................................... 6
2.1 History of Graphene .................................................................................................... 6 2.2 Structure and Properties ............................................................................................... 7
4.2 Diffusion Barrier Studies ........................................................................................... 65 4.3 Transfer Process Optimization ................................................................................... 77
Chapter 5: Device Fabrication and Electrical Characterization ................................................... 84
5.1 Ohmic Contact Development ..................................................................................... 84 5.2 Transport Studies on Various Substrates .................................................................... 94
Appendix B: Electrical Transport Modeling ............................................................................ 119
B.1. Script for fitting experimental data ........................................................................... 119
B.2. Script for projections on various substrates .............................................................. 122
B.3. Temperature function ............................................................................................... 126 B.4. Sheet carrier density function ................................................................................... 128
B.5. Impurity Concentration Function ............................................................................. 130
vi
List of Figures
Figure 1-1: Comparison of normalized energy-delay product for silicon MOSFETs to
InGaAs/InAlAs and InSb/InAlSb quantum well transistors. The quantum well transistors are
demonstrated with performance metrics 1-3 orders of magnitude better than silicon devices at
similar scaling levels. Figure adapted from Reference [15]. ......................................................... 4
Figure 2-1: Graphene as the building block for all graphitic materials, including buckyballs
(left), carbon nanotubes (center), and graphite (right). Figure adapted from Reference [19]. ........ 7
Figure 2-2: Various visual representations of a single graphene sheet. While graphene is
often depicted as a perfectly planar surface (a), it actually exhibits small out-of-plane ripples,
as shown in (b). Figure adapted from Reference [36]. .................................................................. 8
Figure 2-3: E-k relation for different charge carrier behaviors. In conventional
semiconductors, charge carriers behave as Schrodinger fermions and follow a parabolic E-k
relationship near the band edges (a). In graphene, carriers have zero effective mass, instead
behaving as Dirac fermions with a linear band dispersion (b). Figure adapted from Reference
First, I would like to thank my advisor, Dr. Joshua A. Robinson, for his support
throughout both my undergraduate and graduate studies. The path to completion of my master’s
degree has been a long and winding one, and his support and patience have been invaluable to my
ability to ultimately reach my goals. I would not be where I am today without his knowledge,
guidance, and support, and I am forever grateful to him for helping me become a better researcher
and person.
I would also like to extend my sincere thanks to Dr. David Snyder and the Penn State
Electro-Optics Center for giving me the opportunity to begin my research career in the first place.
To my labmates: Mike Bresnehan, Matt Hollander, Zach Hughes, and Max Wetherington
– you guys are my brothers. I could not have asked for a better group of people to work with and
learn from. The time we spent together – in the office, in the fab, out on the town – is time that I
look back on with the fondest of memories. I would also like to give a special thanks to Mike
LaBella and Kathy Trumbull, both for their extensive assistance in this research and for creating
such a great environment to work in. You are two of the most dedicated, hardworking, and caring
people that I have ever met, and you made our lab group like a family.
Finally, I’d like to extend my thanks to the long list of people within the EOC, Materials
Characterization Lab, and Penn State Nanofabrication Facility who provided assistance with a
wide variety of aspects of this work: To Rebecca Marucci and Greg Pastir for assistance with
graphene growth; to Bangzhi Liu, Shane Miller, Guy Lavallee, and Andrzej Mieckowski for
training and help with device fabrication; and to Josh Stapleton and Vince Bojan for their insight
on device characterization.
1
Chapter 1: Introduction
1.1 State of the Electronics Industry
In 1965, Intel co-founder Gordon Moore published the now famous paper, “Cramming
more components onto integrated circuits” [1]. This paper contained Moore’s prediction that the
density of transistors on an integrated circuit (IC) would increase exponentially, doubling
approximately every year. Moore later revised his prediction to call for doubling every two years
[2], one that has remained accurate at describing transistor scaling for the last four decades [3].
This pattern has become known as “Moore’s Law,” and is actively used by the semiconductor
industry as a guideline for future production targets [4].
Continued scaling of silicon MOSFETs is driven by several key performance metrics that
benefit from device scaling. First and most intuitively, is the obvious increase in circuit
complexity that comes with device scaling. If all device dimensions are scaled by a factor α, the
density of devices on a chip scales by a factor α2 [5]. Thus, an IC consisting of scaled devices
would be capable of storing more information or carrying out more operations than an
equivalently-sized IC of a previous generation. As the cost of processing a silicon wafer is
relatively independent of device size, device scaling also decreases the per-device cost of
fabrication [1]. Furthermore, device scaling results in improvements in device switching speed
and power consumption. According to constant-field scaling theory (also known as Dennard
scaling), circuit delay time scales as 1/α, while power dissipation scales by 1/α 2 [5–7].
Early in silicon MOSFET development, limitations on device size were primarily due to
lithography restrictions – that is, the ability to pattern smaller device features [5,7]. Thus, as
lithographic techniques improved, devices scaled in a pattern closely following Dennard scaling.
The 2018 International Roadmap for Devices and Systems (IRDS) describes this period as the
“Geometrical Scaling” era, in which both vertical and horizontal dimensions were scaled together
in close accordance with Dennard scaling [8]. However, due to nonscaling of device threshold
2
voltages and “reluctance to depart from the standardized voltage levels of the previous generation
[7],” device scaling below 1-2 µm features has followed a general trend of increasing oxide field.
This pattern is shown in Table 1-1. Additionally, scaling into the sub-micrometer range has
resulted in a number of deleterious device behaviors that also serve as barriers to further device
scaling. These include increased gate leakage due to tunneling currents through the thin oxide
layer and a variety of “short-channel effects” that result from increased influence of the source
and drain depletion regions on the channel behavior [7].
Table 1-1: Increasing oxide field with subsequent VLSI generations, showing a gradual increase in oxide
field over time. Table adapted from Reference [7].
Feature size
(µm)
Power-supply
voltage (V)
Gate oxide
thickness (Å)
Oxide field
(MV/cm)
2.00 5 350 1.4 1.20 5 250 2.0
0.80 5 180 2.8
0.50 3.3 120 2.8 0.35 3.3 100 3.3
0.25 2.5 70 3.6
0.10 1.5 30 5.0
The semiconductor industry has successfully developed a number of techniques for
suppressing these undesired behaviors to allow continued scaling. These include the adoption of
high-κ gate dielectrics to allow for thicker gate oxides [9], strained silicon-germanium for
increased carrier mobility [7,9], and the use of either silicon-on-insulator [10] or multi-gate
structures [11] to minimize short-channel effects. These techniques have allowed for scaling of
production devices to as small as 6 nm [12], and together form the period described as the
“Equivalent Scaling” era by IRDS [8]. This represents the period of time in which horizontal
device dimensions continue to shrink at a similar pace, but with deviation from historical trends
in vertical scaling and introduction of new materials. Important to note is that IRDS has identified
the end of the Equivalent Scaling era as imminent; within the last several years, memory
applications have already been forced to stack devices vertically (3D integration) in order to
continue to meet device density requirements. Furthermore, a true limit to horizontal scaling of
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conventional CMOS is expected to be reached sometime in the early 2020s [8]. While a variety of
new technologies are being pursued, one promising path identified by IRDS is the incorporation
of two-dimensional channel materials such as graphene, which could allow for even further
horizontal scaling, as well as providing performance benefits in switching speed and switching
energy over silicon-based CMOS [13].
1.2 Role of Novel Materials
While silicon has been the basis of CMOS technology since its inception, the use of novel
materials may become necessary to continue scaling devices beyond the fundamental limits of
silicon technology [14]. One of the great advantages that germanium, III-V semiconductors, and
novel materials such as graphene have over silicon is improved charge carrier mobility.
According to Taur and Ning, “Relatively speaking, mobility is the most important parameter for
CMOS performance” (authors’ emphasis) [7]. Thus, by replacing silicon with a higher mobility
material, device performance could be improved beyond the current limits of silicon. Evidence of
this performance gain has already been demonstrated for quantum well transistors fabricated from
various III-V semiconductors, although they have only been demonstrated for n-channel devices
to date [15]. The normalized energy-delay product, a common figure of merit for logic devices, as
a function of gate length is compared for III-V quantum well transistors and silicon MOSFETs in
Figure 1-1. Furthermore, at highly scaled device dimensions, graphene also benefits from its high
carrier saturation velocity – demonstrated to be in excess of 5x107 cm/s [16].
4
Figure 1-1: Comparison of normalized energy-delay product for silicon MOSFETs to InGaAs/InAlAs and
InSb/InAlSb quantum well transistors. The quantum well transistors are demonstrated with performance
metrics 1-3 orders of magnitude better than silicon devices at similar scaling levels. Figure adapted from
Reference [15].
In addition to graphene’s outstanding intrinsic carrier mobility, its two-dimensional
nature makes it extremely attractive for highly scaled devices. Modeling shows that a device with
a thin channel region and a thin gate dielectric will be most resistant to short-channel effects [17].
Thus, at only one atom thick, graphene is essentially the limiting case for scalability to extremely
short gate lengths [18]. While intrinsic graphene’s lack of a band gap presents a large barrier to its
integration into modern CMOS production, it does present a possible long-term replacement for
silicon in electronic devices. Additionally, graphene is considered a much nearer-term material
for radiofrequency (RF) applications, as the majority of power consumption in RF circuits is a
consequence of the device amplification rather than static leakage currents. Thus, lack of a band
gap does not preclude the use of intrinsic graphene in RF devices [18].
1.3 Goal of this Thesis
This work has three primary objectives: First, to provide the reader with a thorough
background on graphene and summarize important previous research in graphene synthesis,
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device fabrication, and electrical performance; second, to describe experimental work on the
synthesis, processing, and characterization of graphene films completed as part of this research;
and third, to utilize theoretical modeling of electrical transport in graphene films to explain the
experimental results and guide recommendations on future development of graphene-based
microelectronics.
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Chapter 2: Literature Review
This section provides a brief background on the history and properties of graphene, with
a particular focus on electron transport and other properties that are particularly relevant for the
use of graphene in modern microelectronic devices. It also describes several methods that can be
used to synthesize graphene and related materials, such as reduced graphene oxide. Finally, this
section describes recent work in graphene device fabrication and performance, including studies
on ohmic contacts to graphene, integration of dielectrics in graphene field-effect devices, and
theoretical modeling of carrier scattering physics that serve as limiting factors in current devices.
2.1 History of Graphene
While graphene is conventionally understood to have been “discovered” in 2004 [19],
atomically thin carbon films have been studied both theoretically and experimentally for many
decades [20–25]. This includes experimental work on graphite oxide and the derivative graphene
oxide as early as 1961 [22], as well observation of graphene formation on various metal surfaces
several years thereafter [23–25]. However, it was not until 2004 that single-layer graphene was
isolated from bulk graphite by researchers at the University of Manchester, marking the first time
that a truly two-dimensional crystal had been formed without being strongly bonded to a bulk
substrate [26]. Subsequent experiments identifying graphene’s novel electronic properties, such
as the relativistic behavior of its charge carriers [27], high electron mobility [28], and observation
of the quantum Hall effect [29] have made graphene a candidate for a variety of novel electronic
applications.
Subsequent to the demonstration of freestanding graphene, evidence of various other two-
dimensional crystals was also published [30]. By simply rubbing a bulk sample of a particular
layered material against a target substrate, researchers were able to successfully isolate single
sheets of a wide variety of low dimensional materials. This includes hexagonal boron nitride (h-
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BN), various transition metal dichalcogenides (TMDs) (MoS2, MoSe2, WS2, WSe2, NbSe2), and
the complex oxide Bi2Sr2CaCu2Ox. In the time since graphene was first identified, these other
materials have also garnered a great deal of attention for their potential device applications. For
example, h-BN has received focus as a lattice-matched substrate and/or dielectric for graphene
devices [31,32], while various TMDs – MoS2 in particular – have been widely studied as a
potential channel material in novel devices due to their presence of a band gap [33].
2.2 Structure and Properties
2.2.1 Atomic Structure
Graphene is a single atomic sheet of sp2-bonded carbon atoms – the atomically thin limit
of graphite. The carbon atoms form a honeycomb arrangement, with each carbon atom bonded to
its adjacent carbon atoms with one sigma bond and one third of a pi bond [34]. This arrangement
can be considered as the basis for all graphitic materials, as one can visualize a graphene sheet
being “…wrapped up into 0D buckyballs, rolled into 1D nanotubes or stacked into 3D graphite”
[19]. This is shown graphically in Figure 2-1.
Figure 2-1: Graphene as the building block for all graphitic materials, including buckyballs (left), carbon
nanotubes (center), and graphite (right). Figure adapted from Reference [19].
8
The formal definition of the word “graphene” would restrict its use to apply solely to the
case of a single atomic layer. According to the International Union of Pure and Applied
Chemistry (IUPAC), “The term ‘graphene’ should be used only when the reactions, structural
relations or other properties of individual layers are discussed” [35]. However, as structures
consisting of several atomic layers show properties similar to those of a monolayer and quite
different from bulk graphite, the terms “bi-layer graphene” and “few-layer graphene” have also
gained acceptance. The boundary between what can reasonably be considered graphene is
typically accepted as between five and ten atomic layers, when the properties of the film
transition to match those of bulk graphite [19].
While artists’ renderings often present graphene as a perfectly planar surface (see Figure
2-2a), it has been demonstrated that even a single atomic layer of graphene possesses a three-
dimensional structure. Both experimental measurements and theoretical calculations show the
presence of out-of-plane ripples in the graphene structure, typically on the order of tens of
nanometers [36,37] (Figure 2-2b). The appearance of these ripples can be explained by
anharmonic coupling of the bending and stretching phonon modes, which suppress long-range
fluctuations [37]. Thus, while these ripples result in an increase in strain energy, they provide an
overall reduction in free energy that makes such two-dimensional crystals thermodynamically
stable [19,37].
Figure 2-2: Various visual representations of a single graphene sheet. While graphene is often depicted as a
perfectly planar surface (a), it actually exhibits small out-of-plane ripples, as shown in (b). Figure adapted
from Reference [36].
9
2.2.2 Band Structure
In most conventional semiconductors, the energy-wavenumber (E-k) relationship of
charge carriers is approximately parabolic near the conduction and valence band edges, following
the relation
𝐸 =|ℏ2𝒌2|
2𝑚∗ , ( 2-1 )
where ħ is the reduced Planck constant, k is the electron wavevector, and m* is the effective mass
of the charge carrier [38]. This relation is identical to the solution of Schrödinger’s equation for a
free electron, except that the effective mass is used to reflect the interaction between a charge
carrier and the crystal lattice [39]. Graphene, on the other hand, possesses a linear band
dispersion near the neutrality point, reflecting the massless nature of its charge carriers [38,40].
Thus, their behavior is described by the relativistic Dirac equation
𝐸 = |ℏ𝒌|𝑣𝑓 , ( 2-2 )
with the Fermi velocity vf (~106 m/s) substituted for the speed of light [38]. The three-
dimensional band structure for conventional semiconductors and graphene are shown in Figure
2-3.
Figure 2-3: E-k relation for different charge carrier behaviors. In conventional semiconductors, charge carriers behave as Schrodinger fermions and follow a parabolic E-k relationship near the band edges (a). In
graphene, carriers have zero effective mass, instead behaving as Dirac fermions with a linear band
dispersion (b). Figure adapted from Reference [41].
10
This unique band structure has a number of important implications for graphene devices.
First, graphene possesses no energy gap; the valence and conduction bands meet at the six
equivalent points in the first Brillouin zone, commonly referred to as the Dirac points [40]. Thus,
graphene exhibits an ambipolar electric field effect, switching between electron and hole
conduction as an applied bias is swept through the neutrality point. This effect is shown in Figure
2-4. Interestingly, graphene has also been found to be conductive even at the neutrality point,
where theory predicts it to be completely devoid of charge carriers. Various groups have
measured a minimum sheet conductivity on the order of 4e2/h for graphene devices, which
corresponds to a sheet resistivity of approximately 6.5 kΩ/sq [19,27,42,43]. The physical
explanation of this phenomenon is a matter of some debate, with some proposing that the
quantization of minimum conductivity is an inherent result of the two-dimensional system [27],
while others claim that it is simply evidence of charge inhomogeneity that results from inherent
impurities in the graphene system [43].This presents challenges for practical graphene devices,
particularly in the form of high off-state current and poor gate modulation in graphene transistors
[18].
11
Figure 2-4: Ambipolar electric field effect in a graphene device. Graphene can be tuned between electron
conduction (positive bias) and hole conduction (negative bias), with a region of high resistivity at zero applied bias corresponding to the Dirac point. Insets show representative E-k diagrams for the various
regimes. Figure adapted from Reference [19].
2.2.3 Transport
In addition to its unique band structure, graphene has carrier transport properties unlike
those of any other material. Carrier mobilities of approximately 200,000 cm2 V-1 s-1 have been
measured at cryogenic temperatures, exceeding those of any other known material [28,44,45].
However, it should be noted that these high values are only obtained for suspended graphene that
is measured in vacuum following current annealing to drive off adsorbed molecules. This
illustrates the strong influence of interfaces between graphene and other materials and their
ability to limit or alter the properties of a graphene sheet. Nonetheless, room-temperature
mobilities of 10,000-15,000 cm2 V-1 s-1 are common for high quality graphene on SiO2 substrates
[26,46].
12
Theoretical modeling of carrier transport in graphene has focused on three main
carbon nanotubes [103], and most recently, graphene [104].
The Raman signature of graphitic materials contains three peaks of interest, shown in
Figure 2-14. The Raman G-peak, or “graphite peak”, is located at ~1580 relative cm-1 and occurs
due to interaction with the doubly degenerate E2g phonons from in-plane vibrations of carbon-
carbon sp2 bonds [104]. Thus, it is present in all graphitic materials. The D-peak at ~1360 cm-1,
on the other hand, occurs due to zone-boundary phonons, which do not obey the fundamental
Raman selection rule. Thus, the D-peak normally only appears when scanning near grain
boundaries or in defective material [104]. The ratio of the D-peak intensity to G-peak intensity,
known as the D/G ratio or ID/IG, is frequently used as a quantitative means for describing the
defectiveness of graphene, and has been empirically related to the mean graphene crystallite size,
La, by the relation
𝐿𝑎(nm) =560
𝐸𝑙4 (
𝐼𝐷
𝐼𝐺)−1
, ( 2-3 )
where El is the laser excitation energy in eV [105]. La can also be thought of as a mean inter-
defect distance, allowing for its use in quantitatively comparing the crystalline quality of
synthesized graphene [106].
27
Figure 2-14: Raman spectra of bulk graphite, showing the D-peak at ~1380 cm-1, G-peak at ~1580 cm-1,
and 2D-peak at ~2700 cm-1. Figured adapted from Reference [79].
The final peak of interest is the Raman 2D-peak, located at ~2700 cm-1. This peak was
also historically referred to as the G’-peak [99]. But rather than the doubly degenerate E2g
phonons, this peak occurs due to a double resonance of zone boundary phonons. This has led to
most modern discussion referring to this peak as 2D to more accurately reflect its underlying
mechanism [104]. The 2D-peak is of particular significance when characterizing graphene films
because its width, intensity, and shape is highly dependent on the number of graphene layers
present. In bulk graphite, the 2D-peak is typically only approximately half the intensity of the G-
peak and is made up of several components. But as the number of layers decreases and the
electronic structure simplifies, the 2D-peak narrows to a strong, symmetrical peak that is several
times the intensity of the G-peak. This is accompanied by a downward shift in peak position of
approximately 50 wavenumbers for exfoliated graphene.
28
Figure 2-15: Comparison of Raman spectra of bulk graphite and monolayer graphene. Compared to bulk
graphite, the Raman signal of graphene shows a substantial increase in the relative intensity of the 2D-peak,
as well as substantial narrowing; in monolayer graphene, the 2D-peak is symmetric and can be fit by a
single Lorentzian. Figure adapted from Reference [104].
The combination of defect quantification and thickness estimation in a single
characterization technique has led to Raman spectroscopy becoming one of the most frequently
used tools in current graphene research [62,81,93]. Furthermore, Raman has been demonstrated to
provide quantitative information on graphene doping [106] and strain [107,108], further
increasing its utility in characterizing graphene films.
2.5 Materials Integration
In addition to research on graphene itself, a large amount of work has focused on the
ability to integrate graphene with other materials, with the obvious end-goal of demonstrating
useful graphene devices. Two of the primary research areas for graphene transistor production are
the formation of ohmic contacts and the integration of high-quality dielectric materials.
29
2.5.1 Ohmic Contacts to Graphene
The formation of low resistance ohmic contacts is of paramount importance in the
fabrication of any practical transistor. In conventional semiconductor production, low contact
resistance is produced by a combination of several well-studied factors: Proper selection of
contact metal or silicide, sufficient doping levels of the underlying semiconductor, and optimized
processing to minimize surface states due to impurities, dangling bonds, and interfacial layers
[39]. But conventional theory is not easily applied to graphene due to its unique band structure
and lack of reliable doping methods, making the formation of low resistance ohmic contacts a
subject of considerable current research focus.
Metal-graphene interaction has been studied both theoretically and experimentally, with
mixed results. Density functional theory (DFT) studies have varied dramatically on the predicted
strength of binding between graphene and various metals and the subsequent doping and
influence on graphene band structure as a result of work function differences [109–112].
Furthermore, theoretical studies of graphene-metal do not account for the polycrystalline nature
of the metal in practical devices, nor do they take into consideration the influence of impurity
atoms trapped on the graphene surface. Experimental study of graphene-metal interfaces has
shown wide variation in the interaction distance, even for single-crystal metals meant to provide a
simplified case study [113]. Recent study of Al, Cu, Ni, Pd, and Ti contacts to graphene has
shown no clear relationship between metal work function and contact resistance, demonstrating
that the process used to deposit the contacts may be of much greater influence on contact
resistance than the metallization itself [114].
In addition to study of contact metallizations, various groups have investigated means by
which to minimize impurities at the metal-graphene interface, such as residual photoresist. In
traditional semiconductor fabrication, an oxygen plasma treatment is used to remove residual
photoresist after developing. However, oxygen plasmas can also damage the underlying graphene
films, complicating their use in removing resist residues [115]. Nonetheless, previous work has
30
shown that by careful control of the plasma time, specific contact resistance ρc can be reduced by
three orders of magnitude (from ~3x10-4 to ~4x10-7 Ω-cm2) over devices with no plasma
treatment [114]. By adding a brief contact anneal following metal deposition, specific contact
resistance was further reduced to ~7.5x10-8 Ω-cm2, illustrating the strong influence of processing
conditions on ohmic contact resistance in graphene devices. This improvement is shown in
Figure 2-16.
Figure 2-16: Effects of oxygen plasma pre-treatment and post-metal contact anneals on specific contact resistance of graphene devices. Increasing etch time initially improves contact resistance as more resist
residue is removed. But at longer etching increasingly damages the underlying graphene, resulting in an
increase in ρc above 90 seconds of plasma treatment. Figure adapted from Reference [114].
2.5.2 Dielectric Integration
Another main area of focus for graphene research is the integration of dielectric materials
for field-effect devices. Because of graphene’s unique structure and sensitivity to the surrounding
environment, proper selection of substrate and gate dielectric materials is critical for development
of high performance graphene transistors. Research on dielectric integration can be categorized
into three main groups: Theoretical work on scattering from various dielectrics, experimental
31
work on deposition of high-k dielectrics on graphene, and development of hexagonal boron
nitride (h-BN) as a lattice matched substrate and/or dielectric for graphene.
Most early graphene research (and a large majority to date) utilized a silicon wafer with a
thin (~300 nm) SiO2 layer as the substrate [26,27,29,46,104]. Oxidized silicon is inexpensive and
readily available, allows for identification of few-layer graphene flakes by optical microscopy
[57], and allows for back-gating of graphene devices, eliminating the need for a top-gate or
allowing for double-gated devices [116]. A thin (<50 nm) evaporated layer of SiO2 can also be
used as a top-gate dielectric, resulting in a graphene channel layer sandwiched between two SiO2
regions of different thicknesses [116,117]. While devices on SiO2 remain common for physics
studies, work in high-frequency devices has already moved towards high-k materials, similar to
silicon microelectronics [18].
Theoretical work on the influence of dielectric materials, described in detail in Section
2.2.3, has identified two different mechanisms by which polar dielectrics can influence graphene
transport – screening of impurities at the graphene interfaces (which serves to increase mobility),
and scattering due to surface optical phonon (SOP) modes (which serve to degrade mobility).
These studies identified that high-k dielectrics such as HfO2 can more effectively screen charged
impurities, providing a performance boost over SiO2 [48]. However, high-k dielectrics also tend
to have lower energy SOP modes, which results in greater SOP scattering than SiO2. This effect
becomes more pronounced at high carrier concentrations, which is problematic for the operation
of devices at a high doping level in order to achieve high drive current. This effect is shown in
Figure 2-17. According to Konar et al., “The ideal dielectrics would be those that possess both
high static dielectric constants and high phonon energies that are not activated in low-field
transport [48].”
32
Figure 2-17: Carrier mobility as a function of dielectric constant. While high-k dielectrics are extremely
effective at screening charged impurities, their increased SOP scattering effectively negates the potential
performance boost. Figure adapted from [48].
Efforts to incorporate high-k dielectrics with graphene devices have largely focused on
the difficulty of forming a high-quality oxide without significantly damaging the underlying
graphene. This difficulty is a result of the incompatibility of atomic layer deposition (ALD) – a
common technique for depositing high-quality oxides in conventional semiconductor fabrication
– with graphene due to its hydrophobic nature and lack of dangling bonds [118]. ALD relies on
the deposition of reactive precursor species either by physisorption or by rapid dissociative
chemisorption, neither which occur readily on the surface of a pristine graphene film. Figure
2-18 illustrates the poor coverage that occurs when attempting to deposit a high-k dielectric by
ALD directly on the graphene surface. Several methods have been demonstrated to allow for the
use of ALD with graphene, including functionalization of the graphene by acids or organics
[118], spin-coating of an organic polymer “buffer layer” prior to oxide deposition [119], or
33
evaporation of an ultrathin (1-2 nm) metal or oxide seed layer, immediately followed by ALD of
the high-k dielectric [50,120]. The use of a homogeneous stack (e.g. evaporated HfO2 followed
by ALD HfO2) has been shown to be particularly promising, with no measurable degradation of
the underlying graphene and considerable increase in carrier mobility and device performance as
a result of the increased dielectric screening of the HfO2 [50].
Figure 2-18: AFM imaging of graphene flakes on oxidized silicon before and after low-temperature atomic
layer deposition of aluminum oxide. Due to graphene’s hydrophobic nature and lack of dangling bonds,
nucleation of Al2O3 only occurs on the edges of the graphene flakes and on topological defects resulting in
little or no coverage across the majority of the graphene surface. Figure adapted from Reference [118].
The final area of materials integration research focuses on the use of hexagonal boron
nitride as both the substrate and dielectric overlayer in graphene devices. Because h-BN is a two-
dimensional material and has no dangling bonds, it is predicted to provide a higher quality
interface with graphene than traditional three-dimensional materials [31]. Furthermore, DFT
calculations predict that a lattice-matched graphene/h-BN stack would open a band gap of 53
meV in the graphene film, substantially improving the on-off ratio and saturation behavior of
graphene transistors [121]. Boron nitride also possesses high energy SOP modes, which would
introduce minimal scattering compared to other candidate dielectrics. Initial demonstrations of
34
graphene/h-BN integration relied on one or more layer transfer processes similar to what has been
used for integration of graphene with arbitrary substrates, but later work successfully integrated
the two materials by CVD of polycrystalline h-BN on epitaxial graphene [32] as well as direct
epitaxy of graphene on h-BN by way of plasma-enhanced CVD [122]. Subsequent device
characterization has shown promising device behavior, including minimal degradation of
mobility and increased cutoff frequency when compared to devices with HfO2 as the gate
dielectric, bolstering the case for h-BN as a promising dielectric for use with graphene devices.
35
Chapter 3: Experimental Methods
This section describes the various methods used to synthesize and characterize graphene,
transfer graphene sheets to insulating substrates, and fabricate electrical devices for testing. It also
describes the various electrical testing methods used for evaluation of the properties of the
graphene devices and the theoretical modeling used to explain observed transport behavior.
3.1 Graphene Synthesis
Several different graphene synthesis processes were used throughout this work. Early
experiments utilized a hydrogen/methane source gas similar to previous work by the author [123],
while later experiments included the addition of argon to the source gas as a result of continued
optimization and other work published in the literature. These processes are described in detail in
sections 3.1.2 and 3.1.3, respectively.
3.1.1 Equipment
All graphene synthesis was conducted using an MTI Corporation OTF-1200X split-hinge
vacuum tube furnace and flows of ultrahigh purity (99.999%) argon, hydrogen, and methane.
System vacuum was produced by an oil-sealed rotary vane pump, with pressure measured by a
capacitance manometer and regulated by a downstream throttling valve. The experimental setup
is shown schematically in Figure 3-1.
36
Figure 3-1: Schematic representation of the experimental setup used for graphene synthesis, showing
source gas lines, mass flow controllers, vacuum tube furnace, vacuum gauge, downstream throttling valve,
sorbent trap, and vacuum pump.
3.1.2 Early Growth Process
Early experiments on freestanding copper foils utilized a growth process identical to
previous work by the author and similar to other previous publications, with a source gas
composed solely of hydrogen and methane [81,123]. As illustrated in Figure 3-2, samples were
annealed at 1000 °C for 30 minutes under a hydrogen flow of 30 standard cm3 per minute (sccm)
to remove copper oxide and allow for copper grain growth. Following annealing, 150 sccm of
methane was introduced for 10 minutes for graphene synthesis. To terminate graphene growth,
the samples were rapidly cooled by withdrawing them from the hot zone of the furnace. The
system was then allowed to cool to room temperature under hydrogen/methane flow before
venting to atmosphere and unloading of samples. System pressure was maintained at 1 Torr for
the duration of the growth process.
37
Figure 3-2: Growth profile for graphene synthesis on freestanding copper foils using a hydrogen/methane
source gas. Samples are annealed in hydrogen at 1000 °C for 30 minutes, followed by the addition of
methane for a 10 minute growth period.
In addition to freestanding copper foils, graphene synthesis was carried out on evaporated
copper thin films on various substrates (described in Section 3.1.4.2). Growth on thin copper
films utilized a similar process to growth on freestanding foils. However, pre-growth annealing to
achieve copper grain growth was carried out at a lower temperature – typically 700 °C – to
minimize copper evaporation that occurs at high temperature. Excessive exposure to high
temperatures can result in formation of voids in the copper film and decomposition of the film
into islands. This effect has been utilized in an attempt to achieve direct deposition of graphene
on insulating substrates [124], but has not been demonstrated to be useful for producing
continuous, high-quality graphene for device fabrication. Thus, time spent at the growth
temperature was kept to a minimum, as shown in Figure 3-3. Following annealing, the
temperature was then ramped to 1000 °C and allowed to equilibrate for 5 minutes before the
addition of the methane flow for graphene growth. All other aspects of the growth process,
including gas flows, total system pressure, and cool-down procedure, were identical to those
described in Section 3.1.2.
38
Figure 3-3: Growth profile for graphene synthesis on evaporated copper thin films using a
hydrogen/methane source gas. Samples are annealed for 30 minutes at 700 °C before ramping to the growth
temperature and introduction of methane.
3.1.3 Modified Growth Process
For later graphene device experiments, the graphene synthesis process was modified to
reflect recently published research on improving the quality of synthesized graphene [85,87,89].
This included the addition of argon to the source gas to allow for a reduction in the partial
pressures of both hydrogen and methane, as well as a lengthening of the growth time from 10
minutes to 15 minutes. In this growth process, freestanding copper foils were annealed at 1000 °C
for 30 minutes under a gas flow of 180 sccm argon and 20 sccm hydrogen, followed by a 15-
minute growth under flow of 120 sccm argon, 20 sccm hydrogen, and 60 sccm methane. The
growth process is shown in Figure 3-4. This growth process was utilized for all samples
discussed in Sections 4.3-5.1.3.
39
Figure 3-4: Growth profile for graphene synthesis on freestanding copper foils using an
argon/hydrogen/methane source gas.
3.1.4 Substrate Preparation
3.1.4.1 Freestanding Copper Foils
Commercially available copper (Cu) foils (Alfa Aesar, part 13382) were subjected to a
simple organic solvent clean, consisting of a 15-minute soak in heated acetone, followed by
rinsing in isopropyl alcohol (IPA) and deionized water. The foils were then immersed in a heated
solution of 10% acetic acid for 10 minutes to remove copper oxide on the sample surface [93],
followed by another deionized water rinse. The samples were blown dry with nitrogen and
immediately loaded into the vacuum chamber for growth.
3.1.4.2 Copper Thin Films on Rigid Substrates
Graphene synthesis was also carried out on copper thin films deposited onto rigid
substrates in order to evaluate their thermal stability and the effect on the quality of synthesized
graphene. The baseline configuration for growth on thin copper films was a 500 nm Cu film
deposited on oxidized silicon by electron beam evaporation at room temperature and 10-6 Torr. In
addition, two thin film diffusion barrier configurations were evaluated in this study – one utilizing
40
a metallic diffusion barrier layer added between the copper film and the SiO2 (i.e. Cu/metal
barrier/SiO2/Si) and one utilizing an insulating barrier layer in place of the SiO2 (i.e.
Cu/insulating barrier/Si). The latter configuration was chosen for two reasons: 1) It represents a
limiting case for diffusion and 2) It would provide improved electrostatic coupling between the
graphene and silicon back gate for device testing.
Metal barrier layers (Ni, Cr, W) were deposited onto an oxidized silicon wafer by
electron beam evaporation at room temperature and 10-6 Torr, immediately followed by a 500 nm
layer of copper. Insulating barrier layers were deposited directly onto silicon wafers by
techniques as appropriate for the given material; silicon nitride (SiNx) was deposited by plasma-
enhanced chemical vapor deposition at 300 °C from an SiH4/NH3/N2 mixture, and aluminum
oxide (Al2O3) and hafnium oxide (HfO2) were deposited by atomic layer deposition as described
elsewhere [50,120], each immediately followed by e-beam evaporation of the 500 nm Cu film.
Nickel barrier layers of 5, 10, 20, and 50 nm were evaluated, while all other barrier layers were
tested at a thickness of 50 nm. For comparison of another material system, the use of a copper
film deposited directly on a single-crystal sapphire wafer was also investigated. Table 3-1
provides a summary of all sample configurations evaluated in this work.
41
Table 3-1: Summary of various sample configurations tested during barrier layer studies.
Sample configuration Copper thickness
Barrier layer deposition technique
Barrier layer thickness (nm)
Freestanding copper foil 25 µm N/A N/A
Cu/Ni/SiO2/Si 500 nm E-beam evaporation 5
Cu/Ni/SiO2/Si 500 nm E-beam evaporation 10
Cu/Ni/SiO2/Si 500 nm E-beam evaporation 20
Cu/Ni/SiO2/Si 500 nm E-beam evaporation 50
Cu/Cr/SiO2/Si 500 nm E-beam evaporation 50
Cu/W/SiO2/Si 500 nm E-beam evaporation 50
Cu/Si3N4/Si 500 nm Plasma-enhanced CVD 50
Cu/Al2O3/Si 500 nm Atomic layer deposition 50
Cu/HfO2/Si 500 nm Atomic layer deposition 50
Cu/sapphire 500 nm N/A N/A
3.2 Graphene Layer Transfer
After synthesis on freestanding copper foils, graphene films were transferred to insulating
substrates using a wet transfer process similar to that described in literature [91,92]. First,
samples were spin coated with poly-methyl methacrylate (PMMA) (MicroChem 950,000
molecular weight, 3% in anisole) to provide mechanical support and protect the graphene film
during transfer. Next, the back side of the copper foil was exposed to a brief oxygen plasma to
remove any graphene that may have formed there during synthesis. This step is critical for ease of
etching the copper substrate, as any backside graphene will protect the copper foil and drastically
increase the time required to fully etch the copper away [81]. Details of this plasma treatment are
provided in Appendix A.1. Finally, the PMMA/graphene/copper samples were placed in a ferric
chloride etchant solution (Transene Copper Etchant Type 100) for 15 minutes to completely
remove the underlying copper, resulting in a freely floating PMMA/graphene film. For
comparison, samples were also etched using dilute nitric acid and ammonium persulfate, as have
been used in other work on CVD graphene [86,125,126]. The results of this comparison are
discussed in Section 4.3.1.
After etching of the underlying copper, the PMMA/graphene films were transferred to a
deionized water bath for fifteen minutes to remove residual ferric chloride from the sample. Next,
42
the films were transferred to a 10% hydrochloric acid solution to more aggressively remove any
residual iron atoms, similar to cleaning processes reported in literature [127]. The films were then
transferred to another deionized water bath for fifteen minutes before being withdrawn onto the
desired target substrate – oxidized silicon, single crystal sapphire, or epitaxially grown gallium
nitride on sapphire. The graphene-on-insulator samples were then baked on a contact hot plate for
30 minutes at 50 °C to drive off water trapped at the graphene/substrate interface, followed by a 5
minute bake at 120 °C to further drive off water and improve adhesion. Finally, samples were
soaked in heated acetone for 30 minutes to strip the PMMA layer, rinsed with IPA, and blown dry
with nitrogen. The full graphene transfer process is shown schematically in Figure 3-5.
Figure 3-5: Schematic representation of graphene layer transfer from copper foil to an arbitrary insulating
substrate. Figure adapted from Reference [91].
Following graphene layer transfer, the graphene-on-insulator samples were annealed in a
hydrogen atmosphere for 2 hours at 500 °C to remove any residual PMMA from the sample
surface. This step has been previously shown to be critical for removal of all PMMA residues, as
43
acetone is considered a weak resist stripping agent [91]. After annealing, samples were
characterized and processed into test structures for electrical measurements.
3.3 Materials Characterization
Materials characterization formed an important portion of this work, allowing for the
evaluation of various processing techniques and providing information to help explain observed
device behavior. Raman spectroscopy served as the primary technique for evaluating the
structural quality of graphene films, providing quantitative information on defect density and
number of graphene layers. Scanning electron microscopy (SEM) and transmission electron
microscopy (TEM) were utilized to provide high-resolution of surfaces and interfaces, both of as-
grown graphene and post-processed devices. TEM imaging was also coupled with energy-
dispersive x-ray spectroscopy (EDS) to allow for spatially resolved elemental analysis during
imaging. Additionally, Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy
(XPS) were used to evaluate the surface chemistry of as-grown and processed graphene films to
identify and quantify the presence of impurities and contaminants.
3.3.1 Raman Spectroscopy
Raman spectroscopy was used to evaluate graphene crystalline quality and layer
thickness, both following growth and during processing. All Raman spectra were taken using a
Witec CRM-200 confocal Raman microscope paired with a 488-nm argon ion laser, providing a
lateral resolution of 490 nm when using a 40x objective and 325 nm when using a 100x objective.
All spectra were taken using a laser power of 50 mW, which was sufficiently low to avoid
thermally induced damage to the graphene films.
When characterizing as-grown graphene on copper substrates, fluorescence of the
underlying copper results in a broad background signal that prevents direct observation and
comparison of the graphene peaks. The Witec Project software provides a built-in tool for
44
background subtraction, which fits up to a 9th-order polynomial to Raman signal and subtracts
that polynomial from the overall signal. By masking the regions containing the graphene peaks
from the fitting algorithm, the polynomial can be fit to the background signal, allowing for the
isolation of the graphene signal. This process is shown in Figure 3-6. Following background
subtraction, Raman data were exported to Excel for quantitative analysis.
Figure 3-6: Background subtraction from Raman spectra of graphene on copper. Fluorescence of the
copper substrate results in a strong background signal (a). By fitting a polynomial to all data points except
those within the Raman D-, G-, and 2D-peaks (b), the background signal can be subtracted. This provides
the clear Raman signal of the graphene itself, which can be used for peak intensity calculations and defect
density quantification (c).
45
3.3.2 Scanning Electron Microscopy
Scanning electron microscopy (SEM) is a high-resolution imaging technique that
provides complementary information to conventional optical microscopy. In SEM imaging, a
concentrated electron beam is rastered across a sample surface, and the electrons emitted from the
sample surface are collected and counted. For topological imaging, collection is limited to
secondary electrons – low-energy electrons that are ejected from the sample when the incident
electrons are inelastically scattered [98]. All images were taken at high vacuum (<10-5 Torr) using
a Leo 1530 Field-Emission Scanning Electron Microscope.
3.3.3 Transmission Electron Microscopy
Transmission electron microscopy (TEM) is another imaging technique that relies on a
high-energy electron beam as the means of sample interrogation. In this technique, the high-
energy electron beam is focused on a sample typically less than a few hundred nanometers in
thickness. This allows for the formation of an image from transmitted electrons, rather than
reflected or emitted electrons as are used with SEM. This provides TEM with unrivaled spatial
resolution, with many TEM systems capable of imaging features at an atomic scale. By
Post-growth characterization of foil-grown samples yields similar results to current
literature [81,85,86,93]. Raman spectroscopy data are presented in Figure 4-1 for growths at 850,
925, and 1000 °C using the original growth process described in Section 3.1.2, and growth at
1000 °C using the modified growth process described in Section 3.1.3. Evidenced in Table 4-1,
the relative intensity of the Raman D-peak increases with respect to the G-peak as growth
temperature decreases. This represents an increase in defectiveness at lower growth temperature,
which corresponds to a decrease in the mean graphene crystallite size, La. Using the relation
established by Cançado et al. [105], we estimate La to be 162 and 100 nm for growth at 1000
(modified process) and 850 °C, respectively. As graphene domain boundaries serve as scattering
centers and reduce carrier mobility, this demonstrates the necessity for high growth temperatures
to ensure high quality graphene for device applications, which agrees with other work [85].
Scanning electron microscopy (Figure 4-2) indicates typical copper terracing and grain
boundaries, and the characteristic graphene wrinkles that arise from thermal expansion mismatch
between the graphene and copper [71].
63
Figure 4-1: Raman spectra of graphene synthesized at 850, 925, and 1000 °C using a on freestanding
copper foils. Graphene grown at low temperature shows a higher D/G ratio, indicating a higher level of
defects.
Table 4-1: Post-growth Raman characterization of graphene on freestanding copper foils. Increased growth
temperature resulted in a lower D/G ratio and a stronger, narrower 2D peak, indicative of higher quality graphene. This is quantified by an increase of ~35% in the defect-free graphene crystallite size, La. The use
of a slightly longer growth with a lower methane partial pressure resulted in a further increase of ~20% in
La [105].
Growth D/G
ratio
La
(nm)
2D/G
ratio
2D peak width
(rel. cm-1
)
850 °C 0.137 99.6 1.78 41.9
925 °C 0.121 112 2.13 40.4
1000 °C 0.101 135 2.84 35.8
1000 °C, modified growth 0.084 162 3.39 35.2
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Figure 4-2: Scanning electron microscope image of foil-grown graphene samples showing copper step
terraces and grain boundaries as well as wrinkles in the graphene film that result from thermal mismatch.
The observed improvements in crystalline quality at elevated temperatures and with the
more dilute precursor mix are readily explained by typical CVD kinetics. As growth temperature
increases, the surface mobility of an adsorbed carbon atom increases. This increases the
likelihood of that atom diffusing laterally until it meets an existing crystallite, resulting in
crystallite growth as opposed to formation of new crystallites. Similarly, a reduction in the
methane partial pressure as used in the modified growth process would reduce the rate at which
new carbon atoms are adsorbed on the surface of the copper foil, reducing the likelihood of
multiple adatoms forming a new crystallite instead of growing existing crystallites [87,132].
Thus, an ideal growth process would combine a sufficiently high growth temperature with
relatively low carbon-containing precursor concentration for formation of few crystallites that
grow together to form the continuous graphene film. It should also be noted that the calculation of
crystallite size using Equation 4-1 likely underestimates the actual crystallite size of these
samples, as the D-peak intensity is near the noise floor of the Raman characterization system.
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4.2 Diffusion Barrier Studies
4.2.1 Growth on Copper Thin Films
Utilization of thin Cu films on SiO2/Si substrates following graphene growth reveals
marked differences from foil-grown material. Evident from Figure 4-3, average copper grain size
in thin films ranges from 5-50 μm, compared to 100 μm to several millimeters in freestanding
copper foils. Additionally, scanning electron micrographs of graphene grown on Cu/SiO2/Si
samples (Figure 4-4a) show the presence of unexpected surface particle formation. These
particles were identified by Auger electron spectroscopy (AES) to be silicon- and oxygen-rich
with estimated concentrations of 11 and 13 at%, respectively (Figure 4-4b), providing the first
direct evidence that the Cu/SiO2 material system may be highly unstable at typical graphene
synthesis conditions. Furthermore, the lack of Cu-Si-O surface particles on foil-grown graphene
(Figure 4-2) indicates that the formation of these particulates is directly related to the presence of
the SiO2/Si substrate, rather than growth system contamination. Transmission electron
microscopy (TEM) imaging of post-growth samples indicates considerable interdiffusion and
ternary phase formation at the Cu-SiO2 interface (Figure 4-5), confirming that the Cu/SiO2/Si
material system is not stable under typical conditions for graphene synthesis from a methane
precursor. As a result, there is a need to evaluate alternate material systems for graphene
synthesis.
66
Figure 4-3: Optical microscope images of post-growth graphene samples on thin copper films (a) and
freestanding copper foils (b).
Figure 4-4: Scanning electron microscopy of graphene grown on copper thin films reveals the presence of
unexpected particle formations (a). These formations are identified by AES to be silicon-and oxygen-rich
(b).
Figure 4-5: TEM image of the copper-SiO2 interface following graphene synthesis indicating interdiffusion
of up to 200 nm and significant ternary phase formation.
67
4.2.2 Addition of Metal and Insulating Diffusion Barriers
Early barrier layer investigations centered on the addition of a thin nickel layer between
the copper film and SiO2 substrate, similar to Levendorf et al [93]. Post-growth TEM images for
various nickel layer thicknesses are shown in (Figure 4-6). Investigation of nickel interlayer
thickness from 5nm to 50 nm indicates that introduction of Ni significantly reduces Cu-SiO2
interdiffusion, but it does not eliminate it. Energy dispersive spectroscopy (EDS) indicates a lack
of Ni at the Cu/SiO2 interface for 5nm films, suggesting the nickel has diffused into the copper
layer during growth - a result of the miscibility of copper and nickel [133]. Additionally, rough
intermetallic Cu-Ni-Si-O and Cu-Si-O interfacial layers are present in each sample. Thus, even if
the Ni interlayer minimizes the interdiffusion of Cu and SiO2, the presence of a rough
intermetallic layer will result in: 1) residual intermetallic compounds in contact with graphene,
and 2) significant substrate surface roughness following transfer-free metal etching. While further
increasing the nickel layer thickness may provide additional reduction in interdiffusion and
improved interfacial roughness, it will likely not completely remove intermetallic formation, and
significant alloying of the copper film will increase carbon solubility, resulting in multilayer
graphene typical of synthesis on nickel [78]. Therefore, it is advantageous to explore other,
potentially more robust diffusion barrier materials for minimizing interdiffusion at the Cu/SiO2
interface.
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Figure 4-6: The addition of a sacrificial nickel diffusion barrier layer can substantially reduce copper–
silicon interdiffusion during graphene synthesis. Post-growth TEM images of the copper–substrate
interface region for nickel barrier thicknesses of (a) 5 nm, (b) 10 nm, (c) 20 nm and (d) 50 nm showing
reduction in thickness of interdiffusion with increasing nickel thickness.
In addition to changing the interface behavior during growth, the utilization of traditional
and non-traditional diffusion barrier layers significantly impacts the quality of synthesized
graphene. Figure 4-7 shows a comparison of the post-growth Raman spectral signatures of the
various Cu/X/SiO2/Si and Cu/Y/Si sample configurations (X=Ni, Cr, or W; Y=SiNx, Al2O3, or
HfO2). Evident from Raman, a fraction of configurations produce structurally similar graphene to
that of the baseline Cu/SiO2/Si sample, while others exhibit markedly different signatures. This
indicates that not only the copper surface, but also the underlying substrate plays an important
role in the chemical vapor deposition of graphene. It is also clear from Raman that samples
without a diffusion barrier at the Cu/SiO2 interface provide a means to grow high quality
graphene, consisting predominantly of monolayer graphene (narrow, symmetric 2D peak and
I2D/IG ≈ 1.4) with low defect density (ID/IG ≈ 0.1, La ≈ 138 nm) – comparable to foil-grown
69
material discussed in Section 4.1. Similar results are found with the Ni and HfO2 barrier layers.
However, evaluation of other metal barrier layers provides evidence that this is not always the
case. Raman characterization indicates that tungsten and chromium barrier samples produce more
defective graphene (ID/IG > 0.2, La < 65 nm). Additionally, the Al2O3 and SiNx barrier samples
yield highly defective graphene (ID/IG > 0.3, La < 45 nm, weak 2D peak), precluding their use in
device applications. Table 4-2 provides a summary of ID/IG and I2D/IG for these spectra.
Figure 4-7: The addition of metallic and insulating barrier layers drastically affects the quality of
synthesized graphene. A comparison of Raman spectral signals of various sample configurations shows
considerable variation in defect level and estimated thickness for different barrier layers.
Table 4-2: Raman peak intensity ratios for spectra shown in Figure 4-7.
ID/IG I2D/IG
Cu foil 0.053 2.72 No barrier 0.096 1.39
Ni 0.110 1.77
Cr 0.199 0.99
W 0.226 2.09 Si3N4 0.362 0.42
Al2O3 0.248 0.57
HfO2 0.225 2.53
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The source of defect and thickness variation is evident when characterizing the material
systems using SEM and TEM. Utilization of W and Cr barrier layers results in poor Cu film
morphology (Figure 4-8a and b), small Cu grain size, and significant Cu-Si-O surface particulate
formation - which impacts graphene nucleation and growth. Significant variation in the Raman
ID/IG and I2D/IG in metal-barrier samples is likely due to high levels of defects and impurity atoms
at the Cu surface that serve as non-uniform nucleation sites. Furthermore, TEM investigations of
the insulating barrier samples indicate poor barrier behavior, resulting in Cu/Si interdiffusion and
the formation of copper-silicon intermetallics. While the Al2O3 barrier sample (Figure 4-8c)
shows sharp Cu-Al2O3 and Al2O3-Si interfaces without the formation of additional phases, copper
is identified by EDS in the Al2O3 barrier layer and silicon substrate. Thus, even though the Al2O3
layer remains intact, high levels of Cu atoms (3-5 at%) are able to diffuse through it into other
regions of the sample. HfO2 and SiNx barrier samples (Figure 4-8d and e), also show the
presence of copper-silicon intermetallic precipitates at the copper-dielectric and dielectric-
substrate interfaces, again showing their inability to prevent interdiffusion between the copper
film and underlying substrate.
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Figure 4-8: SEM and TEM imaging of post-growth barrier layer samples show poor morphology and
interfacial quality. Post-growth SEM images of (a) tungsten and (b) chromium barrier layer samples show
that the barrier layer strongly influences copper film morphology, which then affects graphene synthesis.
Dielectric layers exhibit poor barrier behavior, as shown by post-growth TEM images of Cu/dielectric/Si
interface region for (c) Al2O3, (d) HfO2 and (e) SiNx samples.
The poor barrier performance of ALD dielectrics can easily be explained by examining
the crystallinity of the films following growth. While films deposited by atomic layer deposition
are typically amorphous, electron diffraction patterns obtained during TEM imaging of the Al2O3
and HfO2 layers indicate that these films undergo crystallization during the graphene growth
process. Instead of being strong diffusion barriers, the polycrystalline oxides exhibit a high
density of grain boundaries along which diffusion can take place. Thus, even though lattice
diffusion may be negligible in these materials, their polycrystalline nature provides low barrier
paths for Cu-Si interdiffusion. A barrier layer with a different crystal structure, such as an
epitaxially grown film, may suppress diffusion more effectively than the films evaluated in this
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study. While electron diffraction suggests that the SiNx layer remains amorphous through the
growth process, previous research suggests that defects resulting from Si-H and N-H bonds create
paths along which copper atoms can readily diffuse [134]. In addition to poor diffusion barrier
performance, SiNx barrier samples exhibit voiding and copper delamination following growth.
This behavior is likely due to evolution of hydrogen gas from the film at elevated temperatures,
which can result in a significant volume change in the film as well as localized voids. Void
formation disrupts graphene synthesis and results in discontinuous graphene, making this material
system unsuitable for device manufacturing.
4.2.3 Graphene on Sapphire
Eliminating the presence of silicon by replacing the substrate with single crystal Al2O3
(sapphire, c-plane) provides a robust material system for graphene synthesis on thin film copper.
The structural quality of graphene grown on Cu/Sapphire, as measured by Raman spectroscopy,
is comparable to the highest quality grown on bulk Cu foils (Figure 4-9a), with ID/IG ≤ 0.1 and a
narrow, symmetric 2D peak approximately 3x the intensity of the G peak. Furthermore, TEM
investigation of the interface (Figure 4-9b) indicates an abrupt interface with no evidence of
interdiffusion, which is confirmed by EDS. Finally, SEM imaging of the sample surface (Figure
4-9c) indicates a pristine surface, free of Cu-Si-O formations found in SiO2/Si substrate samples.
Thus, the copper on sapphire system is both thermally stable and adequate for synthesis of high-
quality graphene. Furthermore, the use of sapphire substrates in the LED market has led to heavy
focus on the scaling of that material system – sapphire substrates are now commercially available
in wafer diameters of up to 200 mm, which is highly attractive for volume manufacturing.
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Figure 4-9: (a) Post-growth Raman spectrum of Cu/sapphire sample indicative of high quality, single-layer
graphene. (b) Post-growth TEM of copper/sapphire interface region shows a pristine interface free of
interdiffusion or formation of intermetallics. (c) SEM imaging of Cu/sapphire sample shows typical copper
grain structure and absence of Cu-Si-O particle formation.
4.2.4 Broader Impact of Diffusion Barriers and Graphene
Since the time that this work was performed, there has been an increased level of interest
in the area of diffusion barriers related to graphene. Interestingly, there have been two somewhat
opposite foci of research – one focusing on diffusion barriers for improving synthesis of graphene
and other two-dimensional materials on a transition metal-coated silicon substrate (as was
examined here), and one focusing on the use of the graphene itself as a diffusion barrier in other
aspects of microelectronics fabrication.
In the context of diffusion barriers for 2D material synthesis on transition metals, most
recent work has fallen along similar lines to this work. That is, it has sought to avoid metal-
silicon interdiffusion by one of the same two methods investigated here: 1) Adding a diffusion
barrier between the metal film and silicon substrate, or 2) by using alternative substrates such as
quartz or sapphire. One particularly interesting paper investigated the use of such a diffusion
barrier in the growth of single-crystal hexagonal boron nitride (h-BN) on a rhodium-coated
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silicon substrate [135]. But rather than the mostly polycrystalline films investigated here, Hemmi
et al. utilized a yttria-stabilized zirconia (YSZ) buffer layer between the Si(111) wafer and the
crystalline rhodium film. The success of the YSZ barrier at preventing inter-diffusion of the
rhodium film and silicon substrate reflects the importance of the crystalline structure of the
diffusion barrier. That is, a polycrystalline film is often less effective as a diffusion barrier than
single-crystal or amorphous films, due to the easier paths for diffusion provided by the grain
boundaries.
Another paper of note focused almost entirely on graphene growth on an epitaxial
Cu(111)/Al2O3(0001) substrate [136]. Part of the motivation for this substrate choice was again to
avoid the pitfalls of copper-silicon interdiffusion during graphene synthesis. But this paper was
somewhat unique in that it utilized a single-crystal copper film that was epitaxially aligned to the
sapphire substrate, rather than the polycrystalline films of most other work. The high quality films
produced by these methods speak to the potential for the copper-sapphire system in volume
graphene synthesis, as the materials and techniques used here would all be considered standard
processes within modern semiconductor manufacturing. If combined with a transfer-free
graphene fabrication technique, the copper-sapphire system may be an extremely promising path
towards industrial fabrication of graphene devices [93,124,137].
On the opposite side of the coin, graphene has itself been recently shown to be an
effective diffusion barrier for certain key microelectronics applications [138]. It is perhaps not a
coincidence that the same material system that proved problematic for graphene growth (copper-
silicon) is also one in which graphene has shown great promise as the actual diffusion barrier
[139]. The copper-silicon system is an extremely important application of diffusion barriers;
virtually all modern VLSI applications utilize copper as the main interconnect metal, and copper
is a known poison to silicon devices. Since the first introduction of copper interconnects in the
late 1990s, the silicon industry has used sputtered titanium, tantalum, or their respective nitrides
(TiN, TaN) as diffusion barriers below the plated copper interconnects. But continued device
75
scaling necessitates reducing the diffusion barrier down to only a few nanometers thick, at which
point these films both lose their effectiveness as diffusion barriers and contribute an undesirable
amount of interfacial resistance due to the relatively high fraction of grain boundaries [139].
The fact that graphene is by definition at most a few atomic monolayers inherently makes
it an attractive candidate for ultrathin diffusion barrier applications. Recent work by Zhao et al.
demonstrated that the “critical thickness” of graphene – for which copper diffusion through it – is
roughly 5x thinner than the critical thickness for a typical TaN barrier [140]. But similar to what
is observed in traditional three-dimensional materials, the crystalline quality of the graphene film
plays an important role in its utility as a diffusion barrier. Hong et al. demonstrated that even a
single monolayer of graphene was robust at preventing copper silicide formation during annealing
at temperatures up to 900 °C, but only when the graphene domain size was considered “large”
(>6 um) [139]. For films with graphene crystallite sizes of 1-3 um, copper silicide XRD peaks
were observed beginning at 800 °C (see Figure 4-10). It should be noted that this is still a
tremendous improvement over the system without a diffusion barrier, where copper silicide forms
as low as 300 °C. But it reinforces the importance of grain size and crystalline quality to the
performance of a diffusion barrier, even when it is a low-dimensional material like graphene.
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Figure 4-10: XRD spectra of copper-graphene-silicon films after various anneals, showing copper silicide
formation on no barrier sample and small-grain graphene sample at 300 and 800 °C, respectively. Large
grain single-layer graphene and multi-layer graphene film were robust against copper silicide formation up
to 900 °C. Adapted from reference [139].
While a majority of research into graphene as a diffusion barrier has focused on the
copper-silicon system, graphene diffusion barriers have also been evaluated for several other
applications, including ohmic contacts for a variety of devices [138,141,142]. In these
applications, the diffusion barrier serves to prevent undesirable reactions amongst often 4- and 5-
metal systems, rather than the simple copper-silicon reaction described above. In one interesting
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example, a liquid conductor composed of gallium, indium, and tin – colloquially termed
“galinstan” – is described as a potential replacement for mercury in applications where a
spreadable conductor is desired. But this complex alloy readily attacks many common metals,
including nickel, aluminum, and even gold. Ahlberg et al. demonstrated that a single layer
graphene film can completely suppress many of these undesirable reactions, allowing for use of
galinstan along with conventional metals in circuits requiring the formation of a liquid electrical
contact [142].
4.3 Transfer Process Optimization
4.3.1 Copper etchant study
Most early work on copper-mediated CVD graphene utilized iron-based etchants (FeCl3,
Fe(NO3)3) during the graphene layer transfer process [81,125]. However, later work also
demonstrated graphene layer transfer using ammonium persulfate [86] and nitric acid [126]. This
work sought to compare these etchants and their viability in a repeatable graphene transfer
process.
The baseline transfer process, utilizing a ferric chloride-based etchant, produced
continuous graphene films free of major defects, as shown in Figure 4-11. This etchant was
found to be sufficiently aggressive to etch the 25 µm-thick copper foils in ~30 minutes, yet gentle
enough to avoid physically or chemically damaging the graphene films. Thus, the ferric chloride-
based solution formed the baseline method for layer transfer against which alternative methods
could be compared for cleanliness and ease of processing.
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Figure 4-11: SEM image of graphene film transferred to SiO2 showing an intact film, free of cracks,
pinholes, or other major defects.
Etching using ammonium persulfate, on the other hand, was quickly found to be
insufficient for high-quality graphene layer transfer. Post-transfer optical imaging showed a high
density of circular defects, believed to be regions of residual un-etched copper (Figure 4-12).
One potential explanation for these defects is that they are the result of gas bubbles formed during
the etch process. Because the reaction between ammonium persulfate and copper produces
hydrogen gas, small H2 bubbles form and are trapped beneath the graphene film in the etchant
bath. In the absence of an agitated bath (which would risk damaging the delicate graphene), these
bubbles remain at the interface between the sample and etchant solution, potentially blocking the
etch process from completion.
Multi-layer domains
Graphene wrinkles
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Figure 4-12: Bright-field and dark-field images of graphene transferred to SiO2 using an ammonium
persulfate-based transfer process. Large circular defects are believed to be residual un-etched copper.
As with ammonium persulfate, etching with nitric acid was also found to result in
significant formation of bubbles during copper etching. However, the bubbling action using nitric
acid as the etchant was far more aggressive – etchant solutions of 5% nitric acid or greater
resulted in macro-scale damage to the graphene films from vigorous bubble formation (Figure
4-13). While a lower concentration etchant was found to reduce the formation of bubbles,
concentrations of less than 5% HNO3 were found to take several days to fully etch a 25 µm-thick
copper foil. Those films were found to be much more likely to crack during transfer to subsequent
rinse baths, indicating the PMMA films were likely being embrittled by the lengthy nitric acid
exposure.
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Figure 4-13: SEM image of graphene film on SiO2/Si following nitric acid-based layer transfer process.
Large holes formed in the graphene film as a result of the vigorous bubbling during the reaction between
nitric acid and copper substrate.
Ultimately, it was determined that a ferric chloride-based transfer process was the best
solution for repeatable, high-quality graphene layer transfers. This was the only solution tested
that was able to quickly etch the copper substrates without introducing major defects into the
graphene films. Post-transfer Raman spectroscopy of transferred films (Figure 4-14) showed high
signal intensity with low ID/IG, indicating that the films remain high quality following the layer
transfer.
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Figure 4-14: Post-transfer Raman spectra of graphene on SiO2/Si substrate showing strong signal intensity,
high crystalline quality, and no appreciable background signal from contaminants.
4.3.2 Removal of Residual Iron Contamination
One drawback to the use of a ferric chloride-based copper etchant is the formation of iron
contamination at the graphene-substrate interface [127]. Post-transfer XPS characterization of
graphene films on SiO2/Si substrates (Figure 4-15) confirms the presence of a small fraction of
residual iron atoms, at a concentration of <1 at.%. These impurities would likely introduce
significant charge scattering in graphene devices; thus, this contamination must be eliminated for
optimal device performance.
D
G
2D
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Figure 4-15: XPS spectrum from graphene on SiO2 showing significant residual iron contamination from
the layer transfer process.
Previous work showed that a modified version of the RCA (Radio Corporation of
America) clean, was effective at removing this metal contamination prior to deposition of the
graphene film onto a final substrate [127]. This clean consisted of dilute (20:1:1) room
temperature baths of H2O/HCl/H2O2 and H2O/NH4OH/H2O2; by comparison, the standard RCA
clean consists of more concentrated baths (typically 5:1:1) held at ~80 °C.
In this work, an even simpler clean was evaluated and adopted – following removal of a
PMMA/graphene film from the etchant solution, it was first placed into a deionized water rinse
bath for 15 minutes, then transferred to a 10% HCl bath for 15 minutes to remove metal
contamination. The sample was then transferred to a second DI water rinse bath for an additional
15 minutes before finally being withdrawn onto the target substrate for drying and removal of the
PMMA support layer. As shown in Figure 4-16, XPS characterization of the films following
layer transfer did not identify the presence of any metal contaminants, indicating that the HCl
bath was effective at removing the residual iron from the sample.
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Figure 4-16: XPS spectrum from graphene on SiO2 with 10% HCl clean during layer transfer. It should be
noted that the fluorine peaks observed were believed to occur due to a fluorine-based alignment etch
performed on this sample. Although they occur in the same energy region as the iron peaks in Figure 4-15,
their signature is significantly different; no iron signal was detected on this sample.
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Chapter 5: Device Fabrication and Electrical Characterization
5.1 Ohmic Contact Development
Similar to previous work on epitaxial graphene [114], this work sought to evaluate the
influence of pre-metallization oxygen plasma treatment and post-metallization anneals on ohmic
contact formation to graphene. However, to limit sample fabrication needs for this work, the
effects of pre-ohmic plasma treatment were evaluated solely using Raman spectroscopy, while
the effects of post-metallization anneals were evaluated by use of contact resistance
measurements (Section 3.5.1). The ohmic metal stack described in Section 3.4.2 (10 nm Ti, 100
nm Au) was used for all samples described in this section.
5.1.1 Effects of Pre-ohmic Plasma
Oxygen plasma treatments prior to metallization are commonplace in semiconductor
manufacturing, being critical for removal of photoresist residues and other organics [143]. In
previous work, Robinson et al. demonstrated the benefits of oxygen plasma descum on the ohmic
contact resistance to epitaxial graphene, as well as establishing an approximate optimum
condition in which contact resistance would be minimized [114]. This work similarly sought to
minimize ohmic contact resistance by optimizing the conditions of the pre-metallization oxygen
plasma descum. For the sake of simplicity of the experiment, the efficacy of various descum
processes was assessed on the basis of Raman spectroscopy alone, rather than by fully fabricating
devices and performing electrical contact resistance measurements with each experimental
condition. This work evaluated a broad array of plasma treatments, including some that ultimately
showed no appreciable ability to remove organic material from the open areas. Thus, it was not
practical to characterize all experimental conditions by electrical methods.
The first set of descum experiments began by attempting to replicate the results of
previous work on epitaxial graphene [114]. That is, samples were fabricated using an identical
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combination of plasma descum, metallization, and anneal, then electrically probed to assess
ohmic contact resistance. Interestingly, the first samples tested with this processing showed
extremely variable results, with many devices appearing to be virtually an open circuit. On closer
examination, it appears that the same plasma treatment was effectively more aggressive on CVD
graphene than for epitaxial graphene. This can be seen in the comparison in Figure 5-1, with the
post-descum spectrum showing significant reduction in the overall signal strength, increase in
D/G ratio, and near complete elimination of the 2D peak. This spectrum reflects an extremely
disordered film, to the extent that it may not even be fully continuous and can only loosely be
described as graphene. Thus, it is not surprising that the resulting ohmic contacts were of
extremely poor quality.
Figure 5-1: Comparison of Raman spectrum of CVD graphene before and after plasma descum using
identical conditions to that of previous work by Robinson et al [114].
Given the previous result, it was then decided to evaluate two main approaches of plasma
descum – one that attempted to find a more suitable combination of process conditions while
using the same basic gas chemistry (O2+He), and another that used a completely different
D G
2D
D+G
Initial Post-Descum
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chemistry. While a fairly wide variety of gases can be used as reactants for plasma descum
processes, only C2F6 was available on the same tool as previously used (in addition to the
aforementioned O2 and He). Thus, a C2F6+He plasma was chosen as the main alternate option, in
order to allow for a direct comparison against the baseline oxygen-based chemistry.
A very basic plasma stability study was performed first, as a means of identifying a
suitable process window for evaluation. The criteria for this study were extremely limited – the
goal was to identify a suitable gas chemistry with which a plasma could be struck and maintained
for at least 1 minute using an RF power of 100W and pressures of both 400 mTorr and 1000
mTorr. These pressures were chosen as reasonable upper and lower bounds for the particular
plasma tool, allowing for some modulation of the relative degree of ion bombardment while still
staying within the normal operating ranges for gas flow and pressure control of the hardware. The
baseline oxygen chemistry of 75% O2 and 25% He was found to be suitable across that window
and was maintained for subsequent studies. In the case of the C2F6 study, it was found that that
reactant gas required a significantly greater amount of helium dilution in order to ignite and
remain stable, to the extent that the helium actually formed a majority of the gas flow. The final
chemistry chosen for this part of the study was 40% C2F6 and 60% He.
Raman spectra for a variety of oxygen-based plasma treatments are shown below.
Samples were characterized prior and subsequent to repeated plasma treatments at either 400 or
1000 mTorr. In both cases, the graphene quality decreases with successive treatments, as
evidenced first by a sizeable increase in the relative D-peak intensity, and second by the
broadening and eventual disappearance of the 2D peak. This transition occurs much more slowly
in the case of the 1000 mTorr process, with the 30-second sample roughly equivalent to the 15-
second sample at 400 mTorr. This is not a particularly surprising result; for the typical RF plasma
system, the degrees of plasma ionization and gas dissociation (and thus the density of free
radicals available to participate in reactions) decline with increased pressure due to the reduced
mean free path of gas molecules and reduced recombination time. Thus, the relative fluxes of
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both oxygen ions and free radicals are lower at the higher pressure, reducing the rate of the
reaction.
Figure 5-2: Raman spectra as a function of exposure to an O2/He plasma
A similar study was performed using the previously described C2F6 plasma, with the
Raman spectra shown below. In stark contrast to the oxygen-based plasma, these treatments
showed little to no change in the Raman spectra, indicating that this plasma was negligibly
attacking the graphene. Even when extending the process time to 60 seconds (compared to a
maximum time of 45 seconds in the oxygen study), there was no discernible change in the Raman
spectrum of the graphene film. This was a very promising result, as it suggested the possibility of
a recipe that allowed for some degree of selectivity in removal of organic residues from the
graphene surface without appreciably degrading the graphene itself. However, attempts to
fabricate real devices using this descum process were wholly unsuccessful. All samples that
received only a C2F6 plasma prior to metallization showed severe lifting of the ohmic
metallization after liftoff (see image below), which is the same signature as is observed in the
30s
15s
Initial
45s
400 mTorr 1000 mTorr
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absence of any descum process prior to evaporation. This suggests that the C2F6 process is not
consuming organic surface contaminants to any significant extent, precluding its use as a pre-
ohmic descum chemistry.
Figure 5-3: Raman spectra as a function of exposure to a C2F6/He plasma
Figure 5-4: Optical microscope image of sample processed through ohmic metallization using C2F6 plasma
showing severe metal lifting
30s
15s
Initial
60s
400 mTorr 1000 mTorr
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Given the above results, it was decided to use the 1000 mTorr oxygen-based descum
recipe with a duration of 30 seconds as the pre-ohmic plasma treatment for all subsequent device
fabrication. This recipe produced a Raman signature that very closely matched the optimum
condition identified in previous work on epitaxial graphene, had a reasonably short process time,
and stayed within the normal operating parameters of the tool in question. It should be noted that
the study performed here was only a small fraction of a much wider variety of descum treatments
that could be evaluated given the right equipment and gas availability. For example, modern
semiconductor manufacturing facilities often employ the use of gases such as hydrogen, nitrogen,
or even water vapor as reactants in ash and descum applications, allowing them to tailor the
plasma chemistry to selectively target removal of residues and surface contamination while
avoiding attack of their devices. Similarly, the equipment in these facilities often have unique
configurations for generation, confinement, and transport of only neutral reactive species to the
wafer surface without any ion bombardment; one such configuration is referred to as a
“downstream microwave” plasma source. This type of configuration might allow for generation
of significant etch selectivity between the undesired photoresist residues and the graphene device
material, even though they are both organic in nature. While these techniques were not available
for testing as part of this work, they may be useful for improved ohmic contact performance and
manufacturability in future integration of graphene into production devices.
5.1.2 Effects of Contact Anneals
In addition to pre-deposition plasma treatments, previous work also emphasized the
importance of post-deposition annealing on the realized ohmic contact resistance of graphene
devices [114]. Using the down-selected descum process described in Section 5.1.1, samples were
fabricated through Ti/Au metal deposition and liftoff, then tested before and after a series of
anneals of increasing temperature. Figure 5-5 shows the extracted contact resistance, Rc, as a
function of anneal temperature. Interestingly, the data shows an apparent increase in Rc upon
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initial anneal, rising from ~2.0 Ω-mm in the as-deposited state to 2.6 Ω-mm after a 250 °C
anneal. Contact resistance then decreased monotonically with subsequent anneal steps, reaching a
mean value of ~1.2 Ω-mm at the highest anneal temperature. This behavior is quite unexpected,
as other previous studies of graphene ohmic contacts do not describe an increase in contact
resistance from the as-deposited state after annealing, irrespective of condition [114,144].
Figure 5-5: Contact resistance of CVD graphene samples as a function of post-deposition annealing.
One potential explanation for the observed contact resistance behavior becomes evident
upon examining the effect of annealing on the graphene itself. The contact resistance Rc is not a
metric of the metal-graphene interface alone – that is, it is a function of both the junction and the
semiconductor material beneath the junction, as the transfer length of the junction will vary
according to the sheet resistivity of the underlying semiconductor. As can be seen in Figure 5-6,
the graphene sheet resistivity Rsh does change appreciably as a result of the annealing treatments.
As-deposited values of Rsh range from 400-800 Ω/sq, increasing by approximately 60% after the
initial anneal at 250 °C. The mean value of Rsh peaks at 920 Ω/sq following the 300 °C anneal,
before dropping down to 670 Ω/sq after the highest temperature anneals.
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Figure 5-6: Graphene sheet resistance as a function of anneals following ohmic metallization.
It should be emphasized that the trend in graphene sheet resistance shown above
describes the condition of the graphene between contact pads, not the graphene beneath the
contacts. Nonetheless, this trend does show that significant changes in graphene sheet resistance
can occur as a result of ohmic contact anneals, which could explain the observed increase in
contact resistance if similar shifts are observed in the graphene beneath the metal contacts.
Unfortunately, the graphene sheet resistance beneath the contact pads cannot be determined
directly from the transfer length method. However, more complex contact structures and
measurement techniques could be employed in the future to independently extract the sheet
resistance beneath the contacts and account for differences from behavior in the region between
contact pads.
In addition to the contact resistance Rc, the transfer length method allows for the
calculation of the specific contact resistance, ρc, which serves as a metric of the contact interface
itself. The trend in ρc as a function of annealing is shown in Figure 5-7. This behavior is much
more aligned with expectations – contact resistance decreases progressively with each anneal,
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dropping by close to an order of magnitude from the as-deposited condition. The best devices
annealed at 400 °C reached a value of ~7x10-6 Ω-cm. Interestingly, the spread in contact
resistance actually increased as a function of annealing. This is not necessarily surprising – the
layer transfer process involved in CVD graphene fabrication contains a component of variability
that is not present in epitaxial device fabrication, and it is entirely possible that residual
contaminants and/or damage to the graphene layer vary in ways that interact directly with the
mechanisms of contact annealing.
Figure 5-7: Specific contact resistivity as a function of post-deposition anneals
5.1.3 Contact Resistance in Context
On the whole, the ohmic contact results described above are not exemplary; performance
is 1-2 orders of magnitude worse than the best that was achieved previously on epitaxial graphene
(7.5x10-8 Ω-cm2) [114]. However, this study was conducted over a lower temperature range than
previous work, and was unable to continue to higher temperatures due to sample degradation
from repeated probing. It is reasonable to expect further decrease in contact resistance with
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anneals of 450-500 °C that would bring these results closer to the best reported results for
epitaxial graphene.
Interestingly, the amount of new ohmic contact work on graphene over the last several
years has been limited. This is not necessarily surprising, given the diminishing return on
investment for further research as better results are achieved. But another factor is equally at play
– the pivot away from graphene and towards other low-dimensional materials among many
academic research groups. These low dimensional materials are predominantly transition metal
dichalcogenides (TMDs) such as MoS2, MoSe2, and WS2, which are structurally similar to
graphene, but possess a band gap and are more attractive than graphene for a number of device
applications [144]. As research in these materials has increased, additional lessons have been
learned that can also serve to inform ohmic contacts to graphene as well.
One of the most straightforward results for ohmic contacts to TMDs was published by
English et al. in 2016 [145]. This paper demonstrated a significant reduction in ohmic contact
resistance (approximately a factor of 3) by maintaining ultrahigh vacuum (~10-9 Torr) during the
ohmic metal evaporation, rather than the ~10-6 Torr that is the typical operating range for most
electron beam evaporators. These results are particularly significant because they demonstrated
specific contact resitivities in the 10-7 Ω-cm2 range without relying on doping effects or work
function engineering. Those techniques have been extensively studied both for graphene and
TMDs, but often present difficulties when devices are aggressively scaled, as lateral doping
effects into the channel region can induce threshold voltage shifts or otherwise impact the
transport behavior of the device outside of the ohmic contacts themselves [144]. This presents a
fairly positive outlook for the “ideal” ohmic contact to graphene – that a properly optimized pre-
ohmic plasma treatment combined with an ultrahigh vacuum deposition of the ohmic
metallization would produce as clean an interface as possible. When combined with an optimized
post-deposition anneal, contact resistances even below current state of the art could be achieved,
which would be suitable for even very aggressively scaled device performance.
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5.2 Transport Studies on Various Substrates
The final component of this work was a study of the transport behavior of graphene films
when integrated with various dielectric materials. An exhaustive study would evaluate a broad
array of both substrate materials and gate dielectrics, as both would be expected to influence
scattering in a graphene device. However, the scope of this work was limited to evaluation of a
select set of substrate materials only. This allowed for characterization of the influence on
transport behavior with a limited process flow that only required processing up through ohmic
contact formation. This also avoided the added influence of a top dielectric film on the scattering
behavior in the graphene, allowing for more straightforward analysis of the influence of the
substrate materials. Processing was identical for all samples with the exception of the target
substrate during the layer transfer (see Section 3.4 for details). Two samples each were
transferred to oxidized silicon, single-crystal sapphire, and epitaxial GaN-on-sapphire substrates.
After ohmic contact formation, all samples were loaded into a vacuum Hall mobility
measurement system and outgassed under vacuum at 400K for one hour prior to execution of
temperature-dependent Hall measurements.
Figure 5-8 shows the raw mobility data as a function of temperature for each sample. At
low temperatures, mobilities ranged from ~1200-2100 cm2 V-1 s-1, with the two GaN samples
considerably higher than the SiO2 and Al2O3 samples. Mobility is relatively flat versus
temperature up to ~200K, after which it begins to fall off. The falloff is considerably more
pronounced for the GaN samples than the other two substrates – the best GaN sample
experienced a >20% drop in mobility over this temperature range, whereas the SiO2 samples
dropped only ~11%. The temperature-dependence of mobility is relatively weak compared to a
majority published literature. For example, simulations from Konar et al. show approximately a
50% reduction in mobility from 5-300K for graphene in contact with an Al2O3 gate dielectric
[48]. However, it should be noted that these simulations also project much higher mobilities
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overall; as subsequent modeling will show, this is likely due to the considerably higher level of
charged impurities in the transferred CVD graphene in this work than is typically simulated in
literature for exfoliated graphene. The overall mobility and temperature-dependence trend in this
work are fairly comparable to recent work on epitaxial graphene, however, indicating that the
observed data are reasonable and in line with defectivity levels observed for other large-area
synthesis methods [32,146].
Figure 5-8: Measured Hall mobility as a function of temperature for two samples each on SiO2, Al2O3, and
GaN substrates.
As described in Section 3.6, the temperature-dependent mobility behavior can be
understood as the combination of four separate scattering mechanisms: Intrinsic graphene
and gate contact formation. Finally, electrical transport behavior of graphene films on various
substrates was examined in order to better understand scattering mechanisms in graphene. This
work hopes to serve as a blueprint for future work on CVD graphene and other similar low-
dimensional materials, including transition metal dichalcogenides such as MoS2.
6.1 Graphene Synthesis
The synthesis of graphene films on copper substrates by chemical vapor deposition
consists of several stages: 1) Substrate heating and pre-annealing, 2) Graphene crystallite
nucleation, and 3) Crystallite growth to form a continuous graphene film. This thesis evaluated
103
and optimized growth processes for use of both freestanding copper foils and thin copper films on
insulating substrates as the basis for graphene synthesis.
Optimization of graphene synthesis on freestanding copper foils separately evaluated the
influence of growth temperature and the composition of the precursor gas on the quality of
synthesized graphene. Growth temperature was varied from 850-1000 °C, with the resulting
Raman spectra demonstrating a clear reduction in defect density with increasing temperature.
Subsequently, growth quality was compared between the baseline methane-rich precursor gas and
a more dilute precursor mix with the addition of argon, with a further improvement in crystalline
quality shown with the modified process. This aligns with contemporary literature indicating that
the highest quality CVD graphene is produced with a high-temperature, slow growth using a
dilute hydrocarbon precursor in a reducing environment.
Study of synthesis of graphene on thin copper films on insulating substrates focused on
solving a different problem – the propensity for interreaction between the copper film and an
underlying silicon substrate at elevated growth temperatures. This study evaluated the efficacy of
a variety of metal (Ni, Cr, W) and dielectric (SiNx, Al2O3, HfO2) diffusion barriers at suppressing
copper-silicon interdiffusion. Most of these diffusion barriers showed some ability to reduce the
extent of this reaction, but none of them were able to suppress it entirely. This was likely due to
the crystallinity of the films in question, as the evaporated metal films are by nature
polycrystalline, and the dielectric layers – while amorphous in the as-deposited state – all showed
evidence of crystallization during graphene growth. Thus, all samples contained plentiful grain
boundaries along which copper and silicon atoms were able to diffuse. By comparison, the use of
a single-crystal sapphire substrate showed great promise for high quality graphene growth, with
no sign of any undesirable reactions and comparable as-grown Raman spectra to the best quality
graphene on freestanding foils.
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6.2 Graphene Device Fabrication
This thesis established a full fabrication flow for CVD graphene devices on arbitrary
substrates, beginning first with the transfer of the graphene films from copper foils onto
insulating substrates such as oxidized silicon or sapphire. A study of copper wet etchants was
performed, comparing the baseline ferric chloride etchant to nonmetallic etchants such as
ammonium persulfate and nitric acid. Ultimately, the ferric chloride based etchant was found to
be more conducive to high-quality graphene layer transfer, as it was the only solution that did not
produce hydrogen bubbles during etching that could mechanically damage the graphene.
However, an additional HCl clean step was needed following etching with ferric chloride in order
to eliminate residual iron contamination. The final graphene transfer process was shown to retain
the high crystalline quality of the as-grown graphene and present a suitable film for subsequent
device processing.
Following graphene layer transfer, fabrication processes for active device isolation,
ohmic contact formation, gate dielectric deposition, and gate contact formation were established
based on a combination of best known methods from literature and experiment. Many processing
steps were leveraged from previous work on epitaxial graphene, but with key nuances specific to
CVD graphene. In particular, the formation of high quality ohmic contacts to CVD graphene
required a re-examination of the pre-ohmic plasma treatment and subsequent high temperature
anneals. Ultimately, the best ohmic contact results from this work were still short of the best
known results for epitaxial graphene – approximately 8x10-6 Ω-cm2, as compared to ~1x10-7 Ω-
cm2 for epitaxial graphene. However, this may have largely been the consequence of sample
limitations that prevented a full evaluation of the available annealing window. Thus, the results of
this thesis still represent a promising foundation for graphene transistors based on CVD material
synthesized on copper foils.
105
6.3 Electrical Characterization of CVD Graphene Devices
The final component of this thesis was a study of electrical transport of graphene
transferred to three different substrate materials: Oxidized silicon, single crystal sapphire, and
MOCVD-grown GaN on sapphire. Temperature-dependent Hall mobility measurements were
performed from 5-400K. Experimental measurements were coupled with theoretical modeling to
assess the relative importance of different scattering mechanisms and provide broader
understanding of the optimal choice of substrate and dielectric overlayers for graphene devices in
various applications.
In general, measured Hall mobilities (1100-2100 cm2 V-1 s-1) were considerably lower
than is typical for exfoliated graphene, but in line with literature values for epitaxial and CVD
graphene. Temperature-dependence of mobility was weak, with only a 10-20% drop in mobility
from 5-400K, indicating that charged impurities were the dominant scattering mechanism
irrespective of substrate material. The influence of dielectric surface optical phonon (SOP)
scattering, while small, was able to be fit by the use of a single dimensionless fitting parameter, β.
Interestingly, this parameter was notably higher for the sapphire substrates, indicating that the
observed SOP scattering was lower on a relative basis than the SiO2 and GaN substrates. The
physical origins of that difference are not able to be conclusively determined from this dataset,
but existing literature posits that the most likely sources of variability are either a difference in the
interaction distance between the graphene and dielectric or the magnitude of the Frolich coupling
parameter.
Calculated trends for mobility as a function of sheet carrier density and impurity
concentration identify clear conclusions for future device applications. In situations where
impurity concentration can be driven lower, optimal dielectrics will have only high energy
phonon modes. Examples of such dielectrics include SiC and AlN. In the opposite scenario where
impurity concentration is known to be high, the use of high-K dielectrics such as HfO2 or ZrO2 is
106
critical, in order to take advantage of the “dielectric screening” effect of those films to improve
mobility.
107
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