This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Outputs: Built-in source series terminators (to SRAMs)
Data Lines (IDT74ALVC162245) :
All Inputs: Built-in diode clamping
B-port Outputs: External source series terminators (to Pulsar)
A-port Outputs: Built-in source series terminators (to SRAMs)
Board Layout TechniquesBoard Layout Techniques
Board Layers: 8Board Layers: 84 signal layers4 power layers
To To acchieveacchieve optimal system performanceoptimal system performanceDouble side placement: Bank0 on top, Bank1 on Bottom.Swap Bank0 and Bank1 Address and Data pin orders to share viasthat greatly reduce route length and avoid T-junctionsShort trace to reduce time of flightTerminate lines to increase signal integrityGroup Address and Data lines for better routing Place different group wires in different layers to reduce cross talkPlace decoupling capacitors to reduce power supply and circuit switch noiseObey EMC/EMI rules to avoid signal cross talk and reduce systemnoiseAll trace are impedance controlled (50 ohms)
Board Stack Order and Layer ThicknessBoard Stack Order and Layer Thickness
Add extra power layer pair (layer4, Layer5)Add extra power layer pair (layer4, Layer5)
(1) Acts as a distributed decoupling capacitor on entire board
(2) Isolates signal layers (layer3 and layer6) to reduce EMC/EMI emissions
(3) Increases ability to sink heat out of SRAM chips