STT-RAM Test Chip #1

STT-RAM Test Chip #1

Amr Amin Preeti Mulage

UCLA

CKY Group

Weekly Status Report

Date: Wed Nov-04-2009

Remaining Tasks• SA offset and min “read” signal• Using VA model for the MTJ (Preeti)• Simulating the “write” circuit (Preeti)• Adjusting the Addressing Logic• Adding the dummy poly resistors and extra MUXs (Amr)• Adding logic for testing (Amr)• Adjusting timing and control• Using an un-clocked amp instead of the latch• Scan Chain synthesis (Yuta and Preeti)• Top cell integration (Amr)• Chip Sim with package model (Amr and Preeti)• Layout (Amr and Preeti)• Post layout sim (Amr and Preeti)• Tapeout !

Memory Array Revisited

• What should be… J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

J

MUX

MSL MBL

Memory Array Revisited

• What we have…

MUX

MSL MBL

Memory Array Revisited

• Adding dummy resistors:– The easy way– Each resistor can have a

different value– Reference resistance will

be constant

MUX

MSL MBL

R1 R2 R3 R4

Memory Array Revisited

• Adding dummy resistors:– One variable conductance

for each half-bank– Can help having a variable

reference– Same Column-Select

Signals can be used for both MUXs

– Resistance programming bits should come from the scan-chain

MUX

MSL MBL

MUX

RN RP

Memory Array Revisited

• Combination of the previous two solutions

• Fixed resistance for each column

• One variable resistance for the reference

• Testing MUX allows each resistor to be measured

• Programming bits and Test MUX controls should come from the scan-chain MUX

MSL MBL

R1 R2 R3 R4

MUX

MSL MBL

R5 R6 R7 R8

RS

L1

RB

L1

RS

L2

RB

L2

MUX

PR

B1

PR

B2

Operation Modes

• Still working on defining the chip operation modes and writing a truth table for the allowed combinations of control bits

Pin ListPin Name Type Direction Description Notes

1 ADD<9> Logic Input Memory input address: 0 Top Banks, 1 Bottom Banks2 ADD<8> Logic Input Memory input address: Row Pre-decoder: SIG_73 ADD<7> Logic Input Memory input address: Row Pre-decoder: SIG_84 ADD<6> Logic Input Memory input address: Row Pre-decoder: SIG_95 ADD<5> Logic Input Memory input address: Row Pre-decoder: SIG_106 ADD<4> Logic Input Memory input address: Row Pre-decoder: SIG_117 ADD<3> Logic Input Memory input address: Row Pre-decoder: SIG_128 ADD<2> Logic Input Memory input address: Column Pre-decoder: SIG_49 ADD<1> Logic Input Memory input address: Column Pre-decoder: SIG_5

10 ADD<0> Logic Input Memory input address: Column Pre-decoder: SIG_6

11 DIN<3> Logic Input Data Input: Right half of Right Banks (DIN_RR)12 DIN<2> Logic Input Data Input: Left half of Right Banks (DIN_LR)13 DIN<1> Logic Input Data Input: Right half of Left Banks (DIN_RL)14 DIN<0> Logic Input Data Input: Left half of Left Banks (DIN_LL)

15 QOUT<3> Logic Output Data Output: Right half of Right Banks (Q_RR)16 QOUT<2> Logic Output Data Output: Left half of Right Banks (Q_LR)17 QOUT<1> Logic Output Data Output: Right half of Left Banks (Q_RL)18 QOUT<0> Logic Output Data Output: Left half of Left Banks (Q_LL)

19 EMA<2> Logic Input Extra Margin Adjustment: fast setting = 020 EMA<1> Logic Input Extra Margin Adjustment: fast setting = 021 EMA<0> Logic Input Extra Margin Adjustment: fast setting = 0

22 CEN_B Logic Input Chip enable: Active Low23 WEN Logic Input Write Enable: Active High24 CLK Logic Input Clock Will be used only for Scan Chain

25 VDD_LFT Power Input VDD = 1V : Left Half of the Chip26 VDD_RGT Power Input VDD = 1V : Right Half of the Chip27 VDD_IO_LFT Power Input VDD = 1.2V : Input/Output Left Half of the Chip28 VDD_IO_RGT Power Input VDD = 1.2V : Input/Output Right Half of the Chip

29 GND_LFT Power Input GND : Left Half of the Chip30 GND_RGT Power Input GND : Right Half of the Chip31 GND_IO_LFT Power Input GND : Input/Output Left Half of the Chip32 GND_IO_RGT Power Input GND : Input/Output Right Half of the Chip

Current List

Can be replaced by Scan Chain

Can be removed and connected internally to GND

Pin List

Pin Name Type Direction Description

1 VB Analog Input Bias Voltage for the Measured cells in the two Sas2 VBR Analog Input Bias Voltage for the Reference cells in the two Sas3 IBIAS_L Analog Input Bias current for the Left SA4 IBIAS_R Analog Input Bias current for the Right SA5 RWEN Logic Input Reference Write Enable (Active High)6 EQ_B Logic Input SA Equalize (Active Low)7 TEN Logic Input Test Mode Enable (Active High)8 PRB_1 Analog Input/Output Measurement Probe9 PRB_2 Analog Input/Output Measurement Probe

10 R_CNTRL<3:0> Logic Input 3 pins for programming the values of the dummy resistances11 R_SEL<16:0> Logic Input 17 pins for selecting 1 out of 17 resistors to be connected to two pins for measurement

Additional Pins Needed

Pin List

Pin Name Type Direction Description Notes

1 ADD<9> Logic Input Memory input address: 0 Top Banks, 1 Bottom Banks2 ADD<8> Logic Input Memory input address: Row Pre-decoder: SIG_73 ADD<7> Logic Input Memory input address: Row Pre-decoder: SIG_84 ADD<6> Logic Input Memory input address: Row Pre-decoder: SIG_95 ADD<5> Logic Input Memory input address: Row Pre-decoder: SIG_106 ADD<4> Logic Input Memory input address: Row Pre-decoder: SIG_117 ADD<3> Logic Input Memory input address: Row Pre-decoder: SIG_128 ADD<2> Logic Input Memory input address: Column Pre-decoder: SIG_49 ADD<1> Logic Input Memory input address: Column Pre-decoder: SIG_5

10 ADD<0> Logic Input Memory input address: Column Pre-decoder: SIG_6

11 R_CNTRL<3:1> Logic Input 3 pins for programming the values of the dummy resistances12 R_SEL<16:0> Logic Input 17 Pins for selecting 1 of 17 resistors for measurement

Scan-Chain Signals

It can be loaded serially and then incremented by 1 with a CLK signal

They can be read serially and kept constant

Pin ListPin Name Type Direction Description Notes

1 SC_IN Logic Input Scan Chain Input2 SC_CNTRL Logic Input Scan Chain Control3 SC_CLK Logic Input Scan Chain Clock4 SC_RD Logic Output Scan Chain Read Out

5 DIN<3> Logic Input Data Input: Right half of Right Banks (DIN_RR)6 DIN<2> Logic Input Data Input: Left half of Right Banks (DIN_LR)7 DIN<1> Logic Input Data Input: Right half of Left Banks (DIN_RL)8 DIN<0> Logic Input Data Input: Left half of Left Banks (DIN_LL)

9 QOUT<3> Logic Output Data Output: Right half of Right Banks (Q_RR)10 QOUT<2> Logic Output Data Output: Left half of Right Banks (Q_LR)11 QOUT<1> Logic Output Data Output: Right half of Left Banks (Q_RL)12 QOUT<0> Logic Output Data Output: Left half of Left Banks (Q_LL)

13 CEN_B Logic Input Chip enable: Active Low14 WEN Logic Input Write Enable: Active High15 RWEN Logic Input Reference Write Enable (Active High)16 EQ_B Logic Input SA Equalize (Active Low)17 TEN Logic Input Test Mode Enable (Active High)

18 VB Analog Input Bias Voltage for the Measured cells in the two Sas19 VBR Analog Input Bias Voltage for the Reference cells in the two Sas20 IBIAS_L Analog Input Bias current for the Left SA21 IBIAS_R Analog Input Bias current for the Right SA22 PRB_1 Analog Input/Output Measurement Probe23 PRB_2 Analog Input/Output Measurement Probe

24 VDD_LFT Power Input VDD = 1V : Left Half of the Chip25 VDD_RGT Power Input VDD = 1V : Right Half of the Chip26 VDD_IO_LFT Power Input VDD = 1.2V : Input/Output Left Half of the Chip27 VDD_IO_RGT Power Input VDD = 1.2V : Input/Output Right Half of the Chip

28 GND_LFT Power Input GND : Left Half of the Chip29 GND_RGT Power Input GND : Right Half of the Chip30 GND_IO_LFT Power Input GND : Input/Output Left Half of the Chip31 GND_IO_RGT Power Input GND : Input/Output Right Half of the Chip

Modified List

4-Pins for the Scan-Chain