Presentation STT-RAM Survey

STT-RAM: SURVEY OF CURRENT AND EMERGING TRENDS

SWAPNIL S. BHOSALE

NEED FOR NEW MEMORY TECHNOLOGY

• Critical applications now-a-days are more data-centric and less compute-centric.

• Memory performance becoming a bottleneck due to increasing amount of data.

• Compute speed can still be increased but processor speed is limited by memory

speed.

• Clock speed cannot be increased above certain limit to avoid heating.

• Need of an alternate memory technology which can replace existing

technologies in memory hierarchy.

REVOLUTION IN MEMORY

• Researchers proposed STT-RAM (Spin Transfer Torque Random Access Memory).

• It can be used as ‘Universal Memory’.

• It has potential to replace all memories in existing memory hierarchy.

• It has characteristics of every level in memory hierarchy viz. high performance

high density

high capacity

high endurance

low power consumption

non-volatility

future scalability

LEADING DEVELOPERS AND RESEARCHERS OF STT-RAM

• Grandis Inc. is the key inventor and pioneer in STT-RAM technology.

• Hitachi and Tohoku University demonstrated a 32-Mbit STT-RAM in June

2009.

• In 2011, Qualcomm presented a 1 Mbit Embedded STT-MRAM,

manufactured in TSMC's 45 nm LP technology at the Symposium on VLSI

Circuits.

ARCHITECTURE AND DESIGN OF STT-RAM CELL

• MTJ (Magnetic Tunnel Junction) is the basic storage element of the cell.

• MTJ structure: Two ferromagnetic layers viz. Hard layer and Free layer

Hard layer has fixed magnetic orientation.

Free layer has variable magnetic orientation.

Data is stored as relative magnetic orientation of these two layers.

• Physics: Two physical phenomenon describe the functionality of STT-RAM.

Tunneling magnetoresistance (TMR) effect for reading and the spin-transfer torque (STT) effect for writing.

TMR enables magnetic state of the Free layer to be sensed and hence the stored information to be read.

STT enables electrons/current flowing through MTJ to change the relative orientation

STT-RAM SCHEMATIC, SINGLE CELL SCHEMATIC AND ITS SI SUBSTRATE REPRESENTATION

STT-RAM SCHEMATIC, SINGLE CELL SCHEMATIC AND ITS SI SUBSTRATE REPRESENTATION

• MTJ is connected between the Bit line and drain of the access/selection

transistor.

• MTJ is represented as resistance.

• It exhibits low resistance when magnetic orientation between Hard Layer and

Free layer is parallel (P).

• It exhibits high resistance when magnetic orientation between Hard Layer

and Free layer is anti-parallel (AP).

WORKING OF STT-RAM CELL

• The relative magnetic orientation is changed by passing spin-polarized

current through MTJ.

• Current transfers spin angular momentum between the magnetic layers.

• This results in torque on magnetization of Free layer changing its relative

magnetic orientation w.r.t. that of Hard layer.

• Depending on the direction of current, the two layers are aligned in parallel

or anti-parallel position.

WRITING ‘1’ AND ‘0’

STT-RAM AND OTHER MEMORY TECHNOLOGIES

CHARACTERISTICS OF STT-RAM

• STT-RAM has all the characteristics of a universal memory:Non-volatile

Highly scalable

Low power consumption

SRAM read/write speed

Unlimited endurance (>10^16)

DRAM & Flash density (6 F2)

Multi-level cell capability

CHALLENGES FACED

• Two main challenges:-

1. Stochastic nature of MTJ:

Transient behavior is non-deterministic due to random thermal kicks acting on its magnetization during switching activity.

Thermal stability factor (D) is the measure of its stable transient behavior.

D = (Hk*Ms^2*Ar*t^2)/(kB*T)

Where, Ms = Saturation magnetization, Ar = Area of MTJ, Hk = Uniaxial anisotropy, t = thickness of free layer

2. High write energy:

Intrinsic/switching/write current density (Jc0) can give the measure of write energy.

Jc0 = (2* α *Ar*Ms*t*e)(Hk + 2πMs)/(η*Ϧ)

Where, η = spin transfer efficiency, α = damping constant, e = electronic charge

• To maintain D with the high Ms, the switching current increases.

• For reliable memory operation, low switching current with high value of D is required.

CURRENT TRENDS

• Clinton W. Smullen, et al demonstrated a scheme to reduce write energy of STT-RAM by relaxing its

non-volatility for using it as fast and energy-efficient cache. Reduction in planar area of MTJ caused

reduction in retention time and hence non-volatility.

• In another paper, Clinton W. Smullen, et al, proposed a scheme to reduce write energy by tuning the

saturation magnetization ‘Ms’ and thickness of Free layer ‘t’.

• In the same paper, Clinton W. Smullen, et al, proposed another approach wherein the difference between

write energy for write 0 and write 1 is considered and the minimum of two is used write STT-RAM cell.

7% average reduction in total write energy is achieved.

• Vidyabhushan Mohan, et al, considered room temperature as parameter to adjust the retention time and

hence reduce write energy. 70% reduction in energy-delay product is supposed to be achieved.

CURRENT TRENDS

• Zhou, Ping, et al. proposed early write termination (EWT) scheme to improve the

energy efficiency of a STT-RAM cache. In this, the content of cache is read out first

before doing a write operation, compared with the incoming bits and only the different

bits are wrote back. 80% reduction in write energy and 33% reduction in total energy is

achieved .

• Yazdanshenas, Sadegh, et al. proposed coding last level STT-RAM cache wherein the

frequent data in the cache lines was coded to avoid unnecessary update of significant

part of the word. 12% reduction in ‘write in the cache lines’ is supposed to be achieved

as compared to the EWT technique.

CURRENT TRENDS

• Jog, Adwait, et al. cache revive technique to calculate retention time. Some cache blocks retain data

even after completion of retention time. The retention time is so chosen that will minimize the

number of unrefreshed cache blocks. This technique would increase the performance and energy by

18% and 60%, respectively.

• Yue Zhang1,2, et al, used stochastic nature of MTJ as a knob to maintain the thermal stability. Multi

level cell structure was designed and programmed such that cells change their states randomly but

correctly.

• Kultursay,E, et al, evaluated the performance of STT-RAM as a main memory and showed that the

performance and energy can be significantly improved by using partial write and row buffer write

bypass. 60% reduction in main memory energy can be achieved as compared to DRAM.

CURRENT TRENDS

• Park, H., et al, provide an insight into limited density of STT-RAM due to access transistor

width and proposed a cell structure with multiple MTJs per access transistor. Limited

amount of sharing is possible but considerable increment in density is achieved.

• Clinton W. Smullen, et al, deals with new class of in-plane MTJ structures with high partial

perpendicular anisotropy for simulating and modelling memory systems. Perpendicular

anisotropy provide faster switching and higher density compared to in-plane anisotropy.

• Grandis Inc. explored dual MTJ structures with two barrier layers and obtained reduced

Jc0 with maintained thermal stability.

FUTURE PROSPECTS

• Promising candidate for replacing SRAM, DRAM and MRAM in cache and main

memory.

• Excellent scalability feature allows the researchers to evaluate its performance in

multicore processing systems and parallel high performance computing systems.

• Compact and simple cell structure provide higher packaging density thus decreasing

the cost per unit. Possible to implement multi-level cell structure using MTJ further

increasing the cells per unit area.

• High endurance implies increased lifetime of memory.

FUTURE PROSPECTS

• Standalone STT-RAM and Embedded STT-RAM product roadmap:

Mohamad T. Krounbi, S. Watts, D. Apalkov, X. Tang, K. MoonV. Nikitin , A. Ong, V. Nikitin, E. Chen, “Status and Challenges for Non-Volatile Spin-Transfer Torque RAM (STT-RAM) ppt,” International Symposium on Advanced Gate Stack TechnologyAlbany, NYSeptember 29 –October 1 , 2010.

CONCLUSION

• STT-RAM is capable of being called as ‘Universal Memory’.

• maintaining a balance between its two parameters viz. thermal stability and

write current density is a prime challenge before it can be used as a Universal

Memory.

• Novel techniques have been proposed and are being invented which could

help improve its performance and energy efficiency.

THANK YOU!