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AIJRSTEM is a refereed, indexed, peer-reviewed, multidisciplinary and open access journal published by International Association of Scientific Innovation and Research (IASIR), USA
(An Association Unifying the Sciences, Engineering, and Applied Research)
Stackiabatic: Novel Concept for Reducing the Power Consumption and
Practical Implementation Using NOT & NAND Gates Kapil Mangla, Prof. (Dr.) Anil Kumar
Al-falah School of Engineering & Technology,
Dhauj, Faridabad, Haryana, INDIA.
I. INTRODUCTION Industry over last few decades has seen a tremendous growth in the electronics segments. Market is flooded
with highly sophisticated and technically advanced gadgets. The advances in electronics industry because of
technically advanced ICs (Integrated Circuits) and increase transistor switching speed has resulted in many fold
performance improvement in computer systems. On the hind side, there has been increased consumption of
power to bring this change. A community of scientists / researchers has thus being trying to reduce this
dissipation by improving the circuit design. High performance systems cause high energy consumption, needs
better cooling technology, requires expensive packaging, decrease system reliability and on top of all-increase
the cost of system.
Power depends on the way circuit is designed however it can be divided into static and dynamic power. The
former is generated due to direct current bias, as in case TTL (Transistor–transistor–logic) and ECL (emitter–
coupled– logic) and NMOS (N-type MOS) or due to leakage current. Except for push – pull type logic family
such as CMOS, static power tends to dominate. Because of this CMOS is considered to be most suitable circuit
style for VLSI (very large scale integrated circuit). The driving force behind very large scale integration circuits
(VLSI) for high performance computing related to science and technology has been digital CMOS integrated
circuits. It is speculated that the demand for digital CMOS IC’s will keep increasing because of its important
feature improvement in processing technology, reliable performance and low power.
A major concern has been the dynamic power requirement of the CMOS in large computer and personal
information systems. In this Work, power consumption depends upon the width and length ratio is presented. If
we change the width and length of the device then it’s current and gate capacitance changes. In this work there
is 180nm technology has been used. So that the length is fixed but there is a change in the width. The result is
depends upon different width and length ratio. Current will increase if the width of transistor increases and gate
capacitance also increases if the width of transistor increase and vice versa. The power consumption also
depends upon the current in the circuit and current depends upon the width and length ration.
II. OVERVIEW OF POWER DISSIPATION
As we all know that CMOS work in three regions: Cut-off region, saturated region and non saturated region. So
the current is different in different regions.
In cut-off region:
In linear / non-saturated / active region:
Abstract: For many years, designing of high speed low power circuits with CMOS technology was a difficult
challenge for research community. There are various levels at which design problem related to low power
and increased demand can be addressed; these levels are - software level, architecture level, algorithm
level, circuit level and process technology level. The objective of this paper is to put forth different
approaches that reduce the consumption of power of any random combinational logic by applying
minimization techniques at circuit level. In this paper we have designed NAND & NOT gate using
stackiabatic technique and compared with conventional, adiabatic & stacking techniques. The objective of
this paper is to put different approaches that reduce the consumption of power
IX. CONCLUSION Comparison has been done for NAND & NOT gate, delay and power is calculated for Different Techniques.
Designed the NAND & NOT using Conventional, Adiabatic, Stacking & Stackiabatic Techniques and
implemented these techniques for power reduction then we can observe the minimum power consumed in
Stackiabatic Technique. The tool for simulation is TANNER. At 180 nm technology and the practical
observations have been tabled.
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