Spring 2009 W. Rhett Davis NC State University ECE 406 Slide 1 ECE 406 – Design of Complex ECE 406 – Design of Complex Digital Systems Digital Systems Lecture 4: Lecture 4: Testing, Dataflow Modeling Testing, Dataflow Modeling Spring 2009 Spring 2009 W. Rhett Davis W. Rhett Davis NC State University NC State University with significant material from Paul Franzon, Bill with significant material from Paul Franzon, Bill Allen, & Xun Liu Allen, & Xun Liu
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Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009.
Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l What is the format of a Verilog instantiation? l Are all parts of the instantiation required? l What is the order of the port-names in a gate instantiation? A module instantiation? l Can a reg variable be connected to the input port of an instance?
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Spring 2009W. Rhett Davis NC State University ECE 406 Slide 1
ECE 406 – Design of Complex ECE 406 – Design of Complex Digital SystemsDigital Systems
Spring 2009Spring 2009W. Rhett DavisW. Rhett Davis
NC State UniversityNC State Universitywith significant material from Paul Franzon, Bill Allen, & Xun with significant material from Paul Franzon, Bill Allen, & Xun
LiuLiu
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 2
Announcements HW#1 Due Today
HW#2 Due in 1 week» Make sure that hw2-2.v executes correctly
with the command “ncverilog hw2-2.v”» Work through first to pages of Verilog
Simulation Tutorial (on the Resources Page) to learn more
Labs Start This Week
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 3
Summary of Last Lecture What is the format of a Verilog instantiation?
Are all parts of the instantiation required?
What is the order of the port-names in a gate instantiation? A module instantiation?
Can a reg variable be connected to the input port of an instance?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 4
Today’s Lecture
Test-Benches
Behavioral (Data-Flow) Modeling
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 5
From Last Lecture
module mux_2 (out, i0, i1, sel); input i0, i1, sel; output out; wire n_sel, x1, x2; or (out, x1, x2); and (x1, i0, n_sel); and (x2, i1, sel); not (n_sel, sel); endmodule
out2-to-1Mux
i0
i1
sel
i0
seli1
out x1n_sel
x2
2-to-1 Multiplexer
How do we test this description?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 6
Parts of a Verilog Module Header: module <module_name> (<port_list>); Parameter, Port, & Variable declarations Functionality description» Structural
– Instantiations of basic gates (T&M 6.2)– Instantiations of lower-level modules (T&M 1.4, 5)
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 7
A Typical Test-Bench
Header: module <module_name>; Variable declarations Functionality description» Instantiation of the Device Under Test (DUT)» initial block to describe the Stimulus and
display the output Terminator: endmodule
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 8
Choosing the Stimulus Job of the Stimulus is to
apply test vectors (input combinations)
If we want to be 100% certain that the module is working correctly, how many vectors must be applied by the stimulus?
out2-to-1Mux
i0
i1
sel
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 9
Choosing the Stimulus Exhaustive testing
quickly becomes impractical as the number of inputs grows.
Need to choose a reduced set of test vectors that exposes the most likely errors.» It’s up to you to figure out
what kinds of errors you’re likely to make
For this example, we’ll use the following vectors:
i0 i1 sel0 1 00 1 11 0 01 0 1
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 10
Variable Declarations All variables in the test bench basically
connect to the DUT
Variables connected to DUT outputs» Will these be declared as wire or reg? Why?
Stimulus variables (connected to DUT inputs)» Will these be declared as wire or reg? Why?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 11
mux_2 Test BenchWrite the module header, variable declarations, and instantiation for the mux_2 test-bench:
out2-to-1Mux
i0
i1
sel
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 12
mux_2 Test BenchStimulus and terminator for the mux_2 test-bench:
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 13
Running the SimulationYou run the simulation,and the output looks like this:
in0 = 0 in1 = 1 sel = 0 out = xin0 = 0 in1 = 1 sel = 1 out = x in0 = 1 in1 = 0 sel = 0 out = x in0 = 1 in1 = 0 sel = 1 out = x
So what happened? Why was out an x?
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 14
Annotating Time
Delays are introduced into the stimulus by inserting #nn at the beginning of a statement (where nn is the number of time units)
Write the code to assign the hex values 1234 and 5678 into A and B simultaneously and then, 10 units of time later, assign the hex value 90AB is set into C:
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 15
mux_2 Test Bench w/ TimeStimulus for the mux_2 test-bench with 10 units of time between each vector:
initial begin in0 = 0; in1 = 1; sel = 0; // vector #1 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 1; // vector #2 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 0; // vector #3 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 1; // vector #4 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); $finish; // not needed, but handy if you want to end earlier end
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 16
Re-running the Simulation
Having made these revisions, the simulation is rerunand the simulation output is:
in0 = 0 in1 = 1 sel = 0 out = 0in0 = 0 in1 = 1 sel = 1 out = 1in0 = 1 in1 = 0 sel = 0 out = 1in0 = 1 in1 = 0 sel = 1 out = 0
Which is what we would expect from the 2-to-1 mux.
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 17
Using $display and $monitor The $display task outputs the specified data whenever
a $display statement is encountered in the sequential execution of the stimulus.
The $monitor task watches the variables listed in the $monitor command and produces an output whenever any one of them changes.
A single $monitor statement may suffice in a test fixture instead of a series of identical $display statements.
Only one $monitor statement can be in effect during a simulation (the last one always takes effect).
It’s common to use single $monitor statement and multiple $display statements.
Spring 2009W. Rhett Davis NC State University ECE 406 Slide 18