421 Appendix F SPHERES AVIONICS DESIGN This appendix presents detailed descriptions of the SPHERES avionics. The SPHERES laboratory avionics sub-systems implements electronics for the satellites, communications with the control computer, metrology beacons, and a beacon tester. This appendix also presents the design of several expansion port items already in use. Each section presents the functional block diagram and the complete schematics (when applicable) for all the electronic components of the SPHERES laboratory: • SPHERES nano-satellites - Power & control panel - Data processing unit (C6701 DSP / SMT375) - Metrology - Communications - Propulsion - Expansion Port - Internal beacon • Laptop communications • Metrology Beacons • Metrology Beacon Tester • Expansion Port Items
86
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421
Appendix F
SPHERES AVIONICS DESIGN
This appendix presents detailed descriptions of the SPHERES avionics. The SPHERES
laboratory avionics sub-systems implements electronics for the satellites, communications
with the control computer, metrology beacons, and a beacon tester. This appendix also
presents the design of several expansion port items already in use. Each section presents
the functional block diagram and the complete schematics (when applicable) for all the
electronic components of the SPHERES laboratory:
• SPHERES nano-satellites
- Power & control panel
- Data processing unit (C6701 DSP / SMT375)
- Metrology
- Communications
- Propulsion
- Expansion Port
- Internal beacon
• Laptop communications
• Metrology Beacons
• Metrology Beacon Tester
• Expansion Port Items
422 APPENDIX F
F.1 SPHERES nano-satellites
The electronics of the SPHERES nano-satellites, shown in Figure F.1, are implemented in
two primary "electronics stacks", with several peripheral electronic boards. The groupings
are as follows (third level bullets indicate peripheral electronic boards which support the
• Provide the necessary power and voltages for all sub-systems
- 3.3 V: DSP, Metrology, Communications
- 5 V: DSP, Metrology, Communications, Propulsion
- ±15 V: Metrology (gyros and accelerometers)
- 22 V: Propulsion
• Meet applicable ISS safety guidelines
• Maximize battery utilization
Functional Block Diagram
The power sub-system is comprised of three main type of electronic boards: battery packs,
control panel, and the power regulation board. The circuit breaker and power switch are
wired independently. The functional description, inputs, and outputs of each component
are presented below.
Battery packs
There are two types of battery packs: flight and rechargeable. The functions of the two
types are:
• Flight: Provides up to two hours of operations to the SPHERES nano-satel-lites through 8 AA alkaline batteries. It also provides diode and fuse protec-tion to meet NASA Safety requirements (triple redundancy).
• Rechargeable: Provides up to two hours of operations to the SPHERESnano-satellites through 8AA NiMH rechargeable batteries. The batterycharging circuit resides within the packs themselves, requiring only a 15Vdcexternal supply. The external supply can have an optional LED to indicatecharging status. The board provides the same diode and fuse protection asthe flight packs.
Its inputs and outputs are listed in Table F.1
APPENDIX F 425
Power Switch
The power switch is a two phase mechanical switch. The switch is two phase so that the
battery positive power connections are isolated when the switch is open (the SPHERES
are off), preventing any current from flowing between the battery packs. While not neces-
sary for NASA safety requirements, it allows the battery packs to remain inserted in the
satellites without risk. Its inputs and outputs are listed in Table F.2
Figure F.2 Power sub-system functional block diagram
The magnetic circuit breaker provides 5A current protection. A thermistor is connected in
series with the circuit breaker to prevent power-surges larger than 5A when the satellites
are turned on and the large bypass capacitor (3300µF) charges. Once heated the thermistor
has a resistance of approximately 0.1Ω. The inputs and outputs of this board are listed in
Table F.3
TABLE F.1 Battery packs signals description
Signal Type DescriptionFlightVin In Unregulated input voltage from 8AA batteries (6.4-
13.6V)Vout Out Protected, unregulated voltage (5.8-13.0V due to 0.6V
drop through diodes)GND Pwr Common reference groundRechargeableVin In Unregulated input voltage from 8AA batteries (6.4-
13.6V)Vout Out Protected, unregulated voltage (5.8-13.0V due to 0.6V
drop through diodes)Vsupply In 15V input voltage for recharging circuitFT Out Signal to external LED which indicates charging in pro-
cess (blinking) or done (solid on)GND Pwr Common reference ground
TABLE F.2 Power Switch signals description
Signal Type DescriptionTwo phase power switch which isolates the battery packs when turned off
Vin1, Vin2 In Protected, unregulated voltage from battery packsVout1, Vout2 Out Switched, unregulated voltage to circuit breaker
APPENDIX F 427
Control Panel
The control panel is the primary manual interface of the satellites. The panel mechanically
holds the power switch, although it is not connected electrically. The panel electronics
only include digital I/O lines powered through the regulated 5V supply. The elements in
the panel are:
• Reset button - creates a negative logic signal which connects directly to thewatchdog module, which in turn generates a correctly timed reset signal forthe rest of the electronics.
• Enable button - creates a negative logic signal which is sent directly to theSPHERES FPGA as a general I/O signal; the SPHERES Core Softwarechecks the state of this button to enable operations (go from "idle" to "ready"or "running" mode).
• Power LED - driven directly off the regulated 5V supply indicates when thepower is on; since it is driven directly off the 5V supply, it is only on whenthe supply operates correctly, giving a reasonable indication that the powerregulation module is operating correctly.
• Low Battery LED - the watchdog measures the unregulated battery voltageand indicates a low battery condition when there are approximately 20 min-utes remaining of operation.
• Enabled LED - the LED is driven directly off the SPHERES FPGA as a gen-eral I/O signal; it is turned on by the SPHERES Core Software when the sat-ellites are in a "ready" or "running".
The inputs and outputs of this board are listed in Table F.4
Power Regulation Board
The power regulation board is the most complex board of the power sub-system. It pro-
vides power regulation for the data stack and all other avionics1, contains the watchdog,
and serves as a bypass for the propulsion signals. The board outputs four voltages to the
TABLE F.3 Circuit breaker signals description
Signal Type DescriptionVin1, Vin2 In Switched, unregulated voltage from power switchVout Out Switched and protected, unregulated voltage to power
board
428 APPENDIX F
second stack: +3.3V, +5V, +15V, and -15V. The +3.3V and +5V signals are used through-
out the system to power electronic components. The ±15V powers the accelerometers and
gyroscopes. The power board is the mechanical attachment point for two of the gyro-
scopes, although no electrical signals from the gyroscopes pass through the board.
Table F.5 lists the inputs and outputs of this board (or refers to other tables as applicable).
1. The propulsion sub-system increases the unregulated voltage to 20V; the power board does not provide the higher voltage required by the propulsion circuit.
TABLE F.4 Control panel signals description
Signal Type DescriptionVcc Pwr Input +5V dcGND Pwr Common reference groundLED-enable In Enable LED control signalLED-lowbat In Low battery LED indicator control signal/Reset Out Reset signal to power board watchdog module/Enable Out Enable signal for SPHERES FPGA
TABLE F.5 Power regulation board signals description
Section Signal Type DescriptionPower to second elec-tronic stack
THR 1-12 In Pass through signals for thrusters 1-12/Enable Out Enable button pass through signal/LED-enable In Enable LED pass through signal/Batlow Out Low battery output to DSPWDOG In Watchdog control signal from DSP/RESET Out Reset control line to second electronics
stack
APPENDIX F 429
Schematics
The schematics of the power sub-systems follow.
Data and power to propulsion board
THR 1-12 Out Pass through signals for thrusters 1-12Vcc(5V) Pwr 5V power for propulsion boardVcc(unreg) Pwr Switched, protected, unregulated voltage
for propulsion boardGND Pwr Common ground
Data to/from con-trol panel
See Table F.4
TABLE F.5 Power regulation board signals description
Section Signal Type Description
430 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Ba
tte
ry P
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1.0
Ba
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APPENDIX F 431
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
H-1
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1-
Battery
Pack C
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D4
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536K
432 APPENDIX F
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPH-1-0800-### -
PowerSwitch Schematic - REFERENCE ONLY, NOT A PCB
A
1 1Sunday, May 19, 2002
Title
Size Document Number Rev
Date: Sheet of
BAT2 +
BAT1 +
BAT2 +
BAT1 +
JH6
BAT1 +
11
SW2
PWR SW
JH1
PWR1 +
1 1JH3
BAT1 +
1 1
J1
BAT 1
12
JH2
PWR2 +
1 1
JH4
BAT2 +
1 1
J3
BAT 2
12
JH5
BAT2 +
11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPH-1-0800-215 A
Circuit Breaker Board
A
1 1Tuesday, September 17, 2002
Title
Size Document Number Rev
Date: Sheet of
SW1
48-08 Circuit Breaker
2 3
4 5
6 7
V- V+
Aux In Aux Out
In Out
JH2
PWR1 +
11
JH3
PWR2 +
11
t
RT1
5
12
JH1
Vcc(Unreg)
1 1
APPENDIX F 433
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Sw
itch
Bo
ard
A
Sw
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Bo
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A
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LED-ENABLE (GRN)S
W1
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1 2
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AB
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6
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R2
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D1
LED-LowBat (AMB)
434 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
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Po
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APPENDIX F 435
5 5
4 4
3 3
2 2
1 1
DD
CC
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2R
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1 2 3
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On
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+V
in
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+V
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dj
436 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Po
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APPENDIX F 437
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
1.25V = Rbot / (Rtop + Rbot) * Vthr
if Vthr = 6.8V (Low Battery @ 7.5V battery - .7V of thermistor voltage drop)
1.25V/6.8V = Rbot / (Rtop + Rbot)
if Rbot = 102 kOhm
Rtop = 442 kOhm
Po
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438 APPENDIX F
F.1.2 Propulsion
Design Drivers
• Create a spike and hold signal for the solenoids as presented in Figure F.3
- Spike at +22V
- Spike hold time: 7ms
- Hold at +5V
- Minimum impulse bit: 5ms
- Maximum impulse bit: infinite
• Provide visual indication of solenoid states (open or closed)
Functional Block Diagram
Figure F.4 presents the functional block diagram of the propulsion system. A propulsion
board receives the propulsion inputs from the data processing stack (pass through in the
power board) and creates a spike and hold signal independently for each solenoid. The
driver signals are sent to the solenoid via shielded wire to reduce the EMI effects of the
spike on other circuits. A board with an LED attaches to the front face of the nozzle of
each solenoid to indicate its state (off = closed, on = open). The propulsion board creates
the +22V supply needed for the spike from the unregulated voltage input.
Figure F.3 Propulsion spike and hold timing diagram
time
outp
utin
put
22V
5V
0
1
0V
7ms
spike
hold
APPENDIX F 439
Propulsion Board
The propulsion board creates the spike and hold signal necessary to operate the solenoids.
The board utilizes a Maxim MAX668 step-up switching regulator to create 22V from the
variable 8-13V unregulated input. Each spike and hold circuit uses the schematic pre-
sented in Figure F.5 (with the necessary current limiting resistors and reverse voltage pro-
tection diodes). The inputs and outputs of this board are described in Table F.6.
Solenoid Board
The solenoid boards provide visual indication of the state of their corresponding solenoid.
Their small size allows them to be mounted directly on top of the connector side of each
nozzle, ensuring immediate correlation between an LED and a solenoid. The inputs and
The schematics for the propulsion sub-system follow.
TABLE F.6 Propulsion board signals description
Signal Type DescriptionGND Pwr Common groundVcc(5V) Pwr +5V supplyVcc(unreg) Pwr Unregulated (8-13V) powerProp[1-12] In Command signals from the data processing stackPosDriver[1-12] Out Positive terminal for each solenoidNegDriver[1-12] Out Negative terminal for each solenoid
TABLE F.7 Solenoid board signals description
Signal Type DescriptionThr + I/O Positive terminal of signal / solenoidThr - I/O Negative terminal of signal / solenoid
APPENDIX F 441
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
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it L
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pIn
Pro
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Drive
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r_4
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r_5
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Drive
r_6
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1
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Drive
r_1
2
Drive
rs
Pro
pO
ut+
Pro
pIn
Pro
pO
ut-
NegDriver_4PosDriver_4
thr9
thr7thr8
thr12
NegDriver_1PosDriver_1
NegDriver_7PosDriver_7
NegDriver_6PosDriver_6
NegDriver_5PosDriver_5
NegDriver_12PosDriver_12
NegDriver_11PosDriver_11
NegDriver_10PosDriver_10
NegDriver_9
thr1
thr4thr3
thr2
thr5thr6
thr10thr11
PosDriver_3
PosDriver_2
NegDriver_3
NegDriver_2
PosDriver_8
PosDriver_9
NegDriver_8
Po
sD
rive
r_5
Po
sD
rive
r_6
Po
sD
rive
r_7
Po
sD
rive
r_8
Po
sD
rive
r_9
Po
sD
rive
r_1
0
Po
sD
rive
r_1
1
Po
sD
rive
r_1
2
Po
sD
rive
r_1
Ne
gD
rive
r_1
Ne
gD
rive
r_5
Ne
gD
rive
r_6
Ne
gD
rive
r_7
Ne
gD
rive
r_9
Ne
gD
rive
r_1
0
Ne
gD
rive
r_1
1
Ne
gD
rive
r_1
2
Po
sD
rive
r_4
Po
sD
rive
r_3
Ne
gD
rive
r_3
Ne
gD
rive
r_4
Ne
gD
rive
r_2
Po
sD
rive
r_2
Ne
gD
rive
r_8
thr1
thr2
thr3
thr4
thr5
thr6
thr7
thr8
thr9
thr1
0
thr1
1
thr1
2
442 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
So
len
oid
Co
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ecto
rs
A
21
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
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ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
Po
sD
rive
r_1
Po
sD
rive
r_2
Po
sD
rive
r_4
Po
sD
rive
r_5
Po
sD
rive
r_6
Po
sD
rive
r_7
Po
sD
rive
r_8
Po
sD
rive
r_9
Po
sD
rive
r_1
1
Po
sD
rive
r_1
2
Ne
gD
rive
r_1
Ne
gD
rive
r_2
Ne
gD
rive
r_3
Ne
gD
rive
r_4
Ne
gD
rive
r_5
Ne
gD
rive
r_6
Ne
gD
rive
r_7
Ne
gD
rive
r_8
Ne
gD
rive
r_9
Ne
gD
rive
r_1
0
Ne
gD
rive
r_1
1
Ne
gD
rive
r_1
2
Po
sD
rive
r_1
0
Po
sD
rive
r_3
J4
TH
R-4
123
J8
TH
R-8
123
J1
2
TH
R-1
2
123
J1
TH
R-1
123
J5
TH
R-5
123
J9
TH
R-9
123
J2
TH
R-2
123
J6
TH
R-6
123
J1
0
TH
R-1
0
123
J3
TH
R-3
123
J7
TH
R-7
123
J1
1
TH
R-1
1
123
APPENDIX F 443
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
22
V S
up
ply
A
31
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(2
2V
)
VC
C(u
nre
g)
+C
13
3u
F
+C
22
2u
F
L1
22
uH
C4 1u
F
C7
0.2
2u
F
C6
0.0
01
uF
C3
1u
FR
20
.02
oh
ms
R3
12
.0k
R4
10
0 k
D1
MB
RS
340T
3
R1
20
0.0
k
C5
0.1
uF
U1
MA
X668
1 9
10 4 2
8 6 7 5
3
LD
O
Vcc
SY
NC
-/S
HD
N
RE
FF
RE
Q
EX
T
CS
+
PG
ND
FB
GND
N1
FD
S6
68
0
4
8 567321
444 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
Inp
ut
Co
nn
ecto
rs
A
41
6F
rid
ay,
Ap
ril 1
9,
20
02
Title
Siz
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ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
TH
R1
0T
HR
11
TH
R7
TH
R1
2
TH
R8
TH
R9
TH
R4
TH
R2
TH
R1
TH
R3
TH
R5
TH
R6
thr1
thr2
thr4
thr7
thr9
thr1
1th
r12
thr3
thr8
thr1
0
thr5
thr6
VC
C(5
V)
VC
C(u
nre
g)
JP
1
Inp
ut
12
34
56
78
91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
2
APPENDIX F 445
The following schematic repeats twelve times, once per signal/solenoid:5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Pro
pu
lsio
n B
oa
rd 2
- S
PH
-1-0
80
0-2
02
-
Pro
pu
lsio
n F
irin
g C
ircu
it
A
516
Frid
ay,
Ap
ril 1
9,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(5
V)
VC
C(2
2V
)
+C
9.0
1u
R6
10
k
R8
2.2
k
R7
10
k
D4
DIO
DE
D2 DIO
DE
D3 DIO
DE
R5
59
.0k
Q1
2N
22
22
C
B
E
U2
LM
555
2 5
3 7 6
4
8
TR
CV
Q
DIS
TH
R
R
VCC
+C
10
.04
7u
+C
8.1
0u
Pro
pO
ut+
Pro
pIn
Pro
pO
ut-
446 APPENDIX F
F.1.3 Data Processing (C6701 DSP / SMT375)
Design Drivers
• Support other subsystems’ data processing needs
- Communications data processing
- Metrology computational support
- Propulsion thruster actuation
- Provide house-keeping information to user
Battery information
Tank usage
• Allow reconfiguration of control algorithms
- Enable the complete software to be changed to allow testing of programswith different configurations and goals
• Maximize processing power for available volume and power
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Propulsion LEDs - SPH-1-0800-501 A
Thursters LED Indicators
A
1 1Tuesday, September 17, 2002
Title
Size Document Number Rev
Date: Sheet of
THR-THR+
J2
Solenoid Out
12
D1
LED
J1
PropIn
12
R14.9k
D2
1N4148
APPENDIX F 447
- Minimize processing needs of ‘bus’ system to maximize processingpower available for control algorithms
Functional Block Diagram
A COTS product was selected to perform the data processing within each SPHERES sat-
ellite. The selected product is a Sundance Multiprocessor Technology Ltd SMT375 board
which features a Texas Instruments TMS320C6701 Digital Signal Processor (DSP). The
SMT375 board utilizes the Texas Instruments Module standard for the C40 DSP (TIM40),
used in the prototype design of SPHERES. The standard implements a 32 bit global data
bus with 31 address lines, plus six TI communications ports which split 32 bit data into
bytes for a maximum data speed of 20MBps. A block diagram (simplified from [Sun-
dance, 2003]) of the SMT375 board is presented in Figure F.6. The SPHERES metrology
FPGA interfaces via the global data bus, while the communications system utilizes the
commports.The features of the SMT375 board are summarized in Table F.8
Figure F.6 SMT375 functional block diagram
TMS320C6701
SDRAM4M x 32
SBSRAM128k x 32
FLASH512k x 32
VIRTEX FPGA
Global BusCommports
SDB
SDB
(2)
Global DataBus
Commports6x
448 APPENDIX F
The SMT375 interfaces to the rest of the sub-systems through the metrology FPGA board
via three 80-pin connectors. The signal descriptions of these connectors are explained in
the metrology and communications sections which utilize them.
F.1.4 Metrology
Design Drivers
• Provide real-time position and attitude information of each satellite
• Implements measurement circuitry for metrology
- One infrared transmitter command (protected)
- 12 infrared receiver channels
- 24 ultrasound receiver channels
- Six 12-bit A/D channels, up to 1KHz
• Propulsion register (to control solenoid valves)
- 12 outputs with read-back capability
• General output register
- Two outputs with read-back capability
• General input register
- Two inputs
TABLE F.8 Features of the SMT375 board
Form Factor Single-width TIM40CPU TMS320C6701Speed 167MHzFLOPS 1 GFLOPS peakRAM 16MB (4M x 32)Cache 512k (128k x 32)Commports 6 x 20MBpsProgramming C and C++Power Consumption 7 W
APPENDIX F 449
Functional Block Diagrams
Because the metrology motherboard is the only board which interfaces directly with the
SMT375 DSP board, it functions not only to support metrology, but also to provide gen-
eral input/output signals and pass-through of the commports and power to the communica-
tions system. To implement these functions the metrology system centers its design
around an FPGA as pictured in Figure F.7. The system interfaces to the twelve US/IR
boards, the internal beacon, three gyroscopes, and three accelerometers (with amplifiers).
An EEPROM stores the configuration of the FPGA and interfaces to a JTAG port to
update the programming as necessary.
The four boards that support the metrology sub-system (motherboard, US/IR, accelerome-
ter amplifier, and internal beacon) are described next.
THR 1-12 Out Pass through signals for thrusters 1-12/Enable In Enable button signal/LED-enable Out Enable LED signal/Batlow In Low battery indicator signalWDOG Out Watchdog control signal/RESET In Reset
Data and power to SMT375
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundC[0-5] D[0-7] I/O Commport data linesCACK[0-5] I/O Commport acknowledge signalCRDY[0-5] I/O Commport ready signalCREQ[0-5] I/O Commport request signalSTRB[0-5] I/O Commport strobe/RESET Out Reset LineIR_RCV_INT Out Infrared reception interrupt. It is asserted
when an IR is received so the DSP can prepare for a global metrology cycle
PADS_INT Out 1kHz interrupt. Provides timing for the DSP and indicates IMU data is available.
A0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 Out Global bus readyPAGE1 In Global bus page selectSTRB1 In Global bus strobeR/W1 In Global bus read/write/CE1 Out Global bus control lines enable/OE Out Global bus data lines enable/AE Out Global bus address lines enable
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address lines (expansion port)D0-D31 I/O Global bus data lines (expansion port)RDY1 I/O Global bus ready (expansion port)PAGE1 I/O Global bus page select (expansion port)STRB1 Out Global bus strobe (expansion port)R/W1 I/O Global bus read/write (expansion port)/RESET Out Reset line/Exp_port_in In High when an expansion port selects to
bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]
In Input ultrasound signals from the expan-sion port board
IR-RX[11-12] In Input infrared signals from the expansion port board
EXP A2D [0-2] In Input analog signals from the expansion port board
All the grounds in this diagram must be one single
thick trace which connects the 470uF cap to the
IRL520N
Me
tro
log
y 6
- S
PH
-1-0
80
0-1
01
B
Bo
ard
Asse
mb
ly
A
13
Tu
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ay,
Fe
bru
ary
18
, 2
00
3
Title
Siz
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ocu
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nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
-2
US
Circu
it
US
Sig
na
l
US
-1
US
Circu
it
US
Sig
na
l
IR R
CV
US
RC
V 1
US
RC
V 2
IR X
MIT
IR X
MIT
VC
C(+
5V
)
VC
C(+
2.5
V)
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)
C1
4
4.7
uF
J1
IR P
AD
12345678
D1IR LED
C20.1uF
D2IR LED
R5
22K
C3 47
uF
JP
1
HE
AD
ER
10
1 2 3 4 5 6 7 8 9 10
R6
22K
D3
IRL
ML
25
02
3
1
2
R1100 Ohm R
4 1M
R2
74
7 O
hm
R21 Ohm
R31 Ohm
C1
3
0.1
uF
C4
4.7
uF
C1
4.7
uF
APPENDIX F 467
Each metrology board includes two of these circuits:5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Keep trace as short as possible
Piggyback parallel to Rf
Piggyback parallel to Rf
Me
tro
log
y 6
B
Sin
lge
US
Am
plif
ier
Ch
an
ne
l
A
23
Th
urs
da
y,
Ma
rch
06
, 2
00
3
Title
Siz
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ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(+
5V
)
VC
C(+
5V
)
VC
C(+
5V
)V
CC
(+5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)
VC
C(+
2.5
V)V
CC
(+5
V)
+ -
U1
C
LM
6154A
/SO
10 9
8
4 11
R1
410K
PO
T
13
2
+ -
U1
B
LM
6154A
/SO
5 67
4 11
+ -
U1
A
LM
6154A
/SO
3 21
4 11
D4
1N
91
4/S
O
R7
34K
R1
234K
C8
5p
R8
1M
R1
168K
D51N914/SO
C6
0.2
70
n
C7
5p
R1
0
10K
C5
10n
R1
668K
R1
3220K
J2
US
1
1 2
R9
68K
R1
51
M
+ -U
1D
LM
6154A
/SO
12
13
14
4 11
US
Sig
na
l
468 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Acce
l P
CB
- S
PH
-1-0
80
0-2
05
B
Acce
lero
me
ter
Bu
ffe
r/A
mp
lifie
rs
A
11
We
dn
esd
ay,
Se
pte
mb
er
18
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
VC
C(5
V)
VC
C(-
15
V)
VC
C(1
5V
)
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)
VC
C(5
V)
VC
C(-
15
V)
R7
10
.0k
R5
10
0k
J1
Acce
l
12345678
R9
56
.2k
-+
U2
MA
X409
3 26
7 451
R6
2k
C1
470p
R4
10
0k
R1
10
2k
QA-750
U1
QA
-750
1 3 4678
Ou
t
-V +V
Te
mp
Te
st
GN
D
R3 10
0k
13
2
R8
10
0k
R2
4.0
2M
APPENDIX F 469
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-08
00
-70
2-
Pro
ce
sso
r
A
12
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
NU
M1
NU
M3
NU
M2
NU
M0
IR_
RC
V
/MC
LR
US
_X
MIT
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
VC
C(1
5V
)
R2
C3
.1u
TP
1
IR_
RC
V
1
U1
PIC
16
C5
05
1 2 3 4 5 6 7891
0
11
12
13
14
Vcc
CL
K_
INC
LK
_O
UT
RB
3
RC
5R
C4
RC
3R
C2
RC
1R
C0
RB
2R
B1
RB
0
GN
D
D1 Sta
t L
ED
TP
2
GN
D
1
R3
R1
470
Y1
40M
Hz
4
3
2
1
VCC OU
T
GND
E/D
R5
JP
1
HE
AD
ER
101 2 3 4 5 6 7 8 9
10
R4
10
k
470 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-08
00
-70
2-
US
Tra
nsm
itte
r
A
22
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
US
_X
MIT
-U
S_X
MIT
+
US
_X
MIT
VC
C(5
V)
VC
C(1
5V
)
R7
10
k
R6
10
k
R8
100
U3
CD
40
93
1 23 4
5 6
7
8 91
0
11
12
13
14
1A
1B
1Y
2Y
2A
2B
GND
3A
3B
3Y
4Y
4A
4B
Vcc
Q1
2N
39
04
C
B
E
TP
3
US
_X
MIT
1
C1
47
uF
U4
US
Xm
it
1 2
C2
.1u
F
U2
LM
3480-1
2/S
OT
23
21
3
INO
UT
GND
APPENDIX F 471
F.1.5 Communications
Design Drivers
• Two wireless communications channels
- Satellite to Laptop (STL) - Telemetry and Commands
- Satellite to Satellite (STS) - Control and Commands
• Support at least three satellites
• Should be expandable
• Accommodate a minimum volume of 6’ x 6’ x 6’
• Highest data rate possible
• Low power
Functional Block Diagrams
Figure F.11 presents the functional block diagram of the communications sub-system. The
major elements of the communications sub-system are three PIC processors that translate
TI Commport signals into standard 8-bit (plus start and stop bit) UART serial data and two
DR200x modules (one each for Satellite-to-Laptop STL and for Satellite-to-Satellite
STS communications) which convert the 8-bit UART data into 14-bit bit-balanced
words to minimize errors during wireless transmissions. The two elements are described
below.
DR200x Wireless Boards
The DR2000 development kit is a COTS product available from RFM Monolithics in. The
kit utilizes an ARM DSP to manage data for wireless transmissions. The ARM performs
four functions:
• Creates 12-bit bit-balanced words for every byte to be transmitted. Bit bal-anced words contain the same number of ones and zeros to reduce the errorrate in wireless transmission.
• Manages packets of a pre-set size. The DR200x can be configured to sendfixed sized packets immediately once the fixed number of bytes arereceived; alternatively, it will transmit a packet if there is a pause longer than2ms between bytes.
472 APPENDIX F
• Adds a start header to all transmissions which allows the crystals in thereceiving end to resonate at the correct frequency before the actual dataarrives.
• Allows identification of each module individually, so that data can bedirected to a specific DR200x board.
The basic features of the DR200x boards are listed in Table F.10. Table F.11 describes the
signals of the DR2000x.
To improve the bandwidth of the system, though, SPHERES uses custom firmware.
Therefore, while [RFM, URL] provides an overview of the hardware used in the board,
Appendix H should be consulted to understand the operations of firmware. Further, to
Section Signal Type DescriptionTo/From Metrology Mother-board
Vcc(+5V) Pwr +5V powerVcc(+3.3V) Pwr +3.3V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 In Global bus address lines (expansion port)D0-D31 I/O Global bus data lines (expansion port)RDY1 I/O Global bus ready (expansion port)PAGE1 I/O Global bus page select (expansion port)STRB1 In Global bus strobe (expansion port)R/W1 I/O Global bus read/write (expansion port)/RESET In Reset line/Exp_port_in Out Expansion port item indicatorIR_XMIT In IR transmit commandUS-RX[11-12]-[1-2]
Out Input ultrasound signals from the expan-sion port board
IR-RX[11-12] Out Input infrared signals from the expansion port board
EXP A2D [0-2] Out Analog signals from expansion portC[1,2,4] D[0-7] I/O Commport data linesCACK[1,2,4] I/O Commport acknowledge signalCRDY[1,2,4] I/O Commport ready signal
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 I/O Global bus readyPAGE1 I/O Global bus page selectSTRB1 Out Global bus strobeR/W1 I/O Global bus read/write/RESET In Reset line/Exp_port_in In High when an expansion port selects to
bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]
In Input ultrasound signals
IR-RX[11-12] In Input infrared signalsEXP A2D [0-2] In Input analog signalsEXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)
Wired Serial Con-nector
EXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)GND Pwr Common Ground
DR200x (2x)
Vcc(+3.3V) Pwr +3.3V powerGND Pwr Common groundRX Out Serial data receive lineTX In Serial data transmit line/RST In Reset
The schematics of the DR200x boards are available in [RFM, URL]. The schematics of
the SPHERES communications motherboard are presented next.
APPENDIX F 477
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
Co
mm
Bo
ard
Co
nn
ecto
rs
A
15
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D2
5
A28
/RD
Y1
A27
A4
D6
/ST
RB
1
D2
9
A30
D1
7
A5
D7
D3
1
/AE
R/W
1
A24
D2
4
A21
A18
A6
D8
D0
D2
0
/DE
D1
5
D2
1
A7
D9
D1
2
D1
ST
AT
0
D1
9
D1
1
A26
D3
0
A25
A15
A8 D2
3
A0
D2
ST
AT
1
A20
D2
8
A10
D2
2
A14
A19
A9
A1
D3
ST
AT
2
D1
0
A13
D2
7
D1
4
/LO
CK
A29
A2
A17
A12
D4
A11
ST
AT
3
D1
3
D1
6
A22
A3
D5
A23
A16
PA
GE
1
/CE
1
D1
8
D2
6
C4
-D3
C2
-D3
C2
-D0
CS
TR
B2
C1
-D3
C2
-D7
C1
-D0
CR
EQ
1
CR
EQ
2
C2
-D2
C1
-D7
C2
-D6
CS
TR
B1
C1
-D2
C4
-D7
C1
-D6
C2
-D1
CR
DY
2
CS
TR
B4
CR
EQ
4
C4
-D5
C2
-D5
CR
DY
1
CA
CK
1
C4
-D2
C1
-D5
CR
DY
4
CA
CK
2
C4
-D4
C4
-D0
C2
-D4
C4
-D6
C1
-D4
CA
CK
4
C4
-D1
C1
-D1
IR-R
X1
1
US
-RX
12-2
US
-RX
11-1
US
-RX
12-1
IR_X
MIT
IR-R
X1
2
US
-RX
11-2
EX
P A
2D
0
EX
P A
2D
1
EX
P A
2D
2
IR_
RC
V_
INT
/RE
SE
TE
xp
-Po
rt-I
n
VC
C(-
15
V)
VC
C(5
V)
VC
C(3
.3V
)
VC
C(1
5V
)
JP
1 Co
mm
Co
mm
Po
rts
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
2 Co
mm
Glo
ba
l
1 2 3 4 5 6 7 8 91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
83
94
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
JP
3
Co
mm
PW
R
12
34
56
78
91
01
11
21
31
41
51
61
71
81
92
02
12
22
32
4
478 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
Exp
an
sio
n P
ort
Co
nn
ecto
rs
A
25
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
D1
D9
D2
7
D1
9
D2
9
D2
D1
3
D3
D2
2
D1
4
D1
0
D4
D2
3
D1
5
D3
0
D1
1
D5
D6
D2
4
D1
6
D3
1
D1
2
D2
8
D7
D2
5
D1
7
D2
0
D0
D8
D2
6
D1
8
D2
1
US
-RX
11-1
IR-R
X1
1
IR-R
X1
2
US
-RX
12-1
US
-RX
12-2
US
-RX
11-2
IR_X
MIT
EX
P-R
XE
XP
-TX
Exp
-Po
rt-I
n
A30
A17
A13
/RD
Y1
A11
A26
A14
A8
A6
A22
A18
A5
A3
A20
PA
GE
1
/CE
1
A28
A0
A10
A1
A27
A23
A7
/ST
RB
1
A29
A9
R/W
1
A25
A16
A15
A4
/LO
CK
A19
A24
A21
A12
A2
EX
P A
2D
1
EX
P A
2D
0
EX
P A
2D
2
/RE
SE
T
VC
C(-
15
V)
VC
C(5
V)
VC
C(1
5V
)
J3
Exp
PW
R
1 2 3 4 5 6
J1
Exp
1
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J2
Exp
2
1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
APPENDIX F 479
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
- E
xp
an
sio
n B
us S
eria
l P
ort
A
35
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
OS
C-P
IC-2
OS
C-P
IC-1/R
ES
ET
C4
-D0
C4
-D1
C4
-D2
C4
-D3
C4
-D4
C4
-D5
C4
-D6
C4
-D7
EX
P-R
XE
XP
-TX
CS
TR
B4
CR
DY
4C
AC
K4
CR
EQ
4
VC
C(5
V)
VC
C(5
V)
VC
C(5
V)
C2
1 u
F
R2
2
50
C7
.1u
C3
1 u
F
RS232
TTL
U2
DS
14
C2
32
13
81
1
10
1 3 4 5 2 6
12 9
14
7
16 15
R1
IN
R2
IND
1IN
D2
IN
C1
+C
1-
C2
+C
2-
V+ V-
R1
OU
T
R2
OU
TD
1O
UT
D2
OU
T
VCC GND
R2
3
50
U1
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
C1 1 u
F
J6
HE
AD
ER
3
1 2 3
R1
10
kR
31
0k
R2
0
50
R2
10
k
C4 1 u
F
R4
10
kR
21
50
480 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
1 -
ST
L C
om
mu
nic
atio
ns C
ha
nn
el
A
45
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
RS
T2
RX
2T
X2C
2-D
0C
2-D
1C
2-D
2C
2-D
3C
2-D
4C
2-D
5C
2-D
6C
2-D
7/R
ES
ET
OS
C-P
IC-2
OS
C-P
IC-1
OS
C-P
IC-1
OS
C-P
IC-2
CR
DY
2C
AC
K2
CS
TR
B2
CR
EQ
2
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)
C8
.1u
U3
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
R2
7
50
R5
10
k
C5
22
pF
R8
10
kR
61
0k
R2
4
50
R9
10
J4
ST
L C
om
m
123456
R2
5
50
Y1
20.0
MH
z
R7
10
k
C6
22
pF
R2
6
50
APPENDIX F 481
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
MB
2:
Co
mm
- S
PH
-1-0
80
0-2
13
A
UA
RT
1 -
ST
G C
om
mu
nic
atio
ns C
ha
nn
el
A
55
Th
urs
da
y,
Octo
be
r 1
0,
20
02
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
RX
1T
X1
RS
T1
/RE
SE
T
C1
-D1
C1
-D0
C1
-D2
C1
-D3
C1
-D4
C1
-D5
C1
-D6
C1
-D7
OS
C-P
IC-2
OS
C-P
IC-1
CA
CK
1
CR
EQ
1
CS
TR
B1
CR
DY
1
VC
C(5
V)
VC
C(5
V)
VC
C(3
.3V
)
U4
PIC
16
C6
6
1 2 3 4 5 6 7
8
91
0
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
/MC
LR
RA
0R
A1
RA
2R
A3
RA
4/T
0C
KR
A5
/SS
GND
OS
C1
OS
C2
RC
0R
C1
RC
2R
C3
RC
4R
C5
RC
6/T
XR
C7
/RX
Vdd
RB
0R
B1
RB
2R
B3
RB
4R
B5
RB
6R
B7
R1
01
0k
R3
0
50
R1
21
0k
R1
11
0k
J5
ST
G
123456
R3
1
50
C9
.1u
R2
8
50
R1
31
0k
R2
9
50
482 APPENDIX F
F.1.6 Expansion Port
Design Drivers
• Provide digital interface for future expansions
Functional Block Diagrams
The broad requirements in the definition of the expansion port resulted in a design which
provides a simple but limited serial line capable of up to 1.25Mbps data rates as well as the
very flexible but complex global bus. Figure F.12 presents the functional block diagram
for the Expansion Port.
Figure F.12 Expansion port functional block diagram
CommMB
PIC &RS232
CommPort 412
Expansion Port
2
MetrologyMB
DSP
Power
A/D
FPGA
Global Bus69
3
US/IR
EXP_in
Analog in
Reset
FX-8
0 C
onne
ctor
UART(RS232)
Reset
EXP_in
IR_xmit
US/IR 12US/IR 11
US-RX11
IR-RX11
US-RX11
IR-RX12
APPENDIX F 483
Apart from providing the required digital data lines, the Expansion Port also supports
three other functions:
• Provides power to expansion items via +5V, +15V, and -15V power lines. Itprotects these lines with 0.5A self-resetable fuses.
• Because three analog lines were available from the basic metrology design,the expansion port makes these lines available to expansion items.
• Allows an expansion item to bypass the internal US/IR metrology boardslocated on the expansion port face (+X face). This allows an expansion itemto replace the functionality of those boards if the expansion item covers thesensors. The expansion board uses high-speed multiplexers so that the sig-nals received by the FPGA are equivalent to any other US/IR signals. TheEXP_in line allows the DSP to account for the new physical locations(which must be programmed) of the US/IR boards when the signals havebeen bypassed.
Table F.13 describes the inputs and outputs of the Expansion Port.
TABLE F.13 Expansion port signals description
Section Signal Type DescriptionTo/From Comm. Mother-board
See Table F.12
Expansion Port Con-nector
Vcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerVcc(-15V) Pwr -15V powerGND Pwr Common groundA0-A30 Out Global bus address linesD0-D31 I/O Global bus data linesRDY1 I/O Global bus readyPAGE1 I/O Global bus page selectSTRB1 Out Global bus strobeR/W1 I/O Global bus read/write/RESET In Reset line
484 APPENDIX F
Expansion Port (cont)
/Exp_port_in In High when an expansion port selects to bypass the satellite US/IR metrology boards
IR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]-EXT
In External sensor input ultrasound signals
IR-RX[11-12]-EXT
In External sensor input infrared signals
EXP A2D [0-2] In Input analog signalsEXP RX In Serial data receive (RS232)EXP TX Out Serial data transmit (RS232)
Metrology Pass-through(2x)
Vcc(+5V) Pwr +5V powerGND Pwr Common groundIR_XMIT Out IR transmit commandUS-RX[11-12]-[1-2]-INT
In Internal sensor input ultrasound signals
IR-RX[11-12]-INT
In Internal sensor input infrared signals
TABLE F.13 Expansion port signals description
Section Signal Type Description
APPENDIX F 485
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-0
80
0-7
01
-
Exte
rna
l C
on
ne
cto
rs
A
13
Tu
esd
ay,
Se
pte
mb
er
17
, 2
00
2
Title
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
A0
8
EX
P A
2D
0
EX
P A
2D
1
/LO
CK
A2
7
PA
GE
1
A0
7
A1
0
A2
1
A0
9
/ST
RB
1/R
DY
1
A1
4
A0
2
A3
0
A1
1
A0
0
A2
5
A2
8
A2
0
A1
5
A1
2
A0
3
A1
6
A0
4
A2
9
A2
4
R/W
1
EX
P A
2D
2
A0
6
/CE
1
A1
9
A0
5
A2
6
A0
1
A2
3
A1
7A
18
A2
2
A1
3
D0
3
D2
4
D0
0
D3
1
D0
7
D2
9
D1
8
D0
1
D2
3
D2
5
D1
9
D2
7
D1
6
D1
3
D0
4
D2
2
D0
9D
08
D0
6
D1
7
D1
1
D2
6
D1
0
D2
1
D1
5D
14
D3
0
D2
0
D0
2
D2
8
D0
5
D1
2
US
-RX
-12-1
-EX
T
IR-R
X-1
1-E
XT
IR-R
X-1
2-E
XT
US
-RX
-11-1
-EX
TU
S-R
X-1
1-2
-EX
T
US
-RX
-12-2
-EX
T
IR_X
MIT
Exp
-Po
rt-I
nE
XP
-TX
EX
P-R
X/R
ES
ET
VC
C(-
15
V)
VC
C(5
V)
VC
C(1
5V
)
R1
1M
F2
.2A
F3
.2A
F1
.2A
JP
1
EX
80-1
00
1 3 5 7 9
112 4 6 8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
PW
R1
3 5 7 9 11
PW
R2
4 6 8 10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PW
R5
1
PW
R5
2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
486 APPENDIX F
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
-1-0
80
0-7
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APPENDIX F 487
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Exp
an
sio
n P
ort
- S
PH
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488 APPENDIX F
F.2 Laptop Communications
Design Drivers
• Interface with standard equipment available on the ISS SSC
Functional Block Diagrams
The laptop transceiver is a modified DR2001 (868.35MHz) development kit (the backup
is a DR2000, 916.5MHz). The transceiver uses the custom firmware developed for
SPHERES and does not use the power regulation circuit. The power regulation has been
replaced with two diodes which step down the +5V voltage of a USB port of the SSC to
approximately 3.6V, the maximum allowed by the DR200x without power
circuitry.Figure F.13 presents the functional block diagram of the laptop communications.
[RFM, URL] provides information on the hardware design, and Appendix H on the firm-
The Expansion Port beacon was developed to allow formation flight algorithms where
each satellite can transmit an ultrasound signal from two opposite sides: one using the on-
board beacon (-X) and another using the expansion port (+X). The expansion port beacon
replicates the internal beacon, but uses the serial line in the expansion port instead of it
own IR or the use of the IR_rcv_int line which is not available to expansion items. The
firmware in the expansion port beacon accounts for the extra delay in serial communica-
tions to initiate the command so that the receiving units do not need to account for the
delay. The functional block diagram of the expansion port beacon is presented in
Figure F.16. Table F.14 describes the inputs and outputs of this expansion item.
Figure F.16 Expansion port beacon functional block diagram
TABLE F.14 Expansion port beacon signals description
Signal Type DescriptionVcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V powerGND Pwr Common GroundTX In Transmit data line (RS232)/RESET In Reset line
RS232
US TXDriverPIC
16C505
ID SW 4
+12V Reg
PWR /Active
APPENDIX F 501
Schematics5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
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Be
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n -
SP
H-1
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65
R5
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502 APPENDIX F
5 5
4 4
3 3
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1 1
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CC
BB
AA
Exp
an
sio
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- S
PH
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1
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4
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2
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1
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80-1
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1 3 5 7 9
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R1
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APPENDIX F 503
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SP
HE
RE
Be
aco
n -
SP
H-1
-10
00
-10
1-
US
Tra
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to
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US
_X
MIT
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S_X
MIT
+
US
_X
MIT
VC
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VC
C(1
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)
R7
10
k
R6
10
k
R8
100
U4
CD
40
93
1 23 4
5 6
7
8 91
0
11
12
13
14
1A
1B
1Y
2Y
2A
2B
GND
3A
3B
3Y
4Y
4A
4B
Vcc
Q1
2N
39
04
C
B
ET
P3
US
_X
MIT
1
C6
47
uF
US
1
US
Xm
it
1 2
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U3
LM
3480-1
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23
21
3
INO
UT
GND
504 APPENDIX F
F.5.2 Expansion Port Tether
The Expansion Port Tether mechanism is a prototype system to test control algorithms for
tethered formation flight spacecraft. The mechanism uses the expansion port serial line to
interface with a COTS pulse-width-modulation driver board, which drives a motor to
extend or retract a monofilament tether which connects two satellites. This prototype does
not have any sensors, allowing the design to be very simple.
Figure F.17 shows the functional block diagram of the expansion port tether board. The
board uses a SMC02B micro serial motor controller by Pololu Corporation ([Pololu,
URL]). A serial line commands the micro controller the speed and direction of the motor.
An adjustable (manual) voltage regulator in the expansion board allows testing of several
motors at voltage ranges between 6.5V to 9V. Table F.15 describes the expansion port sig-
nals used by the expansion tether board.
Figure F.17 Expansion port tether functional block diagram
TABLE F.15 Expansion port tether signals description
Signal Type DescriptionVcc(+5V) Pwr +5V powerVcc(+15V) Pwr +15V power - regulated to +7V for motorGND Pwr Common GroundTX In Transmit data line (RS232)/RESET In Reset line