Software Engineering 2DA4 Slides 7: Synchronous …leduc/slides2d04/2da4slides7.pdf · Shift registers and counters are two examples. ... 3−bit Register 7−Segment Decoder ...

Software Engineering 2DA4

Slides 7: Synchronous Sequential Circuits

Dr. Ryan Leduc

Department of Computing and Software

McMaster University

Material based on S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Ed.

c©1999-2017 R.J. Leduc, M. Lawford 1

Synchronous Sequential Circuits

◮ Sequential circuits include flip-flops as well as logic gates.

◮ A flip-flop stores either a 0 or a 1, which is called the state ofthe flip-flop.

◮ Thus, in sequential circuits, outputs depend on current valuesof the inputs and the state of flip-flops.

DefinitionA Synchronous Sequential circuit is a circuit in which flip-flops aretied to a common clock.

◮ Shift registers and counters are two examples.


Synchronous Sequential Circuits - II◮ The flip-flop outputs are referred to as the present state, Q,

of the circuit.

◮ After each clock pulse the state can change to the next state,depending upon:1. the value of the inputs

2. the current state Q

◮ Synchronous sequential circuits typically have:

Flip-Flops: Flip flops containing current state Q

A: Combinationalcircuit computesnext state fromstate Q and inputs

B: Combinational cctthat computesoutputs.


Synchronous Sequential Circuits - III

◮ Circuit changes from one state to another state according tocombinational circuit A.

◮ The outputs of the seq. circuit are provided by combinationalcircuit B.

◮ Outputs may be a function of:

1. the current state Q

2. the values of inputs (optional)


Moore & Mealy Implementations

◮ A Moore-type circuit is when the outputs Z are a functiononly of the current state Q. In other words, when inputs arenot used for circuit B.

◮ A Mealy-type circuit is when Z is a function of Q and thecurrent inputs W . In other words, when inputs are used forcircuit B.

◮ Both types of circuits are referred to as finite state machines(FSM).


Example of a Simple Moore FSM◮ Design a circuit with the following specs:

1. Single input w and single output z

2. All changes in circuit occur on the positive edge of the clock

3. If during the two immediately preceding clock intervals w was1, then z = 1, otherwise z = 0.

◮ Example Sequence:

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9w 0 1 0 1 1 0 1 1 1 0

z 0 0 0 0 0 1 0 0 1 1

◮ We will try to use informal design process:

i) determine how many possible states we need for cct

ii) determine which transitions from one state to another arepossible

◮ See design on board in class.c©1999-2017 R.J. Leduc, M. Lawford 6

Designing Moore Finite State Machine

Step 1: Identify the inputs to the state machine.

◮ Every state machine has a clock input.

◮ On the rising edge of the clock signal (clock signal transitionsfrom 0 to 1), the state machine samples the inputs, and thencan change state.

◮ Each state machine also has a reset input. If the reset signalis active high, then when reset = 1, the state machine willimmediately (without waiting for the next clock edge) switchto its predefined reset state (see step 3).

Step 2: Indentify the outputs of the state machine.

◮ These outputs provide information and/or instructions to therest of the circuit.

◮ For a Moore state machine, outputs are a function only of thecurrent state.


Designing Moore Finite State Machine - II

Step 3: Define the reset state for your state machine.

◮ Your state machine must always start from a known state, thereset state (initial state).

Step 4: Determine the sequence of states and output values for thesestates necessary to perform the desired task.

◮ Draw state diagram.


State Diagram Notes From Board Discussion◮ State diagrams are usually your starting point for designing

FSM.

◮ Don’t forget to add the Reset (if active high) or Resetn (ifactive low signal) arrow to the initial state of FSM like theexample on the board.

◮ Transitions between states are labelled by values of theprimary inputs, often by boolean equations such as w1 · w2.

◮ All FSM have a clock and Reset (Resetn) inputs, but they arenot primary inputs and are not part of next-state logic.

◮ For a given state, there must be a transition leaving that statethat matches every possible primary input combination (i.e.transition function is a total function).

◮ Each primary input valuation must match exactly onetransition leaving a given state; no overlap!


Simple Moore FSM: State Table

◮ Useful for implementation to have information in tabular formas below.


A Mealy Simple Example

◮ Design a circuit with the following specs:

1. Single input w and single output z

2. All changes in circuit occur on the positive edge of the clock

3. If during the immediately preceding clock cycle w was 1 and w

is still 1 during the current clock cycle, then z = 1, otherwisez = 0.

Example Sequence:

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9w 0 1 0 1 1 0 1 1 1 0

z 0 0 0 0 1 0 0 1 1 0


A Mealy Simple Example: Informal Design◮ Thought process:

◮ Choose a starting state (A).

◮ if w = 0, no action needed; stay in (A): z = 0.

◮ if w = 1, move to new state (B): z = 0.

◮ When in (B):◮ if w = 0, z should be 0, go to (A).

◮ if w = 1, z should be 1, stay in (B).

◮ We only need two states now!

◮ State table for a Mealey FSM.Present Next State Output zState w = 0 w = 1 w = 0 w = 1

A A B 0 0B A B 0 1


Procedural Verilog Statements

◮ So far, have seen only concurrent Verilog statements that aredesigned to execute in parallel.

◮ In order to represent a cuircuit’s behavior in a powerful way,Verilog also supports procedural (sequential) statements(Appendix A.11).

◮ Procedural statements are evaluated in the order they occur.

◮ Procedural statement are only permitted inside an alwaysblock.

◮ In particular, if-else and case statements must go inside analways block.


Always Block◮ The general form of an always block is given below.◮ When a block contains multiple statements, they must be

surrounded by a begin and end pair.◮ The sensitivity list is a list of signals that affect when the

always block list is evaluated.◮ When any signal in the list changes value, the statements in

block are evaluated once in order.◮ If a signal is assigned a value more than once, the last value is

retained.◮ A signal assigned inside an always block is retained until the

block is revaluated. It has “implied memory.”


Always Block - II◮ A signal assigned a value within an always block must be

either of type reg or integer.

◮ There are two types of procedural assignment statements:blocking and nonblocking.

◮ For a blocking assigment (denoted by “=”), the left hand sidesignal takes on the value of the right hand before the next lineis evaluated, thus further references get the new value.

◮ For nonblocking assignments (denoted by “<=”), the value ofvariables when the always block is used, and variables don’ttake on updated values until the end of the block is reached.

◮ When a signal is assigned a value in an always block, thatvalue is remembered until the signal is assigned a new value.

◮ For combinational circuits, only use blocking assignments.

◮ For sequential circuits (synchronized to a clock signal), onlyuse nonblocking assignments.


If-Else Statements

◮ General form of an if-else statement shown below.

◮ The else-if and else portions are optional.


2-to-1 Multiplexor Code

◮ Below is an example of an always block and if statement.


Case Statements◮ General form of a case statement shown below.

◮ The bits in expression are checked for an exact match againstthe bits of each alternative.

◮ The statements of the first match are executed.

◮ Must add a default clause if not all possible valuations forexpression are given.


Moore FSM

◮ We will now give the Verilog code to represent the MooreFSM below, with an active low Reset.


Verilog for Moore FSM


Mealey FSM

◮ We will now give the Verilog code to represent the MealeyFSM below, with an active low Reset.


Verilog for Mealey FSM


Moore Design Example: Simple ALU◮ Design a Moore finite state machine that will control the

simple ALU below.

◮ The state machine should repeatedly prompt the user to entertwo 3-bit numbers, and have the ALU add the numbers ifinput OpType = 0 when the first number is stored, otherwisesubtract the second number from the first.

◮ Input Ready = 1 will signalto store data X.

◮ Assume RReset active high.

Op

Figure 1: Simple 3−bit ALU

3−bit Register

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3−bit Register

7−Segment Decoder

3−bit Add/Sub Circuit

RClock

RReset

Input x2 x 1 x0

RClock


Block Diagram for Simple ALU


State Diagram for Simple ALU

◮ See derivation of statediagram done in class.

◮ Design assumes thatReady input is a pulse(signal only stays activefor one clock period at atime).


Timing ALU◮ A useful design aid for a state machine is to first draw a

timing diagram with the inputs to the FSM (including clockand reset), and the desired output pattern.


FSM and Flip-Flops

◮ Below shows the general form of a four state Moore FSM.


Moore FSM and Flip-Flops

◮ We will now show how to implement with flip-flops the MooreFSM below, with an active low Reset.


Example FSM Implementation: Moore◮ To produce a circuit with logic gates and flip-flops, we need to

make a state assigned table.

◮ To build a circuit that implements this table, we need torepresent the states A,B,C using flip-flops.

◮ We need to decide how many flip-flops are needed and chooseunique patterns of 1’s and 0’s as the output of these flip-flopsfor each state.

◮ For 3 states, we need a minimum of 2 flip-flops (22 = 4 ≥ 3).

◮ Let y1 and y2 be flip-flop outputs and choose stateassignments to make reset and output mapping easier:

For (A) y2 = 0, y1 = 0 (z = 0)For (B) y2 = 0, y1 = 1 (z = 0)For (C) y2 = 1, y1 = 0 (z = 1)

◮ Note: y2 = 1, y1 = 1 are unused (don’t care conditions).c©1999-2017 R.J. Leduc, M. Lawford 29

Deriving Combinational Circuits◮ Let Y2 and Y1 be the next state values of y2 and y1

respectively.

◮ We need to derive logic circuits for Y2 and Y1 that are afunction of y2, y1, and w.

◮ Replacing (A), (B) & (C) in the state table on the left withtheir boolean representations, we obtain the state-assigned

table on the right that is equivalent to a truth table.


Deriving Combinational Circuits - II

◮ We can then use this table to obtain Y2 and Y1 using theusual synthesis methods.


Moore FSM Implementation


Moore FSM Implementation: Timing Diagram

◮ Below is timing diagram for previous circuit.


Alternate Moore FSM Implementation

◮ If we choose a different state assignment, we get a different,but equivalent circuit.

◮ Consider A = 00, B = 01, C = 11 and its correspondingimplementation below.

◮ Read Section 6.1.6 on your own.


Mealey FSM Implementation

◮ We will now show how to implement with flip-flops theMealey FSM below, with an active low Reset.

◮ Choosing A = 0 and B = 1 gives the state-assigned tablebelow.


Mealey FSM Implementation - II


Register Transfer Example

◮ Figure below shows two, 2-bit registers connected to acommon 2-bit bus, and having a common clock signal.

◮ For our application, we will assume we have a third register,R3, of the same form.


Register Transfer Example - II

◮ Let i = {1, 2, 3}. Register i has an active high Riout signalthat drives the contents of the register onto the bus(otherwise high impedance).

◮ Register i also has an active high Riin signal that loads (onthe next clock edge) the contents of the bus.


Register Transfer Example: Problem Definition

◮ Want to be able to swap the contents of registers R1, and R2,using R3 as temporary storage.

Transfer Sequence: R2 → R3

R1 → R2

R3 → R1

◮ Design a Moore FSM that has input w, and outputs Done,Riout, and Riin (i = {1, 2, 3}), that accomplishes this taskwhen w is set to 1.

◮ See design of state diagram in class on board.


Register Transfer Example: Tables

◮ Below is state table and state-assigned table for the example.

◮ As outputs are true at only one state (thus minterms), theycan be read off from the table.


Register Transfer Example: Next-State Equations

◮ As state-assigned table is essentially a truth table, you can useit to fill in the kmaps below.


Register Transfer Example: Sequential Circuit


Handshake Signals◮ Figure below shows a block diagram of the ALU we earlier

designed a FSM for, except we’ve added a new signal, Next.

◮ Signals Ready and Next together perform a “handshake”operation.

◮ This allows the FSM to synchronize its behavior correctly witha user, or another FSM (input FSM) in order to ensureaccurate data transfer.


Handshake Signals - II◮ When the ALU FSM needs a new value, it sets Next = 1, and

waits for the input FSM to set Ready = 1. This signals thatX input is valid.

◮ The input FSM will set X to its value, and set Ready = 1.

◮ The input FSM will keep the data valid until Next = 0.


Handshake Signals - III

◮ The ALU FSM will then latch the data, and then set Next =0, signalling that it is safe for the data to be removed.

◮ The input FSM will set Ready = 0 in the next clock cycleafter it sees Next = 0.


State Minimization for Moore FSM

◮ When designing complex state machines, often end up withredundant states.

◮ Reducing number of states means possibly fewer flip-flopsneeded, and less complex combinational circuits (next-stateand output logic).

◮ Means identifying states that are equivalent with respect tocurrent and future output values.

State Equivalence: Two states, Si and Sj , are equivalent if forevery possible input sequence, the same outputsequence will be produced regardless of whether Si orSj is the initial state.

◮ Our minimization method is based on showing that states arenot equivalent.


k-successors

◮ Suppose a FSM has single input w.

◮ If w = 0 at state Si and FSM then goes to state Su, we saythat Su is the 0-successor of Si.

◮ If w = 1 and the FSM goes to state Sv, then say that Sv isthe 1-successor of Si.

◮ We refer to the successors of Si as the k-successors.

◮ With one input, then k ∈ {0, 1}. With two inputs,k ∈ {00, 01, 10, 11} and so on. ie. all possible inputvaluations.

◮ From definition, if Si and Sj are equivalent, then theircorresponding k-successors must be equivalent.


Partitioning the States

◮ Our minimization procedure involves treating the states of aFSM as a set, and then breaking them down into partitions.

Partition: A partition consists of one or more blocks, whereeach block comprises a subset of states that may beequivalent, but states in a given block are notequivalent to states in other blocks.

◮ A state can only belong to one block at a time.

◮ No blocks may be empty.

◮ Every state must belong to a block.


Minimization Algorithm

1. Create initial partition P1 containing all states in FSM.

2. Form partition P2 by grouping states with same output values.

3. Form new partition by testing if the correspondingk-successors of states in a given block are all in a single block(ie. for a specific value of k).

Use current partition for testing, not new one being created.

Form new blocks so that all k-successors are in a single block.

4. Repeat step 3 until the new partition is the same as theprevious one.

5. Take each block as a state in new FSM, and construct newstate table.


Minimization Example

◮ Minimize Moore FSM below and produce a state table of theresult.

◮ See solution in class on board.


Formal Model for Sequential Circuits

◮ General model for a sequential circuit is shown below.

◮ Circuit has:

Input Vector: W = {w1, w2, . . . wn}

Output Vector: Z = {z1, z2, . . . zm}

Current State Vector: y =

{y1, y2, . . . yk}

Next State Vector: Y =

{Y1, Y2, . . . Yk}


Formal Model for Sequential Circuits - II◮ In feedback path, there are delay elements, such that vector y

is set to value Y , after time delay △s.

◮ For a synchronous sequential circuit, the delay element is theflip flop, and △ equals the clock period.

◮ As we’ll see with asynchronous sequential circuits, the delaycomes from the inherent gate delays of the circuit.


Software Engineering 2DA4 Slides 7: Synchronous …leduc/slides2d04/2da4slides7.pdf · Shift registers and counters are two examples. ... 3−bit Register 7−Segment Decoder ...

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