Single Event Latch-up Test

Single Event Latch-up Test

Arkadiusz Dawiec

14 May 2007 Arkadiusz Dawiec 2

SEL & SEU test setup

able to monitor 5 chips in parallel able to detect Single Events: Latch-up and Upset maximum test frequency – 1kHz (limited by PC LPT)

ParallelPort

Power Supply

5 Power Supplies, CLK, Data IO

Control D

ata,

CLK, Data IO

LatchUpTest Chip

14 May 2007 Arkadiusz Dawiec 3

SEL test – DUT (device under test)

Chip characteristic: 5 channels : 4 shift registers (64 D flip-flops), 1 IO register (IO pads) 5 independent power supply 2 versions of chip : 20µm and 14µm epitaxy

Standard Shift register

Standard 3B shift register

2 µm stretched register

5µm stretched register

[8;0] word of IO pads

14 May 2007 Arkadiusz Dawiec 4

SEL test – DUT cont.

Differences between registers STD & 3B – AMS standard cells 2µ & 5µ stretched registers – distance between complementary transistors was increased:

Standard cell2u Stretched cell

1.5 µm 3.5 µm

14 May 2007 Arkadiusz Dawiec 5

SEL test – place

Ion Energy [MeV] LET [MeV.cm2/mg]

Ar - 40 150 14,1

Ar - 40 (45 deg.) 150 19,94

Kr - 84 316 34

Xe - 132 459 55,9

CYClotron of LOuvain la NEuve (CYCLONE)

Used beams :

14 May 2007 Arkadiusz Dawiec 6

14 May 2007 Arkadiusz Dawiec 7

SEL test – cross sectionLatch-up Cross Section

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 10 20 30 40 50 60

LET [MeV.cm2/mg]

Cro

ss

Se

cti

on

[c

m2

]

Standard - epi 20u

3B - epi 20u

Streched 2u - epi 20u

Standard - epi 14u

3B - epi 14u

Streched 2u - epi 14u

• for 2u stretched cells latch-up hardness is 2 orders of magnitude better

• for 5u we didn’t observe any events